Failure judgment circuit, failure judgment method and resistive random access memory device
By designing a failure judgment circuit in the resistive variable storage device, and using the reference resistor gate circuit and the comparison circuit to compare the resistance values of the resistive variable storage unit and the reference resistor, the failure problems faced by the resistive variable storage device in large-scale applications are solved, and life extension and power consumption reduction are achieved.
Patent Information
- Application Number
- CN202411557385.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-04
- Publication Date
- 2025-03-11
AI Technical Summary
In large-scale applications, resistive variable storage devices face problems such as write errors, read interference, read errors and thermal stability, resulting in reduced life and increased power consumption.
A failure judgment circuit is designed, including a reference resistor gate circuit and a comparison circuit. By gated reference resistor circuit with different resistance values, it is connected to the resistor memory array, compares the resistance value between the resistor memory unit and the reference resistor, and outputs a failure judgment signal.
While judging whether the blocking memory unit is invalid, the number of erases is reduced, the life of the storage device is increased and the power consumption is reduced, thus facilitating the large-scale application of the blocking memory device.
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Figure CN119601057A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of storage technology, and in particular to a failure judgment circuit and a failure judgment method, and a resistive storage device. Background Art
[0002] Resistive Random Access Memory (RRAM) is a volatile or non-volatile memory that records and stores data information based on resistance changes. It has the characteristics of high speed and low power consumption, and can realize storage functions in a small size. The preparation process of resistive memory devices is highly compatible with the preparation process of traditional complementary metal oxide semiconductor (CMOS) circuits. In view of these advantages, resistive memory devices have become particularly important in the context of the current booming development of intelligent products and the Internet of Things. However, resistive memory devices also generally face problems such as write errors, read interference, read errors and thermal stability, which increases the difficulty of large-scale application of resistive memory devices. Summary of the invention
[0003] Based on this, the embodiments of the present disclosure provide a failure judgment circuit and a failure judgment method, and a resistive memory device, which can reduce the number of erase and write times while judging whether the resistive memory unit has failed, so as to increase the life of the resistive memory device and reduce the power consumption of the resistive memory device, thereby facilitating the large-scale application of the resistive memory device.
[0004] In order to achieve the above-mentioned purpose, in the first aspect, some embodiments of the present disclosure provide a failure judgment circuit, including a reference resistor gating circuit and a comparison circuit. The reference resistor gating circuit includes: at least two reference resistor circuits connected in parallel, and a control circuit respectively connected to each reference resistor circuit. Wherein, the resistance values of the reference resistors in different reference resistor circuits are different; the control circuit is used to independently gating each reference resistor circuit in response to a control instruction. The comparison circuit connects a resistive memory array and each reference resistor circuit; wherein the resistive memory array includes a plurality of resistive memory cells arranged in an array. The comparison circuit is configured to: compare the resistance value between the resistive memory cell and the reference resistor in the reference resistor circuit that is enabled, so as to output a failure judgment signal according to the comparison result of the resistance value between the resistive memory cell and the reference resistor.
[0005] In some embodiments of the present disclosure, the reference resistor gating circuit includes: a reference reference resistor circuit, a first reference resistor circuit, and a second reference resistor circuit. The reference reference resistor circuit includes a reference reference resistor and a reference switch circuit. The first reference resistor circuit includes a first reference resistor and a first switch circuit. The second reference resistor circuit includes a second reference resistor and a second switch circuit. Among them, the first end of the reference reference resistor, the first end of the first reference resistor, and the first end of the second reference resistor are all grounded, the second end of the reference reference resistor is connected to the comparison circuit through the reference switch circuit, the second end of the first reference resistor is connected to the comparison circuit through the first switch circuit, and the second end of the second reference resistor is connected to the comparison circuit through the second switch circuit. The reference switch circuit, the first switch circuit, and the second switch circuit are also connected to the control circuit respectively. The control circuit is configured to: gating the reference switch circuit to output the storage data of the resistive memory cell according to the resistance value relationship between the resistive memory cell and the reference reference resistor; and gating the first reference resistor circuit and / or the second reference resistor circuit to output the failure judgment signal according to the resistance value relationship between the resistive memory cell and the first reference resistor or the second reference resistor.
[0006] In some embodiments of the present disclosure, the resistance of the first reference resistor is greater than ten times the first average resistance of each resistive memory cell in a high resistance state, and the resistance of the second reference resistor is less than one tenth of the second average resistance of each resistive memory cell in a low resistance state.
[0007] In some embodiments of the present disclosure, the reference switch circuit and the first switch circuit include transistors of the first conductivity type. The second switch circuit includes a transistor of the second conductivity type. The control circuit includes: a first control circuit connected to the reference switch circuit and the second switch circuit respectively, and a second control circuit connected to the first switch circuit. The first control circuit is configured to: generate a reference control instruction to turn on the reference switch circuit, and generate a second control instruction to turn on the second switch circuit. The level signals of the reference control instruction and the second control instruction are opposite. The second control circuit is configured to: generate the first control instruction to turn on the first switch circuit.
[0008] In some embodiments of the present disclosure, the first conductive type transistor includes an NMOS transistor, and the second conductive type transistor includes a PMOS transistor; the first control circuit includes a first power supply circuit for providing a first high level signal and a first low level signal in a time-sharing manner, and the second control circuit includes a second power supply circuit for providing a second high level signal.
[0009] In a second aspect, some embodiments of the present disclosure further provide a failure judgment method, which can be applied to the failure judgment circuit described in any of the above embodiments. The failure judgment method includes: independently selecting a reference resistor circuit in a reference resistor selection circuit in response to a control instruction, wherein the reference resistor selection circuit includes at least two reference resistor circuits connected in parallel, and the resistance values of the reference resistors in different reference resistor circuits are different; comparing the resistance values between the resistive memory cells of the resistive memory cells in the resistive memory array and the reference resistors of the selected reference resistor circuit, and outputting a failure judgment signal according to the comparison result of the resistance values between the resistive memory cells and the reference resistors.
[0010] In some embodiments of the present disclosure, the reference resistor selection circuit includes: a base reference resistor circuit, a first reference resistor circuit, and a second reference resistor circuit; wherein, the response control instruction independently selects the reference resistor circuit in the reference resistor selection circuit, and compares the resistance between the resistive memory cell of the resistive memory cell in the resistive memory array and the reference resistor of the selected reference resistor circuit, and outputs a failure judgment signal according to the comparison result of the resistance between the resistive memory cell and the reference resistor, which may include the following steps.
[0011] Gate reference resistor circuit.
[0012] The resistance values of the resistive memory cell and the reference resistor in the reference resistor circuit are compared.
[0013] The storage data of the resistive memory cell is obtained according to the comparison result of the resistance value of the resistive memory cell and the base reference resistor.
[0014] The first reference resistor circuit or the second reference resistor circuit is selected.
[0015] The resistance values of the resistive memory unit and the first reference resistor in the enabled first reference resistor circuit or the second reference resistor in the enabled second reference resistor circuit are compared.
[0016] A failure judgment signal is outputted according to a comparison result of the resistance value between the resistive memory unit and the corresponding first reference resistor or the second reference resistor.
[0017] When the failure judgment signal is a non-failure signal, the storage data of the resistive memory unit is output.
[0018] In some embodiments of the present disclosure, the resistance of the first reference resistor is greater than ten times the first average resistance of each resistive memory cell in a high resistance state, and the resistance of the second reference resistor is less than one tenth of the second average resistance of each resistive memory cell in a low resistance state.
[0019] Correspondingly, the failure judgment signal is output according to the comparison result of the resistance value between the resistive memory unit and the corresponding first reference resistor or the second reference resistor, including: when the resistance value of the resistive memory unit is greater than the first reference resistor, the failure judgment signal of the resistive memory unit is output as an open circuit failure; when the resistance value of the resistive memory unit is less than the second reference resistor, the failure judgment signal of the resistive memory unit is output as a short circuit failure.
[0020] In some embodiments of the present disclosure, the reference reference resistor circuit further includes a reference switch circuit connected to the reference reference resistor. The first reference resistor circuit further includes a first switch circuit connected to the first reference resistor. The second reference resistor circuit further includes a second switch circuit connected to the second reference resistor. The control circuit includes: a first control circuit connected to the reference switch circuit and the second switch circuit respectively, and a second control circuit connected to the first switch circuit.
[0021] Correspondingly, the switching on the reference resistor circuit includes: a first control circuit sends a reference control instruction to a reference switch circuit to switch on the reference switch circuit.
[0022] The method of switching on the first reference resistor circuit or the second reference resistor circuit includes: the second control circuit sends a first control instruction to the first switch circuit to switch on the first switch circuit; or the first control circuit sends a second control instruction to the second switch circuit to switch on the second switch circuit.
[0023] Furthermore, the level signals of the reference control instruction and the second control instruction are opposite.
[0024] In a third aspect, some embodiments of the present disclosure further provide a resistive memory device, comprising: a resistive memory array, and a failure judgment circuit connected to the resistive memory array and as described in any of the above embodiments.
[0025] The embodiments of the present disclosure may or at least have the following advantages:
[0026] In the embodiment of the present disclosure, by setting a reference resistor gating circuit, specifically, setting at least two reference resistor circuits connected in parallel and a control circuit connected to each reference resistor circuit respectively, and making the resistance values of the reference resistors in different reference resistor circuits different, each reference resistor circuit is connected to the resistive memory unit through a comparison circuit, so that the control circuit can respond to the control instruction to independently select different reference resistor circuits, thereby by comparing the resistance value between the resistive memory unit and the reference resistor in the selected reference resistor circuit, it is possible to output a failure judgment signal according to the comparison result of the resistance value between the resistive memory unit and the reference resistor. Therefore, the embodiment of the present disclosure outputs a failure judgment signal by selecting different reference resistors to compare the resistance values with the resistive memory unit, which can avoid adding two erase and write actions for failure judgment each time data is stored, so that the number of erase and write times can be reduced while judging whether the resistive memory unit is failed, so as to increase the life of the resistive memory device, reduce the power consumption of the resistive memory device, and thus facilitate the large-scale application of the resistive memory device.
[0027] The details of one or more embodiments of the present disclosure are set forth in the following drawings and description. Other features, objects, and advantages of the present disclosure will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0029] Figure 1 It is a structural schematic diagram of a failure judgment circuit provided in some embodiments;
[0030] Figure 2 It is a structural schematic diagram of another failure judgment circuit provided in some embodiments;
[0031] Figure 3 is a structural schematic diagram of another failure judgment circuit provided in some embodiments;
[0032] Figure 4 A schematic diagram of the distribution of a range of values of a benchmark reference resistor provided in some embodiments;
[0033] Figure 5 A schematic flow chart of a failure judgment method provided in some embodiments;
[0034] Figure 6A schematic flow chart of another failure judgment method provided in some embodiments.
[0035] Description of reference numerals:
[0036] 1-reference resistor selection circuit, 11-reference resistor circuit, 11A-reference reference resistor circuit, Rref-reference reference resistor, 111-reference switch circuit, 11B-first reference resistor circuit, R1-first reference resistor, 112-first switch circuit, 11C-second reference resistor circuit, R2-second reference resistor, 113-second switch circuit, 12-control circuit, 12A-first control circuit, 12B-second control circuit, 2-comparison circuit, 3-resistive storage array, SA-read sense amplifier. DETAILED DESCRIPTION
[0037] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.
[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.
[0039] It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below can be represented as a second element, component, region, layer or part.
[0040] It should be understood that when an element is considered to be "connected" to another element, it can be directly connected to the other element, or connected to the other element through an intermediate element. In addition, the "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc. if there is transmission of electrical signals or data between the connected objects.
[0041] It should be understood that the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.
[0042] In the related art, the resistive memory device is manufactured based on the technical principle that the resistive memory unit can realize reversible conversion between the high resistance state and the low resistance state. Moreover, in the application of digital circuits, the resistive memory unit can output data 1 when it is in the high resistance state, and can output data 0 when it is in the low resistance state. Secondly, when judging whether the state of the resistive memory unit is a high resistance state or a low resistance state, it is usually necessary to set a reference resistor to distinguish the high resistance state or the low resistance state of the resistive memory unit, and the reference resistor is usually between the high resistance state resistance value and the low resistance state resistance value of the resistive memory unit. Then, since the basic structure of the resistive memory unit in the resistive memory device is usually composed of a phase change material and a lower electrode and an upper electrode respectively connected to the phase change material, and the phase change material is often a non-conductive insulating layer film, when the resistive memory unit in the resistive memory device fails, it will present two states of open circuit failure or short circuit failure.
[0043] For example, if the resistive memory cell exhibits an open failure, data 1 will be read regardless of whether the resistive memory cell is written with data 0 or data 1. Similarly, if the resistive memory cell exhibits a short failure, data 0 will be read regardless of whether the resistive memory cell is written with data 0 or data 1.
[0044] In some embodiments, in order to determine whether the resistive memory cell is failed, data 0 and data 1 need to be repeatedly written, and the failure state of the resistive memory cell is determined by data reading. However, such an operation requires adding two erasing and writing actions for failure judgment each time data is stored (for example, writing data 0 and reading data 1), which easily leads to a large number of repeated erasing and writing times of the resistive memory device, for example, up to about 1E8 times, which not only reduces the life of the resistive memory device, but also easily increases the power consumption of the resistive memory device.
[0045] Based on this, the embodiments of the present disclosure provide a failure judgment circuit and a failure judgment method, and a resistive memory device, which can reduce the number of erase and write times while judging whether the resistive memory unit has failed, so as to increase the life of the resistive memory device and reduce the power consumption of the resistive memory device, thereby facilitating the large-scale application of the resistive memory device.
[0046] See also Figure 1 Some embodiments of the present disclosure provide a failure judgment circuit, including a reference resistor selection circuit 1 and a comparison circuit 2. The reference resistor selection circuit 1 includes: at least two reference resistor circuits 11 connected in parallel, and a control circuit 12 respectively connected to each reference resistor circuit 11. The resistance values of the reference resistors in different reference resistor circuits 11 are different; the control circuit 12 is configured to independently select each reference resistor circuit 11 in response to a control instruction. The comparison circuit 2 is connected to a resistive memory array 3 and each reference resistor circuit 11; the resistive memory array 3 includes a plurality of resistive memory cells arranged in an array. The comparison circuit 2 is configured to compare the resistance value between the resistive memory cell and the reference resistor in the selected reference resistor circuit 11, so as to output a failure judgment signal according to the comparison result of the resistance value between the resistive memory cell and the reference resistor.
[0047] In the embodiment of the present disclosure, by setting a reference resistor selection circuit 1, specifically, setting at least two reference resistor circuits 11 connected in parallel and a control circuit 12 respectively connected to each reference resistor circuit 11, and making the resistance values of the reference resistors in different reference resistor circuits 11 different, each reference resistor circuit 11 is connected to the resistive memory unit through the comparison circuit 2, so that the control circuit 12 can respond to the control instruction to independently select different reference resistor circuits 11, thereby by comparing the resistance value between the resistive memory unit and the reference resistor in the selected reference resistor circuit 11, it is possible to output a failure judgment signal according to the comparison result of the resistance value between the resistive memory unit and the reference resistor. Therefore, the embodiment of the present disclosure outputs a failure judgment signal by selecting different reference resistors to compare the resistance values with the resistive memory unit, which can avoid adding two erase and write actions for failure judgment each time data is stored, so that the number of erase and write times can be reduced while judging whether the resistive memory unit is failed, so as to increase the life of the resistive memory device, reduce the power consumption of the resistive memory device, and thus facilitate the large-scale application of the resistive memory device.
[0048] See also Figure 2In some embodiments of the present disclosure, the reference resistor gating circuit 1 includes: a reference reference resistor circuit 11A, a first reference resistor circuit 11B, and a second reference resistor circuit 11C. The reference reference resistor circuit 11A includes a reference reference resistor Rref and a reference switch circuit 111. The first reference resistor circuit 11B includes a first reference resistor R1 and a first switch circuit 112. The second reference resistor circuit 11C includes a second reference resistor R2 and a second switch circuit 113. Among them, the first end of the reference reference resistor Rref, the first end of the first reference resistor R1, and the first end of the second reference resistor R2 are all grounded, the second end of the reference reference resistor Rref is connected to the comparison circuit 2 through the reference switch circuit 111, the second end of the first reference resistor R1 is connected to the comparison circuit 2 through the first switch circuit 112, and the second end of the second reference resistor R2 is connected to the comparison circuit 2 through the second switch circuit 113. The reference switch circuit 111, the first switch circuit 112, and the second switch circuit 113 are also connected to the control circuit 12 respectively. The control circuit 12 is configured to: enable the reference switch circuit 111 to output the storage data of the resistive memory cell according to the resistance relationship between the resistive memory cell and the reference resistor Rref; and enable the first reference resistor circuit 112 and / or the second reference resistor circuit 113 to output a failure judgment signal according to the resistance relationship between the resistive memory cell and the first reference resistor 112 or the second reference resistor 113.
[0049] It can be understood that the reference switch circuit 111, the first switch circuit 112 and the second switch circuit 113 can be composed of switch transistors, but it is not limited to this. Any switch device that can respond to the control instruction to perform the on or off action can be used as the corresponding switch circuit, and the embodiments of the present disclosure do not limit this. In some embodiments of the present disclosure, please combine Figure 2 and Figure 3 It is understood that the reference switch circuit 111 and the first switch circuit 112 include first conductivity type transistors. The second switch circuit 113 includes second conductivity type transistors.
[0050] Accordingly, the control circuit 12 includes: a first control circuit 12A connected to the reference switch circuit 111 and the second switch circuit 113 respectively, and a second control circuit 12B connected to the first switch circuit 112. The first control circuit 12A is configured to: generate a reference control instruction to turn on the reference switch circuit, and generate a second control instruction to turn on the second switch circuit; wherein the level signals of the reference control instruction and the second control instruction are opposite. The second control circuit 12B is configured to: generate a first control instruction to turn on the first switch circuit 111.
[0051] For example, the first conductive type transistor is an NMOS transistor, which can be turned on in response to a high level signal; that is, the reference control instruction and the first control instruction can be the same high level signal or different high level signals. The second conductive type transistor is a PMOS transistor, which can be turned on in response to a low level signal; that is, the second control instruction can be a low level signal. Also, please refer to Figure 3 Optionally, the first control circuit 12A includes but is not limited to a first power supply circuit, which is used to provide a first high-level signal (such as a reference control instruction) and a first low-level signal (such as a second control instruction) in a time-sharing manner. The second control circuit 12B includes but is not limited to a second power supply circuit, which is used to provide a second high-level signal (such as a first control instruction).
[0052] On the contrary, it is also allowed that the first conductive type transistor is a PMOS transistor and the second conductive type transistor is an NMOS transistor; accordingly, each control instruction can be generated to match the conductive type of the transistor.
[0053] It is worth mentioning that see Figure 4 In some embodiments of the present disclosure, the resistance range of the base reference resistor Rref is between the high resistance normal distribution interval of each resistive memory cell and the low resistance normal distribution interval of each resistive memory cell.
[0054] Here, the low-resistance normal distribution interval of each resistive memory cell means that after each resistive memory cell in the resistive memory array is written into a low-resistance state, the resistance value (abscissa) and the sample size (ordinate) of each resistive memory cell conform to the first normal distribution Q1, and the resistance value interval corresponding to the first normal distribution Q1 is the low-resistance normal distribution interval of each resistive memory cell. The high-resistance normal distribution interval of each resistive memory cell means that after each resistive memory cell in the resistive memory array is written into a high-resistance state, the resistance value (abscissa) and the sample size (ordinate) of each resistive memory cell conform to the second normal distribution Q2, and the resistance value interval corresponding to the second normal distribution Q2 is the high-resistance normal distribution interval of each resistive memory cell.
[0055] Correspondingly, the resistance range of the benchmark reference resistor Rref is between the high-resistance normal distribution interval of each resistive memory unit and the low-resistance normal distribution interval of each resistive memory unit, which means that the resistance range of the benchmark reference resistor Rref is located in the resistance range corresponding to the blank area between the aforementioned first normal distribution Q1 and the second normal distribution Q2.
[0056] In some embodiments of the present disclosure, please continue to refer to Figure 4 , the resistance of the first reference resistor R1 is ten times (i.e., greater than one order of magnitude) greater than the first average resistance value A of each resistive memory unit in the high resistance state; for example, the first average resistance value A is R A, then the first reference resistor R1 can be 10R A The resistance of the second reference resistor R2 is less than one tenth (ie, less than one order of magnitude) of the second average resistance value B of each resistive memory unit in the low resistance state. For example, the second average resistance value B is R B , then the second reference resistor R2 can be 0.1R B .
[0057] For example, the first average resistance value A is the resistance value corresponding to the symmetry axis in the second normal distribution Q2, and the second average resistance value B is the resistance value corresponding to the symmetry axis in the first normal distribution Q1.
[0058] In a second aspect, some embodiments of the present disclosure further provide a failure judgment method, which can be applied to the failure judgment circuit described in any of the above embodiments. The failure judgment method also has the technical advantages of the above failure judgment circuit, which will not be elaborated here.
[0059] See also Figure 5 The failure judgment method may include the following steps S100 and S200.
[0060] Step S100, independently selecting a reference resistor circuit in a reference resistor selection circuit in response to a control instruction, wherein the reference resistor selection circuit includes at least two reference resistor circuits connected in parallel, and the resistance values of reference resistors in different reference resistor circuits are different.
[0061] Step S200, comparing the resistance values of the resistive memory cells in the resistive memory array with the reference resistor of the enabled reference resistor circuit, and outputting a failure judgment signal according to the comparison result of the resistance values of the resistive memory cells and the reference resistor.
[0062] In some embodiments of the present disclosure, please combine Figure 2 and Figure 3 It is understood that the reference resistor selection circuit 1 includes: a base reference resistor circuit 11A, a first reference resistor circuit 11B and a second reference resistor circuit 11C; wherein, in step S100, the reference resistor circuit in the reference resistor selection circuit is independently selected in response to a control instruction, and in step S200, the resistance value between the resistive memory cell of the resistive memory cell in the resistive memory array and the reference resistor of the selected reference resistor circuit is compared, and a failure judgment signal is output according to the comparison result of the resistance value between the resistive memory cell and the reference resistor. There may also be other specific implementation methods.
[0063] See also Figure 6 The failure judgment method may include the following steps S10 to S70.
[0064] Step S10, enabling the reference resistor circuit.
[0065] Step S20, comparing the resistance value of the resistive memory unit with the resistance value of a reference resistor in a reference resistor circuit.
[0066] Step S30 , acquiring storage data of the resistive memory cell according to a comparison result of the resistance values of the resistive memory cell and the base reference resistor.
[0067] Step S40, enabling the first reference resistance circuit or the second reference resistance circuit.
[0068] Step S50, comparing the resistance values of the resistive memory cell and the first reference resistor in the enabled first reference resistor circuit or the second reference resistor in the enabled second reference resistor circuit.
[0069] Step S60: outputting a failure determination signal according to a comparison result of the resistance values between the resistive memory unit and the corresponding first reference resistor or second reference resistor.
[0070] Step S70 , outputting the storage data of the resistive memory cell when the failure determination signal is a non-failure signal.
[0071] Please combine Figure 3 , Figure 4 and Figure 6 It is understood that in some embodiments of the present disclosure, the resistance range of the base reference resistor Rref is between the high resistance normal distribution interval of each resistive memory cell and the low resistance normal distribution interval of each resistive memory cell. The resistance of the first reference resistor R1 is greater than ten times the first average resistance value A of each resistive memory cell in the high resistance state. The resistance of the second reference resistor R2 is less than one tenth of the second average resistance value B of each resistive memory cell in the low resistance state.
[0072] Correspondingly, in step S60, a failure judgment signal is output according to the comparison result of the resistance value between the resistive memory unit and the corresponding first reference resistor or the second reference resistor, including: when the resistance value of the resistive memory unit is greater than the first reference resistor, a failure judgment signal is output that the resistive memory unit is an open circuit failure; when the resistance value of the resistive memory unit is less than the second reference resistor, a failure judgment signal is output that the resistive memory unit is a short circuit failure.
[0073] Here, open circuit failures include, for example, early preparation failures of resistive memory cells, end of life of resistive memory cells, or poor application environment of resistive memory cells. Short circuit failures include, for example, early preparation failures of resistive memory cells, breakdown of the medium in the resistive memory cells, or poor application environment of resistive memory cells.
[0074] In some embodiments of the present disclosure, the reference reference resistor circuit further includes a reference switch circuit connected to the reference reference resistor, the first reference resistor circuit further includes a first switch circuit connected to the first reference resistor, and the second reference resistor circuit further includes a second switch circuit connected to the second reference resistor. The control circuit includes: a first control circuit connected to the reference switch circuit and the second switch circuit, respectively, and a second control circuit connected to the first switch circuit.
[0075] Correspondingly, in step S10, turning on the reference resistor circuit includes: the first control circuit sends a reference control instruction to the reference switch circuit to turn on the reference switch circuit.
[0076] In step S40, the first reference resistor circuit or the second reference resistor circuit is turned on, including: the second control circuit sends a first control instruction to the first switch circuit to turn on the first switch circuit; or the first control circuit sends a second control instruction to the second switch circuit to turn on the second switch circuit.
[0077] By way of example, the level signals of the reference control command and the second control command are opposite.
[0078] It should be understood that although Figure 5 and Figure 6 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 5 and Figure 6 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.
[0079] For example, it should be added that in some other possible implementations, the base reference resistor circuit, the first reference resistor circuit and the second reference resistor circuit can be randomly enabled, or enabled in other preset orders. For example, the first reference resistor circuit can be enabled first. If the failure judgment signal can be directly determined in this way, there is no need to enable the second reference resistor circuit; or, for example, the second reference resistor circuit can be enabled first. If the failure judgment signal can be directly determined in this way, there is no need to enable the first reference resistor circuit. The disclosed embodiment does not limit this, and the failure judgment signal can be output through the comparison result of the resistance value between the reference resistor and the resistive memory unit.
[0080] In order to more clearly illustrate the failure judgment method provided by the embodiment of the present disclosure, the following is combined with Figure 3 The failure judgment circuit shown describes in detail a possible implementation of the failure judgment method.
[0081] See also Figure 3 The first conductive type transistor is an NMOS transistor, and the second conductive type transistor is a PMOS transistor. The first control circuit 12A is a first power supply circuit for providing a high level signal. The second control circuit 12B is a second power supply circuit for providing a low level signal.
[0082] First, a high-level signal (i.e., a reference control instruction) is provided through the first power supply circuit (12A), and the NMOS tube of the reference resistor circuit 11A is turned on in response to the high-level signal. The comparison circuit 2 compares the resistance value of the resistive storage unit and the reference resistor Rref, and can output data 1 (i.e., the storage data of the resistive storage unit is 1) when the resistance value of the resistive storage unit is greater than the reference resistor Rref, and output data 0 (i.e., the storage data of the resistive storage unit is 0) when the resistance value of the resistive storage unit is less than the reference resistor Rref. At this time, the PMOS tube of the second reference resistor circuit 11C is in the off state in response to the high-level signal.
[0083] When the comparison circuit 2 outputs data 1, it can indicate that the resistive memory unit is in a high-resistance state, or it can indicate that the resistive memory unit is in an open-circuit failure; when the comparison circuit 2 outputs data 0, it can indicate that the resistive memory unit is in a low-resistance state, or it can indicate that the resistive memory unit is in a short-circuit failure; therefore, it is necessary to select the first reference resistor circuit 11B or the second reference resistor circuit 11C accordingly to output a failure judgment signal according to the comparison result of the resistance value between the resistive memory unit and the corresponding first reference resistor or the second reference resistor.
[0084] Specifically, a low-level signal (i.e., a second control instruction) is provided by the first power supply circuit (12A), and the PMOS tube of the second reference resistor circuit 11C is turned on in response to the low-level signal. The comparison circuit 2 compares the resistance value of the resistive memory unit and the second reference resistor R2, and can output data 0 (failure judgment signal) when the resistance value of the resistive memory unit is less than the second reference resistor R2, that is, it is judged that the resistive memory unit is short-circuited and failed. At this time, the NMOS tube of the reference resistor circuit 11A is in an off state in response to the low-level signal.
[0085] The second power supply circuit (12B) provides a high-level signal (i.e., the first control instruction), and the NMOS tube of the first reference resistor circuit 11B is turned on in response to the high-level signal. The comparison circuit 2 compares the resistance value of the resistive memory unit with the resistance value of the first reference resistor R1, and can output data 1 (failure judgment signal) when the resistance value of the resistive memory unit is greater than the first reference resistor R1, that is, it is judged that the resistive memory unit is open-circuit failure. At this time, the NMOS tube of the reference resistor circuit 11A and the PMOS tube of the second reference resistor circuit 11C are both in the off state.
[0086] It can be understood that in some embodiments, the first power supply circuit (12A) provides a low-level signal (i.e., the second control instruction) when the comparison circuit 2 outputs data 0 by comparing the resistance value of the resistive storage unit and the reference resistor Rref. The second power supply circuit (12B) provides a high-level signal (i.e., the first control instruction) when the comparison circuit 2 outputs data 1 by comparing the resistance value of the resistive storage unit and the reference resistor Rref.
[0087] In a third aspect, some embodiments of the present disclosure further provide a resistive memory device, comprising: a resistive memory array, and a failure judgment circuit connected to the resistive memory array and as described in any of the above embodiments. The resistive memory device also possesses the technical advantages of the aforementioned failure judgment circuit. The embodiments of the present disclosure will not elaborate on this.
[0088] In some embodiments of the present disclosure, please combine Figure 3 It is understood that the resistive memory device further includes: a read sense amplifier SA connected to the resistive memory array; wherein the read sense amplifier SA can be reused as a comparison circuit 2 in the failure judgment circuit. In this way, there is no need to independently add a comparison circuit 2, which is conducive to simplifying the structure of the resistive memory device and its preparation process.
[0089] Furthermore, it can be understood that the circuit branch composed of the reference resistor circuit 11A and the comparison circuit 2 in the failure judgment circuit is a data reading circuit of the resistive memory cell in the resistive memory array, that is, when the failure judgment circuit determines that the resistive memory cell has not failed, the resistance value of the resistive memory cell and the reference resistor Rref in the reference resistor circuit 11A can be compared through the comparison circuit 2, thereby outputting read data 1 (that is, the resistive memory cell is in a high-resistance state) or read data 0 (that is, the resistive memory cell is in a low-resistance state).
[0090] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0091] The above-described embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure shall be subject to the attached claims.
Claims
1. A failure judgment circuit, characterized in that: include: Reference resistor gating circuit, comprising: at least two reference resistor circuits connected in parallel, wherein the resistance values of the reference resistors in different reference resistor circuits are different; A control circuit is connected to each of the reference resistance circuits, and is configured to: independently select each of the reference resistance circuits in response to a control instruction; A comparison circuit is connected to the resistive memory array and each of the reference resistor circuits; wherein the resistive memory array includes a plurality of resistive memory cells arranged in an array; and the comparison circuit is configured to compare the resistance values between the resistive memory cells and the reference resistors in the selected reference resistor circuit, so as to output a failure judgment signal according to the comparison result of the resistance values between the resistive memory cells and the reference resistors.
2. The failure judgment circuit according to claim 1, characterized in that: The reference resistor gating circuit comprises: A reference resistor circuit, comprising a reference resistor and a reference switch circuit; A first reference resistor circuit, comprising a first reference resistor and a first switch circuit; A second reference resistor circuit, comprising a second reference resistor and a second switch circuit; Wherein, the first end of the base reference resistor, the first end of the first reference resistor and the first end of the second reference resistor are all grounded, the second end of the base reference resistor is connected to the comparison circuit through the base switch circuit, the second end of the first reference resistor is connected to the comparison circuit through the first switch circuit, and the second end of the second reference resistor is connected to the comparison circuit through the second switch circuit; The reference switch circuit, the first switch circuit and the second switch circuit are also connected to the control circuit respectively; The control circuit is configured to: enable the reference switch circuit to output the storage data of the resistive memory unit according to the resistance relationship between the resistive memory unit and the reference resistor; and enable the first reference resistor circuit and / or the second reference resistor circuit to output the failure judgment signal according to the resistance relationship between the resistive memory unit and the first reference resistor or the second reference resistor.
3. The failure judgment circuit according to claim 2, characterized in that: The resistance of the first reference resistor is greater than ten times the first average resistance of each of the resistive memory cells in the high resistance state; the resistance of the second reference resistor is less than one tenth of the second average resistance of each of the resistive memory cells in the low resistance state.
4. The failure judgment circuit according to claim 2 or 3, characterized in that: The reference switch circuit and the first switch circuit include transistors of a first conductivity type; the second switch circuit includes transistors of a second conductivity type; The control circuit comprises: A first control circuit is connected to the reference switch circuit and the second switch circuit respectively, and is configured to: generate a reference control instruction to turn on the reference switch circuit, and generate a second control instruction to turn on the second switch circuit; the level signals of the reference control instruction and the second control instruction are opposite; The second control circuit is connected to the first switch circuit and is configured to generate a first control instruction to turn on the first switch circuit.
5. The failure judgment circuit according to claim 4, characterized in that: The first conductive type transistor includes an NMOS tube, and the second conductive type transistor includes a PMOS tube; the first control circuit includes a first power supply circuit for providing a first high level signal and a first low level signal, and the second control circuit includes a second power supply circuit for providing a second high level signal.
6. A failure judgment method, characterized in that: include: In response to the control instruction, the reference resistor circuit in the reference resistor gating circuit is independently selected; wherein the reference resistor gating circuit includes at least two reference resistor circuits connected in parallel, and the resistance values of the reference resistors in different reference resistor circuits are different; The resistance values of the resistive memory cells in the resistive memory array and the reference resistor of the reference resistor circuit that is enabled are compared, and a failure judgment signal is output according to the comparison result of the resistance values between the resistive memory cells and the reference resistor.
7. The failure determination method according to claim 6, characterized in that: The reference resistor gating circuit comprises: a base reference resistor circuit, a first reference resistor circuit and a second reference resistor circuit; wherein, the response control instruction independently selects the reference resistor circuit in the reference resistor gating circuit, and the resistance value between the resistive memory cell of the resistive memory cell in the resistive memory array and the reference resistor of the reference resistor circuit being selected is compared, and a failure judgment signal is output according to the comparison result of the resistance value between the resistive memory cell and the reference resistor, including: gating the reference resistor circuit; Comparing the resistance values of the resistive memory unit and a reference resistor in the reference resistor circuit; Acquiring storage data of the resistive memory unit according to a comparison result of the resistance values of the resistive memory unit and the base reference resistor; enabling the first reference resistance circuit or the second reference resistance circuit; Comparing the resistance value of the resistive memory unit with the first reference resistor in the first reference resistor circuit that is enabled or the second reference resistor in the second reference resistor circuit that is enabled; Outputting the failure judgment signal according to a comparison result of the resistance value between the resistive memory unit and the corresponding first reference resistor or the second reference resistor; When the failure judgment signal is a non-failure signal, the storage data of the resistive memory unit is output.
8. The failure determination method according to claim 7, characterized in that: The resistance value of the first reference resistor is greater than ten times the first average resistance value of each of the resistive memory cells in the high resistance state; the resistance value of the second reference resistor is less than one tenth of the second average resistance value of each of the resistive memory cells in the low resistance state; Wherein, outputting the failure judgment signal according to the comparison result of the resistance value between the resistive memory unit and the corresponding first reference resistor or the second reference resistor includes: When the resistance value of the resistive memory unit is greater than the first reference resistor, outputting a failure judgment signal indicating that the resistive memory unit is open circuit failed; When the resistance value of the resistive memory unit is less than the second reference resistance, a failure judgment signal indicating that the resistive memory unit is short-circuited and failed is output.
9. The failure determination method according to claim 7 or 8, characterized in that: The base reference resistor circuit further includes a base switch circuit connected to the base reference resistor, the first reference resistor circuit further includes a first switch circuit connected to the first reference resistor, and the second reference resistor circuit further includes a second switch circuit connected to the second reference resistor; The control circuit comprises: a first control circuit connected to the reference switch circuit and the second switch circuit respectively, and a second control circuit connected to the first switch circuit; Wherein, the step of switching on the reference resistor circuit comprises: the first control circuit sends a reference control instruction to the reference switch circuit to switch on the reference switch circuit; The step of switching on the first reference resistor circuit or the second reference resistor circuit comprises: the second control circuit sending a first control instruction to the first switch circuit to switch on the first switch circuit; or the first control circuit sending a second control instruction to the second switch circuit to switch on the second switch circuit; Wherein, the level signals of the reference control instruction and the second control instruction are opposite.
10. A resistive memory device, characterized in that: include: A resistive memory array, and a failure judgment circuit connected to the resistive memory array and according to any one of claims 1 to 5.