Semiconductor device

Abstract

An emitter electrode of the semiconductor element (40) has an Al electrode (422) and a Ni electrode (423) disposed on the Al electrode (422). A solder (91) that joins the emitter electrode and the conductive spacer (70) contains Cu and Sn. An alloy layer (100) interposed between the emitter electrode and the solder (91) contains Ni, Cu, and Sn. In the solder (91), the particle diameter on the semiconductor element (40) side is smaller than the particle diameter on the conductive spacer (70) side at least in a portion overlapping with the diode region (411d) when viewed in a plane in the Z direction.

Description

[0001] Cross-references of related applications

[0002] This application is based on Japanese Patent Application No. 2022-107162 filed on July 1, 2022, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The disclosure of this specification relates to a semiconductor device. Background Art

[0004] Patent Document 1 discloses a semiconductor device having an IGBT region and a diode region in a common semiconductor substrate. The contents of the prior art document are incorporated herein by reference as explanations of technical elements in this specification.

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent Application Publication No. 2021-136311 Summary of the invention

[0008] By adopting RC-IGBT, which integrates IGBT and freewheeling diode, it is possible to achieve miniaturization. However, since the area of ​​the diode region becomes smaller by one chip, the current density in the diode region becomes higher, and EM becomes a problem. EM is the abbreviation of Electro Migration. From the above viewpoints or other viewpoints not mentioned, further improvements are required for semiconductor devices.

[0009] The present disclosure has been made in view of such a problem, and an object of the present disclosure is to provide a semiconductor device capable of improving EM life.

[0010] As one of the disclosed semiconductor devices, it comprises: a semiconductor element having a semiconductor substrate including an IGBT region and a diode region, and an upper electrode arranged on one side of the semiconductor substrate; an upper conductor arranged opposite to the upper electrode; an upper solder interposed between the upper electrode and the upper conductor to join the upper electrode and the upper conductor; and an alloy layer interposed between the upper electrode and the upper solder; the upper electrode having an Al electrode arranged on one side and a Ni electrode arranged on the Al electrode; the upper solder containing Cu and Sn; the alloy layer containing Ni, Cu and Sn; for the upper solder, in a planar observation in the plate thickness direction of the semiconductor substrate, at least in the portion overlapping with the diode region, the particle size on the semiconductor element side is smaller than the particle size on the upper conductor side.

[0011] According to the disclosed semiconductor device, in the portion overlapping with the diode region with high current density, the particle size of the upper solder on the semiconductor element side is small. This can delay the disappearance of the alloy layer and the Ni electrode caused by EM. As a result, a semiconductor device capable of improving the EM life can be provided.

[0012] The multiple technical solutions disclosed in this specification adopt different technical means to achieve their respective purposes. The marks in brackets recorded in the claims and their items are illustrative of the correspondence with the parts of the embodiments described later, and are not intended to limit the technical scope. The purposes, features and effects disclosed in this specification will be more clearly understood by referring to the subsequent detailed description and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is a diagram showing a schematic configuration of a drive system of a vehicle to which the semiconductor device according to the first embodiment is applied.

[0014] Figure 2 It is a plan view showing the semiconductor device according to the first embodiment.

[0015] Figure 3 It is along Figure 2 Cross-sectional view along line III-III.

[0016] Figure 4 It is along Figure 2 Cross-sectional view of line IV-IV.

[0017] Figure 5 It is a plan view showing a semiconductor element.

[0018] Figure 6 It is along Figure 5 Cross-sectional view of line VI-VI.

[0019] Figure 7 This is an enlarged cross-sectional view of the emitter electrode and its surroundings.

[0020] Figure 8 It is a cross-sectional view showing a reference example.

[0021] Fig. 9 It is a reference diagram showing the mechanism of EM progression.

[0022] Fig.10 It is a plan view showing a semiconductor element in a semiconductor device according to a second embodiment.

[0023] Fig.11 It means Fig.10 Region XI corresponds to the solder diagram.

[0024] Fig.12It is a cross-sectional view showing a method for manufacturing a semiconductor device according to a third embodiment.

[0025] Fig.13 This is an enlarged cross-sectional view of the emitter electrode and its surroundings in the semiconductor device according to the fourth embodiment.

[0026] Fig.14 It is a cross-sectional view showing a modified example.

[0027] Fig.15 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to a fifth embodiment.

[0028] Fig.16 It is a cross-sectional view showing a modified example. DETAILED DESCRIPTION

[0029] Hereinafter, a plurality of embodiments are described based on the accompanying drawings. In addition, in each embodiment, the same reference numerals are given to corresponding constituent elements and repeated descriptions are omitted. In the case where only a part of the structure is described in each embodiment, the structure of other embodiments described in advance can be applied to the other parts of the structure. In addition, not only the combination of structures explicitly described in the description of each embodiment, but also the structures of multiple embodiments can be partially combined with each other even if not explicitly described, as long as there is no particular obstacle in the combination.

[0030] The semiconductor device of this embodiment is applied to, for example, a power conversion device of a mobile body using a rotating electric machine as a driving source. The mobile body is, for example, an electric vehicle such as a battery electric vehicle (BEV), a hybrid electric vehicle (HEV), a plug-in hybrid electric vehicle (PHEV), an electric vertical take-off and landing machine or an unmanned aerial vehicle, a ship, a construction machine, or an agricultural machine. The following describes an example of application to a vehicle.

[0031] (First embodiment)

[0032] First, based on Figure 1 A schematic structure of a vehicle drive system will be described.

[0033] <Vehicle drive system>

[0034] like Figure 1 As shown, a vehicle drive system 1 includes a DC power supply 2 , a motor generator 3 , and a power conversion device 4 .

[0035] The DC power supply 2 is a DC voltage source composed of a secondary battery that can be charged and discharged. The secondary battery is, for example, a lithium-ion battery or a nickel-metal hydride battery. The motor generator 3 is a three-phase AC rotating electric machine. The motor generator 3 functions as a driving source for the vehicle, i.e., an electric motor. The motor generator 3 functions as a generator during regeneration. The power conversion device 4 performs power conversion between the DC power supply 2 and the motor generator 3.

[0036] <Power conversion device>

[0037] Next, based on Figure 1 The circuit structure of the power conversion device 4 is described. The power conversion device 4 includes a power conversion circuit. Figure 1 As shown, the power conversion device 4 includes a smoothing capacitor 5 and an inverter 6 as a power conversion circuit.

[0038] The smoothing capacitor 5 mainly smoothes the DC voltage supplied from the DC power supply 2. The smoothing capacitor 5 is connected to a P line 7 which is a power line on the high potential side and an N line 8 which is a power line on the low potential side. The P line 7 is connected to the positive electrode of the DC power supply 2, and the N line 8 is connected to the negative electrode of the DC power supply 2. The positive electrode of the smoothing capacitor 5 is connected to the P line 7 between the DC power supply 2 and the inverter 6. The negative electrode of the smoothing capacitor 5 is connected to the N line 8 between the DC power supply 2 and the inverter 6. The smoothing capacitor 5 is connected in parallel with the DC power supply 2.

[0039] The inverter 6 is a DC-AC conversion circuit. The inverter 6 converts the DC voltage into a three-phase AC voltage according to the switch control performed by the control circuit (not shown) and outputs it to the motor generator 3. As a result, the motor generator 3 is driven to generate a predetermined torque. During the regenerative braking of the vehicle, the inverter 6 converts the three-phase AC voltage generated by the motor generator 3 under the rotational force from the wheels into a DC voltage according to the switch control performed by the control circuit, and outputs it to the P line 7. In this way, the inverter 6 performs bidirectional power conversion between the DC power supply 2 and the motor generator 3.

[0040] The inverter 6 is configured with upper and lower arm circuits 9 of three phases. The upper and lower arm circuits 9 are sometimes referred to as legs. The upper and lower arm circuits 9 have an upper arm 9H and a lower arm 9L, respectively. The upper arm 9H and the lower arm 9L are connected in series between the P line 7 and the N line 8, with the upper arm 9H being the P line 7 side. The connection point between the upper arm 9H and the lower arm 9L is connected to the winding 3a of the corresponding phase of the motor generator 3 via the output line 10. The inverter 6 has six arms. At least a portion of each of the P line 7, the N line 8, and the output line 10 is formed of a conductive member such as a bus bar.

[0041] The elements constituting each arm include an IGBT 11 as a switching element and a diode 12 for freewheeling. IGBT is the abbreviation of Insulated Gate Bipolar Transistor. In the present embodiment, an n-channel IGBT 11 is used. The diode 12 is connected in anti-parallel to the corresponding IGBT 11. In the upper arm 9H, the collector of the IGBT 11 is connected to the P line 7. In the lower arm 9L, the emitter of the IGBT 11 is connected to the N line 8. Furthermore, the emitter of the IGBT 11 in the upper arm 9H and the collector of the IGBT 11 in the lower arm 9L are connected to each other. The anode of the diode 12 is connected to the emitter of the corresponding IGBT 11, and the cathode is connected to the collector.

[0042] The power conversion device 4 may also include a converter as a power conversion circuit. The converter is a DC-DC conversion circuit that converts a DC voltage into a DC voltage of a different value. The converter is provided between the DC power supply 2 and the smoothing capacitor 5. The converter is configured to include, for example, a reactor and the upper and lower arm circuits 9 described above. According to this structure, voltage can be increased or decreased. The power conversion device 4 may also include a filter capacitor that removes power supply noise from the DC power supply 2. The filter capacitor is provided between the DC power supply 2 and the converter.

[0043] The power conversion device 4 may also include a drive circuit for a switching element constituting the inverter 6 or the like. The drive circuit supplies a drive voltage to the gate of the IGBT 11 of the corresponding arm based on a drive instruction from the control circuit. The drive circuit drives the corresponding IGBT 11 by applying the drive voltage, i.e., turns it on or off. The drive circuit is sometimes referred to as a driver.

[0044] The power conversion device 4 may also include a control circuit for the switching element. The control circuit generates a drive instruction for actuating the IGBT 11 and outputs it to the drive circuit. The control circuit generates a drive instruction based on a torque request input from a higher-level ECU (not shown) and signals detected by various sensors. Various sensors include, for example, a current sensor, a rotation angle sensor, and a voltage sensor. The current sensor detects the phase current flowing through the winding 3a of each phase. The rotation angle sensor detects the rotation angle of the rotor of the electric generator 3. The voltage sensor detects the voltage across the smoothing capacitor 5. The control circuit outputs, for example, a PWM signal as a drive instruction. The control circuit is composed of, for example, a processor and a memory. ECU is the abbreviation of Electronic Control Unit. PWM is the abbreviation of Pulse Width Modulation.

[0045] <Semiconductor Device>

[0046] Next, based on Figure 2 to Figure 6 The schematic structure of a semiconductor device is described. Figure 2 is a plan view showing a semiconductor device. Figure 2 is a top plan view of a semiconductor device. Figure 3 It is along Figure 2 Cross-sectional view along line III-III. Figure 4 It is along Figure 2 Cross-sectional view of line IV-IV. Figure 5 It is a plan view showing a semiconductor element. Figure 6 It is along Figure 5 Cross-sectional view of line VI-VI.

[0047] In the following, the plate thickness direction of the semiconductor element (semiconductor substrate) is defined as the Z direction. A direction orthogonal to the Z direction is defined as the X direction. A direction orthogonal to both the Z direction and the X direction is defined as the Y direction. Unless otherwise specified, the shape observed from the plane in the Z direction, in other words, the shape along the XY plane defined by the X direction and the Y direction, is defined as the planar shape. In addition, there is a case where the planar observation from the Z direction is simply represented as the planar observation.

[0048] like Figure 2 to Figure 6 As shown, the semiconductor device 20 includes a sealing body 30, a semiconductor element 40, wiring members 50, 60, a conductive spacer 70, and an external connection terminal 80. The semiconductor device 20 also includes a bonding wire 90 and solders 91 to 93. The semiconductor device 20 constitutes one of the arms. That is, two semiconductor devices 20 constitute the upper and lower arm circuits 9 of one phase.

[0049] The sealing body 30 seals a part of other elements constituting the semiconductor device 20. The rest of the other elements are exposed outside the sealing body 30. The sealing body 30 is made of, for example, resin. An example of a resin is an epoxy resin. The sealing body 30 is made of resin, for example, and is formed by a transfer mold method. Such a sealing body 30 is sometimes referred to as a sealing resin body, a molding resin, a resin molded body, etc. The sealing body 30 can also be formed using, for example, a gel. The gel is filled (arranged) in, for example, the opposing regions of a pair of wiring components 50, 60.

[0050] like Figure 2 to Figure 4As shown, the planar shape of the sealing body 30 is roughly rectangular. In the sealing body 30, as the surface forming the outer contour, there is a side 30a and a back surface 30b which is opposite to the side 30a in the Z direction. The side 30a and the back surface 30b are, for example, roughly flat surfaces. In addition, there are side surfaces 30c, 30d, 30e, and 30f connected to the side 30a and the back surface 30b. The side surface 30c is the surface where the main terminals 81 and 82 of the external connection terminal 80 protrude. The side surface 30d is the surface opposite to the side surface 30c in the Y direction. The side surface 30d is the surface where the signal terminal 83 protrudes. The side surfaces 30e and 30f are the surfaces where the external connection terminal 80 does not protrude. The side surface 30e is the surface opposite to the side surface 30f in the X direction.

[0051] The semiconductor element 40 includes a semiconductor substrate 41, an emitter electrode 42, a collector electrode 43, and a pad 44. The semiconductor element 40 is sometimes referred to as a semiconductor chip. The semiconductor substrate 41 is made of silicon (Si), a wide bandgap semiconductor having a wider bandgap than silicon, and is formed into a vertical element. Examples of wide bandgap semiconductors include silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), and diamond.

[0052] The vertical element is configured so that the main current flows in the thickness direction of the semiconductor substrate 41 (semiconductor element 40), that is, in the Z direction. The vertical element of this embodiment is an IGBT 11 and a diode 12 that constitute one arm. The vertical element is an IGBT in which the diode 12 is connected in anti-parallel, that is, an RC-IGBT. RC is the abbreviation of Reverse Conducting. The vertical element is a heating element that generates heat when electricity is applied. A gate electrode, not shown, is formed on the semiconductor substrate 41. The gate electrode forms a groove structure, for example.

[0053] like Figure 5 As shown, the planar shape of the semiconductor substrate 41 is roughly rectangular. The semiconductor substrate 41 has an active region 411 and a peripheral region 412. The active region 411 is a formation region of a vertical element. The active region 411 is sometimes referred to as a main region, a main unit region, a unit region, a device region, a device formation region, etc. In the peripheral region 412, a voltage-resistant structure portion not shown in the figure, such as a guard ring, is formed.

[0054] The active region 411 is parallel to the pad 44 in the Y direction. The active region 411 is, for example, roughly rectangular in planar shape. The active region 411 has an IGBT region 411i as a formation region of the IGBT in the RC-IGBT and a diode region 411d as a formation region of the diode. The IGBT region 411i and the diode region 411d are alternately arranged in the X direction. In the active region 411, a plurality of units (unit structural parts) are provided. The plurality of units are connected in parallel to each other to form an RC-IGBT. As an example, the IGBT region 411i and the diode region 411d are alternately arranged at a predetermined interval. The two ends of the arrangement direction are the IGBT region 411i. With respect to the area when observed in a planar manner, the IGBT region 411i is larger than the diode region 411d.

[0055] The semiconductor substrate 41 has one surface 41a and a back surface 41b as the plate surface where the main electrode is provided. The one surface 41a is the surface on the one surface 30a side of the sealing body 30 in the semiconductor substrate 41. The back surface 41b is the surface opposite to the one surface 41a in the plate thickness direction. The emitter electrode 42, which is one of the main electrodes, is arranged on the one surface 41a of the semiconductor substrate 41. The collector electrode 43, which is another main electrode, is arranged on the back surface 41b of the semiconductor substrate 41.

[0056] When the IGBT 11 is turned on, a current (main current) flows between the main electrodes, that is, between the emitter electrode 42 and the collector electrode 43. The emitter electrode 42 also serves as the anode electrode of the diode 12. The collector electrode 43 also serves as the cathode electrode of the diode 12. The collector electrode 43 is formed on substantially the entire back surface 41b of the semiconductor substrate 41. The emitter electrode 42 is formed on a portion of the one surface 41a of the semiconductor substrate 41. The emitter electrode 42 corresponds to the upper electrode, and the collector electrode 43 corresponds to the lower electrode.

[0057] The pad 44 is a signal electrode. The pad 44 is formed in a region different from the region where the emitter electrode 42 is formed on one side 41a of the semiconductor substrate 41. The pad 44 is formed at an end on the opposite side of the region where the emitter electrode 42 is formed in the Y direction. The pad 44 is arranged in parallel with the emitter electrode 42 in the Y direction. The number of pads 44 is not particularly limited. The pad 44 includes at least a pad for a gate electrode.

[0058] As an example, Figure 5 As shown, the semiconductor element 40 has five pads 44. Specifically, there are a gate electrode pad, an emitter potential detection pad, a cathode potential detection pad and an anode potential detection pad of a temperature sensing diode (not shown) provided in the semiconductor element 40, and a current sensing pad. The five pads 44 are arranged along the X direction.

[0059] like Figure 5 and Figure 6 As shown, the semiconductor element 40 includes a protective film 45 disposed on one side 41a of a semiconductor substrate 41. The protective film 45 is an insulating film provided on one side 41a of the semiconductor substrate 41 to cover the emitter electrode 42, specifically, to cover the peripheral portion of an Al electrode 422 described later. As a material of the protective film 45, for example, polyimide, silicon nitride film, etc. can be used.

[0060] The protective film 45 has an opening 451, a peripheral portion 452, and a partitioning portion 453. The opening 451 defines a bonding region between the emitter electrode 42 and the solder 91. The opening 451 is a through hole that penetrates the protective film 45 in the Z direction. The opening 451 is provided so as to overlap with the emitter electrode 42 in plan view. The opening 451 is substantially consistent with the active region 411 in plan view. Similarly, the protective film 45 has an opening (not shown) that defines a bonding region of the pad 44.

[0061] The peripheral portion 452 is arranged at the peripheral portion of the semiconductor element 40. The peripheral portion 452 is arranged to be roughly consistent with the peripheral area 412 when viewed from a plane. The dividing portion 453 divides the Ni electrode 423 into a plurality of areas. As an example, the dividing portion 453 of the present embodiment is set to divide the Ni electrode 423 roughly into two equal parts in the X direction. The dividing portion 453 divides the opening 451 into two areas. The dividing portion 453 passes through the center of the semiconductor element 40 and extends in the Y direction. One of the ends of the dividing portion 453 is connected to the peripheral portion 452 on the side of the pad 44, and the other end is connected to the peripheral portion 452 on the opposite side of the pad 44.

[0062] The emitter electrode 42 has an exposed portion 421 that is exposed from the opening 451 of the protective film 45 to provide a bonding area. The exposed portion 421 forms a bonding portion with the solder 91. The outer contour of the exposed portion 421 is consistent with the outer contour of the opening 451 in planar observation. The exposed portion 421 is arranged on the active region 411 of the semiconductor substrate 41. The emitter electrode 42 has a multilayer structure. The emitter electrode 42 has an Al electrode 422 and a Ni electrode 423. The pad 44 also has the same structure as the emitter electrode 42.

[0063] In the emitter electrode 42 of the multilayer structure, the Al electrode 422 is a metal layer formed adjacent to the semiconductor substrate 41. The Al electrode 422 is formed using a material having Al (aluminum) as a main component. As an example, in the present embodiment, it is an Al alloy such as AlSi, AlSiCu, etc. The Al electrode 422 may be referred to as a base electrode, a wiring electrode, a base layer, a first metal layer, etc. The Al electrode 422 is connected to one side 41a of the semiconductor substrate 41.

[0064] In planar view, the Al electrode 422 includes the active region 411 inside and extends to the peripheral region 412. The Al electrode 422 is connected to the emitter and the anode of the vertical element. The Al electrode 422 has a peripheral portion 422a surrounding the exposed portion 421 in planar view. The peripheral portion 422a is a portion of the Al electrode 422 that overlaps with the protective film 45. The protective film 45 is arranged on one surface 41a of the semiconductor substrate 41 in a manner that covers the peripheral portion 422a of the Al electrode 422.

[0065] The Ni electrode 423 is stacked on the Al electrode 422 for the purpose of improving the bonding strength with the solder 91 and improving the wettability to the solder 91. The Ni electrode 423 is formed using a material containing Ni (nickel) as a main component. As an example, in this embodiment, it is NiP formed by a non-electroplating method. The Ni electrode 423 is a Ni plating film containing P. There are cases where the Ni electrode 423 is called an upper electrode, a connecting electrode, an upper layer, a second metal layer, a plating layer, a sound layer, etc.

[0066] Ni is harder than the Al alloy constituting the Al electrode 422. In addition, during the manufacturing process, an Au electrode may be further provided on the Ni electrode 423. Au, for example, suppresses oxidation of Ni and improves wettability with the solder serving as the solder 91. Since Au diffuses into the solder during soldering, it exists in the state before joining, but does not exist in the state after joining.

[0067] The Ni electrode 423 is stacked on the Al electrode 422 and exposed from the opening 451. As an example, the Ni electrode 423 of this embodiment is arranged on the Al electrode 422 in the opening 451. The outer peripheral edge of the Ni electrode 423 contacts the wall surface of the protective film 45 defining the opening 451.

[0068] The wiring member 50 is electrically connected to the emitter electrode 42 and provides a wiring function. Similarly, the wiring member 60 is electrically connected to the collector electrode 43 and provides a wiring function. The wiring members 50 and 60 are arranged so as to sandwich the semiconductor element 40 in the Z direction. The wiring members 50 and 60 are arranged so as to be at least partially opposed to each other in the Z direction. The wiring members 50 and 60 contain the semiconductor element 40 inside when viewed in a plan view. The wiring member 60 is equivalent to a lower conductor.

[0069] The wiring components 50 and 60 provide a heat dissipation function for dissipating the heat generated by the semiconductor element 40. The wiring components 50 and 60 may be referred to as heat sinks, heat sinks, etc. The wiring components 50 and 60 of the present embodiment are metal plates made of metals with good conductivity such as Cu and Cu alloys. The metal plate is provided as a part of a lead frame, for example. Instead of the metal plate, a substrate having a metal body arranged on both sides of an insulating substrate may be used. The wiring components 50 and 60 may also have a plated film of Ni, Au, etc. on the surface.

[0070] The wiring component 50 has an opposing surface 50a on the side of the semiconductor element 40 and a back surface 50b opposite to the opposing surface 50a. Similarly, the wiring component 60 also has an opposing surface 60a and a back surface 60b. The wiring components 50, 60 are, for example, roughly rectangular in plan view. The back surfaces 50b, 60b of the wiring components 50, 60 are respectively exposed from the sealing body 30. There are cases where the back surfaces 50b, 60b are referred to as heat dissipation surfaces, exposed surfaces, etc. The back surface 50b of the wiring component 50 is roughly coplanar with one surface 30a of the sealing body 30. The back surface 60b of the wiring component 60 is roughly coplanar with the back surface 30b of the sealing body 30.

[0071] The conductive spacer 70 is interposed between the semiconductor element 40 and the wiring member 50. The conductive spacer 70 provides a spacer function of ensuring a predetermined distance between the semiconductor element 40 and the wiring member 50. For example, the conductive spacer 70 ensures a height for electrically connecting the corresponding signal terminal 83 to the pad 44 of the semiconductor element 40. The conductive spacer 70 is located in the middle of the electrical and thermal conduction path between the emitter electrode 42 of the semiconductor element 40 and the wiring member 50, and provides a wiring function and a heat dissipation function. The conductive spacer 70 is equivalent to an upper conductor.

[0072] The conductive spacer 70 includes a metal material with good electrical and thermal conductivity such as Cu. The conductive spacer 70 may also have a plated film on the surface. The conductive spacer 70 may be referred to as a terminal, a terminal block, a metal block, etc. The conductive spacer 70 of this embodiment is a columnar body having a substantially rectangular planar shape.

[0073] The external connection terminal 80 is a terminal for electrically connecting the semiconductor device 20 to an external device. The external connection terminal 80 is formed using a metal material with good conductivity such as copper. The external connection terminal 80 is, for example, a plate. There are cases where the external connection terminal 80 is called a lead. The external connection terminal 80 includes main terminals 81, 82 and a signal terminal 83. The main terminals 81, 82 are external connection terminals 80 electrically connected to the main electrodes of the semiconductor element 40.

[0074] The main terminal 81 is electrically connected to the emitter electrode 42. The main terminal 81 may be referred to as an emitter terminal. The main terminal 81 is connected to the emitter electrode 42 via the wiring member 50. The main terminal 81 is connected to one end of the wiring member 50 in the Y direction. The thickness of the main terminal 81 is thinner than that of the wiring member 50. The main terminal 81 is connected to the wiring member 50 in a manner that is substantially coplanar with the opposing surface 50a, for example. The main terminal 81 may be connected to the wiring member 50 by being continuously and integrally provided, or may be provided as another member and connected by bonding.

[0075] The main terminal 81 of this embodiment is provided integrally with the wiring member 50 as a part of the lead frame. The main terminal 81 extends from the wiring member 50 in the Y direction and protrudes to the outside from the side surface 30c of the sealing body 30. The main terminal 81 has a bent portion in the middle of the portion covered by the sealing body 30 and protrudes from the side surface 30c near the center in the Z direction.

[0076] The main terminal 82 is electrically connected to the collector electrode 43. The main terminal 82 may be referred to as the collector terminal. The main terminal 82 is connected to the collector electrode 43 via the wiring component 60. The main terminal 82 is connected to one end of the wiring component 60 in the Y direction. The thickness of the main terminal 82 is thinner than that of the wiring component 60. The main terminal 82 is connected to the wiring component 60 in a manner that is substantially coplanar with the opposing surface 60a, for example. The main terminal 82 may be connected to the wiring component 60 by being continuously and integrally provided, or may be provided as another component and connected by bonding.

[0077] The main terminal 82 of this embodiment is provided integrally with the wiring member 60 as a part of a lead frame different from the main terminal 81. The main terminal 82 extends from the wiring member 60 in the Y direction and protrudes to the outside from the same side surface 30c as the main terminal 81. The main terminal 82 also has a bent portion in the middle of the portion covered by the sealing body 30, and protrudes from the side surface 30c near the center in the Z direction. The two main terminals 81 and 82 are arranged in the X direction so that the side surfaces face each other.

[0078] The signal terminal 83 is electrically connected to the corresponding pad 44 of the semiconductor element 40. The signal terminal 83 is electrically connected to the pad 44 via the bonding wire 90. The signal terminal 83 extends in the Y direction and protrudes from the side surface 30d of the sealing body 30 to the outside. The semiconductor device 20 of this embodiment has five signal terminals 83 corresponding to the pad 44. The five signal terminals 83 are arranged in the X direction. The signal terminal 83 is, for example, formed in a lead frame common to the wiring member 60 and the main terminal 82. The plurality of signal terminals 83 are electrically separated from each other by cutting a tie bar (not shown).

[0079] Solder 91 is interposed between emitter electrode 42 of semiconductor element 40 and conductive spacer 70, and joins emitter electrode 42 and conductive spacer 70. Solder 91 is sometimes referred to as upper solder of element. Solder 91 corresponds to upper solder. Solder 92 is interposed between conductive spacer 70 and wiring member 50, and joins conductive spacer 70 and wiring member 50. Solder 92 is sometimes referred to as upper solder of spacer. Solder 93 is interposed between collector electrode 43 of semiconductor element 40 and wiring member 60, and joins collector electrode 43 and wiring member 60. Solder 93 is sometimes referred to as lower solder of element. Solder 93 corresponds to lower solder.

[0080] The solders 91 to 93 may be made of the same material or different materials. The solder 91 contains Cu and Sn. As an example, the solder 91 is a multi-component lead-free solder containing Cu, Bi, Sb, etc., and the remainder is made of Sn.

[0081] As described above, in semiconductor device 20, semiconductor element 40 constituting one arm is sealed by sealing body 30. Sealing body 30 integrally seals semiconductor element 40, part of wiring member 50, part of wiring member 60, conductive spacer 70, and part of external connection terminal 80.

[0082] The semiconductor element 40 is arranged between the wiring components 50 and 60 in the Z direction. The semiconductor element 40 is sandwiched by the wiring components 50 and 60 arranged opposite to each other. As a result, the heat of the semiconductor element 40 can be dissipated to both sides in the Z direction. The semiconductor device 20 has a double-sided heat dissipation structure. The back surface 50b of the wiring component 50 is roughly coplanar with the one surface 30a of the sealing body 30. The back surface 60b of the wiring component 60 is roughly coplanar with the back surface 30b of the sealing body 30. Since the back surfaces 50b and 60b are exposed surfaces, the heat dissipation can be improved.

[0083] <Component upper structure and solder particle size>

[0084] Next, based on Figure 7 and Figure 8 The upper structure of the component and the solder particle size are described. Figure 7 It is a cross-sectional view showing the upper structure of the element of the semiconductor device 20 according to the present embodiment. Figure 7 It is a cross-sectional view showing an enlarged view of the periphery of the emitter electrode 42 . Figure 7 is with Figure 5 The cross-sectional view corresponding to the line VII-VII. Figure 8 2 is a cross-sectional view showing the upper structure of a device of a reference example. In the reference example, the reference numerals of the elements are obtained by appending r to the end of the reference numerals of the related elements of the semiconductor device 20 .

[0085] like Figure 7 As shown, the semiconductor device 20 includes an alloy layer 100 between the Ni electrode 423 and the solder 91. The alloy layer 100 is sometimes referred to as IMC. IMC is an abbreviation for Intermetallic Compound. The alloy layer 100 is formed during bonding. The alloy layer 100 contains Ni, Cu, and Sn. The composition of the alloy layer 100 is, for example, (Ni-Cu)3Sn4.

[0086] The semiconductor device 20 further includes a P-rich layer 424. The P-rich layer 424 is formed on the surface of the Ni electrode 423. The P-rich layer 424 is formed by diffusion of a portion of Ni of the Ni electrode 423 toward the solder 91 during bonding. The P-rich layer 424 is a layer richer in P than the Ni electrode 423 (NiP). The composition of the P-rich layer 424 is, for example, Ni3P.

[0087] The Ni electrode 423 has a concavoconvex portion 4231 with continuous concavoconvexity formed on the surface of at least the portion overlapping with the diode region 411d. The concavoconvex portion 4231 is formed with concavoconvexity and concavoconvexity repeatedly and continuously in the X direction, for example. The repetition direction of the concavoconvex portion 4231 is not limited to the X direction. For example, it can also be the Y direction, or the X direction and the Y direction. The concavoconvex portion 4231 can also be arranged like a checkerboard pattern. The height difference of the concavoconvex portion 4231 is, for example, about 1 μm. The Ni electrode 423 has the concavoconvex portion 4231, so that the P-rich layer 424 and the alloy layer 100 arranged on the Ni electrode 423 also have a concavoconvex shape.

[0088] The concavoconvex portion 4231 is formed, for example, by patterning the surface of the Ni electrode 423. Alternatively, the concavoconvex portion 4231 may be provided on the surface of the Ni electrode 423 by providing a concavoconvex structure on the Al electrode 422 located directly below the Ni electrode 423. The concavoconvex portion 4231 may also be provided on the surface of the Ni electrode 423 by providing a concavoconvex structure on one surface 41a of the semiconductor substrate 41 through an interlayer insulating film or the like.

[0089] The solder 91 starts grain growth from the concavo-convex originating from the Ni electrode 423 when the solder 91 solidifies. Adjacent grains collide to form grain boundaries 910. The grains grow from the concavo-convex as a starting point, and become smaller on the semiconductor element 40 side. Thus, in the portion of the solder 91 at least overlapping the diode region 411d, the grain size on the semiconductor element 40 side is smaller than the grain size on the conductive spacer 70 side. In the solder 91, the portion closer to the semiconductor element 40 than the center in the Z direction is the semiconductor element 40 side, and the portion closer to the conductive spacer 70 than the center is the conductive spacer 70 side.

[0090] Although not shown in the figure, the particle size of the solder 91 at least in the portion overlapping the diode region 411d on the semiconductor element 40 side is smaller than the particle size of the solder 93. The thickness of the solder 91 is, for example, about 100 μm. Figure 7 In the example shown, the conductive spacer 70 has a plating film 71 on the surface. The plating film 71 has Ni as the main component, similarly to the Ni electrode 423. The alloy layer between the plating film 71 and the solder 91 is omitted for convenience. Figure 7 As shown, the plating film 71 has no concavo-convex portions.

[0091] exist Figure 8 In the comparative example shown, there is no concavo-convex portion on the surface of the Ni electrode 423r. That is, the particle size of the solder 91r is not controlled. The other structures are the same as those of the semiconductor device 20 of the present embodiment. In this case, the particle size of the solder 911r is about 100 μm. The crystal grains of the solder 911r exist in the thickness direction (Z direction) of the solder 91 to the extent of one or two. As a result, in the entire area of ​​the solder 91r, the particle size on the semiconductor element 40r side and the particle size on the conductive spacer 70r side are both larger. The particle size on the semiconductor element 40r side and the particle size on the conductive spacer 70r side are of the same degree.

[0092] <em>

[0093] Next, based on Fig. 9 EM (electromigration) will be described. Fig. 9 is a reference diagram showing the mechanism of EM progression. Fig. 9 In the example shown in the reference figure, the symbol of each element is set to the end of the symbol of the element related to the semiconductor device 20 with r added. Figure 8 The structure shown is the same as that of the semiconductor device 20 of the present embodiment, and the particle size control of the solder 91r is not performed. The other structures are the same as those of the semiconductor device 20 of the present embodiment.

[0094] Fig. 9 The first time (1st) indicates the initial stage before power is applied. An alloy layer 100r exists between the Ni electrode 423r and the solder 91r. In addition, a P-rich layer 424r is formed on the surface of the Ni electrode 423r.

[0095] Fig. 9 The second (2nd), third (3rd) and fourth (4th) times represent the application of the freewheeling current. The dotted arrows represent the electrons (e - ) flow direction. That is, the freewheeling current flows from the conductive spacer side (not shown) to the semiconductor element side. The freewheeling current is the current that flows when the diode is in operation.

[0096] like Fig. 9 As shown in the second time (2nd), as the electrons move, the Cu and other metals in the alloy layer 100r on the diode region move (diffusion) toward the conductive spacer side. Specifically, the metals such as Cu are ionized and move toward the conductive spacer side. As a result, the alloy layer 100r gradually becomes thinner, as shown in FIG. Fig. 9 The third time (3rd) disappears as shown.

[0097] If the alloy layer 100r disappears, Fig. 9 As shown in the third time (3rd), as the electrons move, the Ni of the Ni electrode 423r moves (diffuses) toward the conductive spacer side, the Ni electrode 423r decreases, and the P-rich layer 424r increases. Fig. 9 As shown in the fourth time (4th), the Ni electrode 423r disappears and the P-rich layer 424r reaches the Al electrode 422r. That is, the P-rich layer 424r is replaced by the Ni electrode 423r.

[0098] After the P-rich layer 424r reaches the Al electrode 422r, if it passes further, the adhesion is reduced, for example, voids are generated. In addition, cracks are generated along the interface starting from the voids.

[0099] As described above, in the structure where the solder particle size is not controlled (refer to Figure 8 ), the particle size of the solder 91 is large. There are few grain boundaries in the movement path of Cu. Therefore, the Cu of the alloy layer 100r easily moves with the movement of electrons.

[0100] On the other hand, in the structure of this embodiment (see Figure 7 ), the particle size of the solder 91 on the semiconductor element 40 side is smaller than the particle size on the conductive spacer 70 side just above the diode region 411d where the current density is high. That is, there are more grain boundaries 910 on the semiconductor element 40 side. Therefore, the Cu of the alloy layer 100 is not easy to move with the movement of electrons. That is, the alloy layer 100 is not easy to disappear. The time taken until the alloy layer 100 disappears becomes longer. As a result, the time when the Ni electrode 423 becomes the P-rich layer 424 and starts to decrease becomes later. The time taken until the Ni electrode 423 disappears becomes longer.

[0101] <Summary of the First Embodiment>

[0102] By using the RC-IGBT in which the IGBT 11 and the diode 12 are integrated into a single chip, for example, the semiconductor device 20 can be miniaturized. However, by integrating into a single chip, the area of ​​the diode region 411 d is reduced, and the current density in the diode region 411 d is increased.

[0103] In the present embodiment, at least in the portion overlapping with the diode region 411d, the particle size of the solder 91 on the semiconductor element 40 side is smaller than the particle size on the conductive spacer 70 side. There are many grain boundaries 910 on the semiconductor element 40 side. The grain boundaries 910 hinder the movement of Cu. Therefore, the Cu of the alloy layer 100 is not easy to move with the movement of electrons. As a result, the time taken until the alloy layer 100 disappears can be lengthened. In addition, the time taken until the Ni electrode 423 disappears can be lengthened. Based on the above, the EM life can be improved. In particular, in the present embodiment, the area of ​​the diode region 411d is smaller than the area of ​​the IGBT region 411i, and the current density of the current path in the diode region 411d is the largest. However, since the particle size of the solder 91 on the semiconductor element 40 side is made small, the EM life can be improved.

[0104] In addition, the effect of the particle size of the solder 91 has been confirmed by trial production. It can be confirmed that by reducing the particle size of the solder 91 on the semiconductor element 40 side, the disappearance of the alloy layer 100 is slowed down, that is, the progress of EM can be slowed down. At this time, the Ni electrode 423 is formed by non-electrolytic NiP plating. The composition of the alloy layer 100 is (Ni-Cu)3Sn4.

[0105] The particle size of the solder 91 on the semiconductor element 40 side may be smaller than the particle size on the conductive spacer 70 side at least in the portion overlapping with the diode region 411d. For example, the particle size of the solder 91 on the semiconductor element 40 side may be smaller than the particle size on the conductive spacer 70 side only in the portion overlapping with the diode region 411d. The particle size of the solder 91 on the semiconductor element 40 side may be smaller than the particle size on the conductive spacer 70 side in the diode region 411d and the IGBT region 411i.

[0106] In the present embodiment, the particle size of the semiconductor element 40 side of the solder 91 in at least the portion overlapping with the diode region 411d is smaller than the particle size of the solder 93. The solder 93 has no solder particle size control and has a large particle size. By controlling the particle size, the particle size of the semiconductor element 40 side of the solder 91 is smaller than that of the solder 93 at least in the portion overlapping with the diode region 411d. Thus, at least in the portion overlapping with the diode region 411d, there are many grain boundaries 910 on the semiconductor element 40 side of the solder 91. The grain boundaries 910 hinder the movement of Cu. Therefore, the Cu of the alloy layer 100 is not easy to move with the movement of electrons. Thus, the time taken until the alloy layer 100 disappears can be lengthened. In addition, the time taken until the Ni electrode 423 disappears can be lengthened.

[0107] In this embodiment, the Ni electrode 423 has a concavoconvex portion 4231 with continuous concavoconvexity formed on the surface of at least the portion overlapping the diode region 411d. In this way, by providing the concavoconvex portion 4231 on the Ni electrode 423, the particle size becomes smaller on the semiconductor element 40 side. The EM life can be improved with a simple structure. In addition, according to the formation range of the concavoconvex portion 4231, the portion with a smaller solder particle size can be controlled.

[0108] (Second embodiment)

[0109] This embodiment is a modified example based on the previous embodiment, and the description of the previous embodiment can be cited. In the previous embodiment, the solder particle size on the semiconductor element 40 side is reduced by providing the concavo-convex portion 4231 on the surface of the Ni electrode 423. Alternatively, the concavo-convex portion can also be provided at the end of the protective film 45.

[0110] Fig.10 FIG. 2 is a plan view showing a semiconductor element 40 in the semiconductor device 20 of the present embodiment. Fig.10 , the active region 411 including the IGBT region 411i and the diode region 411d and the peripheral region 412 are omitted. Figure 5 The structure shown is the same.

[0111] As in the previous embodiment, the protective film 45 has a partition portion 453. The partition portion 453 passes through the center of the semiconductor element 40 and extends in the Y direction. The partition portion 453 is set to divide the Ni electrode 423 into two equal parts in the X direction. When viewed from a plane, the end of the partition portion 453 is in a continuous concave-convex shape. The protective film 45 has a concave-convex portion 454 at the end of the partition portion 453. As an example, the concave-convex portion 454 is provided at both ends of the partition portion 453. The concave-convex portion 454 is provided over the entire length of the partition portion 453 in the Y direction.

[0112] Fig.11 Yes Fig.10 The area XI is enlarged in the figure. Fig.11 FIG. 4 shows the solder 91 disposed on the emitter electrode 42. Fig.11 , only a portion of the grain boundary 910 is shown. The solder 91 takes the concavo-convex provided at the end of the partition portion 453 as a starting point, and the grains grow when the solder 91 solidifies. Since the growth takes the concavo-convex as a starting point, the grains become smaller on the semiconductor element 40 side. In particular, the grains at a position closer to the center of the semiconductor element 40 become smaller in a planar view.

[0113] <Summary of Second Embodiment>

[0114] According to the structure described in this embodiment, the same effect as the structure described in the previous embodiment can be achieved. Specifically, the end of the partition portion 453 is in a continuous concave-convex shape. In this way, since the grains grow starting from the concave-convex of the protective film 45, the grain size becomes smaller on the semiconductor element 40 side. As a result, the EM life can be improved as in the previous embodiment.

[0115] In addition, a concavo-convex portion 454 is provided at the end of the partition portion 453 passing through the center of the semiconductor element 40. The solder particle size decreases as it is closer to the concavo-convex portion 454 in plan view, and increases as it is farther away. That is, the particle size of the solder 91 decreases near the center of the semiconductor element 40. In particular, the solder particle size on the diode region 411d can be reduced near the center where the temperature increases and EM is promoted.

[0116] The configuration of the partitioning portion 453 is not limited to the above-mentioned example. For example, the partitioning portion 453 may be configured in a planar cross shape to roughly divide the Ni electrode 423 into four equal parts. The partitioning portion 453 includes a portion extending in the X direction and a portion extending in the Y direction. In such a structure, the concave-convex portions 454 may be provided at both ends of the portion extending in the X direction, and the concave-convex portions may be provided at both ends of the portion extending in the Y direction. Of course, the concave-convex portions 454 may also be provided on both the portion extending in the X direction and the portion extending in the Y direction.

[0117] The example in which the concavo-convex part 454 is provided over the entire length of the partition part 453 is shown, but the present invention is not limited thereto. The concavo-convex part 454 may be provided over at least a portion of the entire length of the partition part 453. In addition, the concavo-convex part 454 may be provided only at one end instead of at both ends of the partition part 453. By making at least a portion of the end of the partition part 453 concavo-convex, the solder particle size can be reduced.

[0118] (Third embodiment)

[0119] This embodiment is a modified example based on the previous embodiment, and the description of the previous embodiment can be cited. In the previous embodiment, there is no particular mention about cooling when solidifying the solder 91. Instead, the solder 91 can be solidified by cooling from a predetermined direction.

[0120] <Manufacturing method>

[0121] An example of a manufacturing method of the semiconductor device 20 shown in the first embodiment will be described.

[0122] First, prepare the elements constituting the semiconductor device 20. Specifically, prepare the semiconductor element 40, wiring members 50, 60, conductive spacer 70, and external connection terminal 80. At this time, prepare the semiconductor element 40 having the concavo-convex portion 4231 on the surface of the Ni electrode 423. For example, prepare the wiring member 60, prepare a lead frame including a main terminal 82 and a signal terminal 83.

[0123] Next, the semiconductor element 40 is arranged on the opposing surface 60a of the wiring member 60 via the solder 93. The semiconductor element 40 is arranged on the solder 93 so that the collector electrode 43 faces the wiring member 60. Next, the conductive spacer 70 is arranged on the emitter electrode 42 via the solder 91. Solder 92 is arranged on the surface of the conductive spacer 70 opposite to the semiconductor element 40. The solder 92 is arranged in an amount that can absorb the height deviation in the semiconductor device 20. The solders 91, 92, and 93 are provided, for example, as solder foils. The solder 92 can also be applied to the conductive spacer 70 as a pre-solder.

[0124] In this stacked state, the first reflow is performed to obtain a connection body in which the semiconductor element 40 , the wiring member 60 , and the conductive spacer 70 are stacked and integrally connected. Next, the pad 44 of the semiconductor element 40 is connected to the signal terminal 83 by the bonding wire 90 .

[0125] Next, the wiring member 50 is placed on one surface of a base (not shown) with the facing surface 50a facing upward. The above-mentioned connection body is placed on the wiring member 50 so that the solder 92 faces the wiring member 50, and the second reflow is performed. In the second reflow, a load is applied in the Z direction from the wiring member 60 side so that the height of the semiconductor device 20 becomes a predetermined height.

[0126] Next, the sealing body 30 is formed. Although not shown in the figure, in the present embodiment, the sealing body 30 is formed by a transfer mold method. The sealing body 30 is formed so as to completely cover the wiring components 50 and 60, and is cut after forming. The sealing body 30 is cut together with a part of the wiring components 50 and 60. Thus, the back surface 50b and 60b are exposed. The back surface 50b is roughly coplanar with the one surface 30a, and the back surface 60b is roughly coplanar with the back surface 30b.

[0127] Alternatively, the sealing body 30 may be formed while the back surfaces 50b and 60b are pressed and brought into close contact with the cavity wall surface of the forming mold. In this case, when the sealing body 30 is formed, the back surfaces 50b and 60b are exposed from the sealing body 30. Therefore, cutting after forming is no longer necessary.

[0128] Next, unnecessary portions of the lead frame such as tie bars and the outer peripheral frame are removed, thereby obtaining the semiconductor device 20 .

[0129] <Cooling of Solder 91>

[0130] Fig.12 is a cross-sectional view showing the cooling process during the first reflow. Fig.12 In the figure, the solder 92 is omitted for convenience.

[0131] In this embodiment, if Fig.12 As shown, in the cooling after heating during reflow, the connection body is cooled from the wiring member 60 side. As a result, the solder 91 is cooled first from the semiconductor element 40 side. The solder 91 solidifies from the semiconductor element 40 side. The solder 91 starts to grow grains starting from the concavo-convex originating from the Ni electrode 423 when solidifying. By cooling from the wiring member 60 side, the growth of grains starting from the concavo-convex can be promoted.

[0132] <Summary of the Third Embodiment>

[0133] According to the present embodiment, in the cooling after the heating in the reflow, the connection body is cooled from the wiring component 60 side. That is, the solder 91 is cooled in such a way that the semiconductor element 40 side is cooled earlier than the conductive spacer 70 side. As a result, the solder 91 solidifies from the semiconductor element 40 side. As a result, it is possible to promote the situation where the grain growth occurs starting from the concave and convex originating from the Ni electrode 423. Therefore, the grain size becomes smaller on the semiconductor element 40 side. That is, by the above-mentioned cooling, at least in the portion overlapping with the diode region 411d, the small grain size of the solder 91 on the semiconductor element 40 side can be promoted.

[0134] The above-mentioned cooling may be combined with the structure described in the second embodiment. Since the solder 91 solidifies from the semiconductor element 40 side, it is possible to promote the growth of grains starting from the concavities and convexities of the partitioning portion 453 of the protective film 45 .

[0135] (Fourth embodiment)

[0136] This embodiment is a modified example based on the previous embodiment, and the description of the previous embodiment can be cited. In the previous embodiment, the particle size of the semiconductor element 40 side in the solder 91 is made smaller by careful design of the semiconductor element 40. Alternatively, the solder particle size on the semiconductor element 40 side can also be made smaller by careful design of the solder 91.

[0137] Fig.13 It is a cross-sectional view showing the upper structure of an element in the semiconductor device 20 of the present embodiment. Fig.13 It is a cross-sectional view showing an enlarged view of the periphery of the emitter electrode 42 . Fig.13 Corresponds to Figure 7 .

[0138] like Fig.13 As shown, conductive balls 94 are added to the solder 91. The balls 94 are mainly composed of Ni or Cu. Such balls 94 may be referred to as Ni balls or Cu balls. The balls 94, for example, ensure the minimum thickness of the solder 91. Due to the presence of the balls 94, the solder 91 undergoes grain growth starting from the balls 94 when solidifying. Since the balls 94 are used as the starting point, the grain size on the semiconductor element 40 side becomes smaller than that of the structure without the balls 94. At least in the portion overlapping with the diode region 411d, the grain size of the solder 91 on the semiconductor element 40 side becomes smaller than the grain size on the conductive spacer 70 side.

[0139] <Summary of the Fourth Embodiment>

[0140] According to the structure described in this embodiment, the same effect as the structure described in the previous embodiment can be achieved. Specifically, by adding the ball 94 to the solder 91, the grain growth is carried out starting from the ball 94, and the grain size becomes smaller on the semiconductor element 40 side. As a result, at least in the portion overlapping with the diode region 411d, the grain size of the solder 91 on the semiconductor element 40 side is smaller than the grain size on the conductive spacer 70 side. As a result, the EM life can be improved.

[0141] In addition, the effect of the ball 94 was also confirmed by trial production. It was confirmed that the particle size of the solder 91 on the semiconductor element 40 side was reduced by adding the ball 94. In addition, it was confirmed that the disappearance of the alloy layer 100 was slowed down, that is, the progress of EM could be slowed down. At this time, the Ni electrode 423 was formed by non-electrolytic NiP plating. The composition of the alloy layer 100 is (Ni-Cu)3Sn4.

[0142] <Modification>

[0143] The solder 91 may be formed into a multi-layer structure so that the occupancy rate of the balls 94 per unit volume varies according to the layers. Fig.14 In the example shown, the solder 91 has a first layer 911 and a second layer 912. The first layer 911 is a layer on the semiconductor element 40 side, and the second layer 912 is a layer on the conductive spacer 70 side. The first layer 911 is the layer closest to the semiconductor element 40, and the second layer 912 is a remaining layer after the first layer 911 is removed. Fig.14 Corresponds to Fig.13 .exist Fig.14 , for convenience, the grain boundary 910 is omitted.

[0144] exist Fig.14 In the example shown, the occupancy rate of balls 94 in the first layer 911 is higher than that in the second layer 912. The first layer 911 has more balls 94 than the second layer 912. This can further enhance the effect of reducing the particle size of the solder 91 on the semiconductor element 40 side.

[0145] Alternatively, the diameters of balls 94 may be different in first layer 911 and second layer 912, so that the occupancy rate of balls 94 in first layer 911 is higher than that in second layer 912. The number and diameter of balls may be different.

[0146] The above structure can be realized by arranging two layers of solder foils having different ball contents, for example. Alternatively, three layers of solder foils without balls may be stacked so that the number and / or diameter of the balls 94 arranged between the respective solder foils are different.

[0147] The number of layers of solder 91 is not limited to two, but may be three or more. Even if there are three or more layers, the occupancy rate of balls 94 in the first layer 911 closest to semiconductor element 40 is higher than the occupancy rate of balls 94 in the remaining layers.

[0148] (Fifth embodiment)

[0149] This embodiment is a modified example based on the previous embodiment, and the description of the previous embodiment can be cited. In the previous embodiment, there is no particular mention of cooling when solidifying the solder 91 with the balls 94 added. Instead, the solder 91 can be solidified by cooling from a predetermined direction.

[0150] Fig.15 It is a cross-sectional view showing the cooling process during reflow. Fig.15 Corresponds to Fig.12 .

[0151] In this embodiment, if Fig.15 As shown, in the cooling after the heating in the reflow, the connection body is cooled from the conductive spacer 70 side. The thermal resistance of the heat transfer path to the solder 91 is smaller on the conductive spacer 70 side than on the wiring member 60 side. By cooling from the conductive spacer 70 side, the ball 94 is cooled faster. Since the solder 91 starts to aggregate with the ball 94 as the starting point, the grain growth with the ball 94 as the starting point can be promoted by cooling from the conductive spacer 70 side.

[0152] <Summary of the Fifth Embodiment>

[0153] According to the present embodiment, during the cooling after the heating during the reflow, the connection body is cooled from the conductive spacer 70 side. As a result, the ball 94 is cooled relatively quickly. As a result, the grain growth of the solder 91 starting from the ball 94 can be promoted. Therefore, in at least the portion overlapping with the diode region 411d, the small grain size of the solder 91 on the semiconductor element 40 side can be promoted.

[0154] <Modification>

[0155] In a structure where the semiconductor element 40 or the solder 91 is not carefully designed as described above, the connection body may be cooled from the conductive spacer 70 side. In this case, the solder 91 solidifies from the conductive spacer 70 side. Fig.16 As shown, a liquid portion 913 remains on the semiconductor element 40 side. The liquid portion 913 and a solidified portion 914 are mixed in the solder 91. The liquid portion 913 is an unsolidified portion of the solder 91, that is, a portion in a molten state. Fig.16 Corresponds to Fig.15 .

[0156] As the solder 91 solidifies, the voids 915 such as microvoids and impurities gather in the liquid portion 913. As a result, when the liquid portion 913 solidifies, grain growth proceeds starting from the voids 915. As a result, at least in the portion overlapping the diode region 411d, the particle size of the solder 91 on the semiconductor element 40 side can be made smaller than the particle size on the conductive spacer 70 side.

[0157] (Other embodiments)

[0158] The disclosure in this specification and the drawings, etc. is not limited to the illustrated embodiments. The disclosure includes the illustrated embodiments and the modified forms made by those skilled in the art based thereon. For example, the disclosure is not limited to the combination of parts and / or elements shown in the embodiments. The disclosure can be implemented through a variety of combinations. The disclosure may have additional parts that can be added to the embodiments. The disclosure includes forms in which parts and / or elements of the embodiments are omitted. The disclosure includes replacement or combination of parts and / or elements between one embodiment and other embodiments. It should be understood that the technical scope of the disclosure is not limited to the description of the embodiments. Certain technical scopes of the disclosure are represented by the description of the claims, and also include all changes within the meaning and scope equivalent to the description of the claims.

[0159] The disclosure in the specification and drawings is not limited by the claims. The disclosure in the specification and drawings includes the technical ideas described in the claims, and also involves more diverse and extensive technical ideas than the technical ideas described in the claims. Therefore, it is possible to extract a variety of technical ideas from the disclosure in the specification and drawings without being restricted by the claims.

[0160] When a certain element or layer is referred to as being "on", "connected", "connected" or "bonded to", it may be directly on, connected, connected or bonded to other elements or layers, and there may be spacing elements or spacing layers. In contrast, when a certain element is referred to as being "directly on", "directly connected", "directly connected" or "directly bonded to" other elements or layers, there are no spacing elements or spacing layers. Other words used to describe the relationship between elements should be interpreted in the same manner (for example, "between" versus "directly between", "adjacent" versus "directly adjacent", etc.). When used in this specification, the term "and / or" includes any and all combinations related to the associated listed one or more items.

[0161] Spatially relative terms such as "inside", "outside", "back", "below", "low", "upper", "high", etc. are used here to facilitate the description of the relationship between an element or feature and other elements or features as shown in the illustration. Spatially relative terms can mean that in addition to the orientation depicted in the drawings, different orientations of the device in use or operation are also included. For example, if the device in the figure is turned over, the element described as "below" or "directly below" other elements or features is oriented "above" other elements or features. Therefore, the term "below" can include both upper and lower orientations. The device can also be oriented in other directions (it can also be rotated to 90 degrees or other orientations), and the spatially relative descriptors used in this specification can be interpreted accordingly.

[0162] The vehicle drive system 1 is not limited to the above-mentioned structure. For example, an example is shown in which a single electric generator 3 is provided, but the present invention is not limited thereto. A plurality of electric generators may also be provided. An example is shown in which the power conversion device 4 is provided with an inverter 6 as a power conversion unit, but the present invention is not limited thereto. For example, a structure may be provided with a plurality of inverters. A structure may also be provided with at least one inverter and a converter. A converter may also be provided only.

[0163] The structure of the semiconductor device 20 is not limited to the above example. The semiconductor device 20 may include at least a semiconductor element, an upper conductor, a solder for bonding an upper electrode of the semiconductor element to the upper conductor, and an alloy layer interposed between the upper electrode and the solder.

[0164] The wiring member 50 may be provided with a protrusion instead of the conductive spacer 70. In this case, the wiring member 60 corresponds to the upper conductor.

[0165] Although the semiconductor device 20 is an example of a double-sided heat dissipation structure, it is not limited thereto. It can also be applied to a single-sided heat dissipation structure. For example, the collector electrode 43 is connected to a metal body of a heat sink or a substrate, and the emitter electrode 42 is connected to a lead. In this case, the lead is equivalent to the upper conductor.

[0166] The example in which the semiconductor device 20 has only one semiconductor element 40 constituting one arm is shown, but the present invention is not limited thereto. The semiconductor device 20 may also have a plurality of semiconductor elements 40 constituting one arm. That is, a plurality of semiconductor elements 40 may be connected in parallel to each other to constitute one arm. In addition, the semiconductor device 20 may also have a plurality of semiconductor elements 40 constituting one-phase upper and lower arm circuits 9. It may also have a plurality of semiconductor elements 40 constituting multiple-phase upper and lower arm circuits 9.

[0167] The arrangement of the IGBT regions 411i and the diode regions 411d is not particularly limited. Instead of the alternating arrangement in the X direction, an alternating arrangement in the Y direction may be adopted. Instead of the stripe arrangement, an arrangement in which the diode regions 411d provided in islands are scattered may be adopted.

[0168] An example is shown in which the back surfaces 50b and 60b of the wiring members 50 and 60 are exposed from the sealing body 30, but the present invention is not limited thereto. A structure in which at least one of the back surfaces 50b and 60b is covered by the sealing body 30 may be adopted. A structure in which at least one of the back surfaces 50b and 60b is covered by an insulating member (not shown) different from the sealing body 30 may be adopted. A structure in which the semiconductor device 20 does not include the sealing body 30 may also be adopted.

[0169] An example in which the area of ​​the diode region 411d is smaller than the area of ​​the IGBT region 411i is shown, but the present invention is not limited thereto. The present invention can also be applied to a structure in which the area of ​​the diode region 411d is substantially equal to the area of ​​the IGBT region 411i, or a structure in which the area of ​​the IGBT region 411i is smaller than the area of ​​the diode region 411d. In addition, when the area of ​​the IGBT region 411i is small, the EM life is not likely to become a problem. The direction in which the main current flows is the opposite direction to the direction in which the freewheeling current flows. When the main current flows, electrons move from the conductive spacer 70 side toward the semiconductor element 40 side. Since the area of ​​the conductive spacer 70 is large, the EM life is not likely to become a problem.

[0170] (Disclosure of technical ideas)

[0171] This specification discloses multiple technical ideas recorded in the following multiple items. Some items are recorded in a multiple dependent form that selectively refers to the preceding item in the subsequent item. Furthermore, some items are recorded in a multiple dependent form that refers to another multiple dependent form. These items recorded in multiple dependent forms define multiple technical ideas.

[0172] <Technical Thought 1>

[0173] A semiconductor device comprises: a semiconductor element (40) having a semiconductor substrate (41) including an IGBT region (411i) and a diode region (411d), and an upper electrode (42) arranged on one side of the semiconductor substrate; an upper conductor (70) arranged opposite to the upper electrode; an upper solder (91) interposed between the upper electrode and the upper conductor to join the upper electrode and the upper conductor; and an alloy layer (100) interposed between the upper electrode and the upper solder; the upper electrode having an Al electrode (422) arranged on the one side and a Ni electrode (423) arranged on the Al electrode; the upper solder containing Cu and Sn; the alloy layer containing Ni, Cu and Sn; for the upper solder, in a planar observation in the plate thickness direction of the semiconductor substrate, at least in a portion overlapping with the diode region, the particle size on the semiconductor element side is smaller than the particle size on the upper conductor side.

[0174] <Technical Thoughts 2>

[0175] In the semiconductor device as described in technical idea 1, the semiconductor element has a lower electrode (43) arranged on the back side of the semiconductor substrate; the semiconductor device also has a lower conductor (60) arranged opposite to the lower electrode, and a lower solder (93) interposed between the lower electrode and the lower conductor and connecting the lower electrode and the lower conductor; the particle size of the upper solder on the semiconductor element side in at least the portion overlapping with the diode region is smaller than the particle size of the lower solder.

[0176] <Technical Thought 3>

[0177] In the semiconductor device according to the technical idea 1 or the technical idea 2, the Ni electrode has a concavoconvex portion (4231) in which concavoconvexities are continuously formed at least on the surface of the portion overlapping the diode region.

[0178] <Technical Thought 4>

[0179] In a semiconductor device as described in Technical Idea 1 or Technical Idea 2, the semiconductor element has a protective film (45), which is arranged on one surface of the semiconductor substrate and has an opening portion (451) for exposing the Ni electrode in a bondable manner and a dividing portion (453) for dividing the Ni electrode into a plurality of areas; in the above-mentioned plane observation, the end portions of the above-mentioned dividing portions are continuous concave and convex.

[0180] <Technical Thought 5>

[0181] In the semiconductor device according to the technical idea 1 or the technical idea 2, conductive balls (94) are added to the upper solder.

[0182] <Technical Thought 6>

[0183] In the semiconductor device described in Technical Idea 5, the upper solder is a multi-layer structure; the occupancy rate of the balls per unit volume in the upper solder is higher in the first layer (911) closest to the semiconductor element than in the remaining layers (912) except the first layer.

[0184] <Technical Thought 7>

[0185] In the semiconductor device according to the fifth or sixth technical idea, the ball contains Ni or Cu.

[0186] <Technical Thought 8>

[0187] In the semiconductor device according to any one of technical concepts 1 to 7, the Ni electrode is a Ni plating film containing P.< / em>

Claims

1. A semiconductor device, characterized in that: have: A semiconductor element (40) comprising a semiconductor substrate (41) including an IGBT region (411i) and a diode region (411d), and an upper electrode (42) arranged on one surface of the semiconductor substrate; An upper conductor (70) is arranged opposite to the upper electrode; An upper solder (91) is disposed between the upper electrode and the upper conductor to bond the upper electrode to the upper conductor; as well as An alloy layer (100) is disposed between the upper electrode and the upper solder; The upper electrode comprises an Al electrode (422) arranged on the one surface and a Ni electrode (423) arranged on the Al electrode; The upper solder contains Cu and Sn; The alloy layer contains Ni, Cu and Sn; The upper solder has a smaller grain size on the semiconductor element side than on the upper conductor side in at least a portion overlapping the diode region in a planar view in the thickness direction of the semiconductor substrate.

2. The semiconductor device according to claim 1, wherein The semiconductor element has a lower electrode (43) arranged on the back surface of the semiconductor substrate; The semiconductor device further comprises a lower conductor (60) arranged to face the lower electrode, and a lower solder (93) interposed between the lower electrode and the lower conductor and connecting the lower electrode and the lower conductor. The particle size of the upper solder on the semiconductor element side in at least a portion overlapping the diode region is smaller than the particle size of the lower solder.

3. The semiconductor device according to claim 1 or 2, wherein: The Ni electrode has a concavoconvex portion (4231) having concavoconvexities continuously formed on at least the surface of the portion overlapping the diode region.

4. The semiconductor device according to claim 1 or 2, wherein: The semiconductor element has a protective film (45), which is arranged on one surface of the semiconductor substrate and has an opening (451) for exposing the Ni electrode so that it can be bonded, and a partitioning portion (453) for partitioning the Ni electrode into a plurality of partitions. In the above-mentioned planar observation, the end portion of the above-mentioned division portion has a continuous concavo-convex shape.

5. The semiconductor device according to claim 1 or 2, wherein: Conductive balls (94) are added to the upper solder.

6. The semiconductor device according to claim 5, wherein: The above-mentioned upper solder is a multi-layer structure; The occupancy rate of the balls per unit volume in the upper solder is higher in the first layer (911) closest to the semiconductor element than in the remaining layers (912) except the first layer.

7. The semiconductor device according to claim 5, wherein: The above-mentioned balls contain Ni or Cu.

8. The semiconductor device according to claim 1 or 2, wherein: The Ni electrode is a Ni plating film containing P.

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