Federal learning Krum algorithm hardware acceleration and optimization system and method

Abstract

The invention relates to a federated learning Krum algorithm hardware acceleration and optimization system and method, and belongs to the technical field of federated learning and hardware acceleration. Comprising a data control module, a data FIFO module and an algorithm calculation module. The data control module, the data FIFO module and the algorithm calculation module are connected in sequence, and the data control module is connected with the algorithm calculation module; the data control module is used for pipeline control of the whole Krum algorithm; the data FIFO module is used for caching gradient parameters of a client model on one side and circularly reading the gradient parameters; and the algorithm calculation module is used for calculating a krum algorithm, including Euclidean distance calculation and minimum gradient calculation. And each module is independent and has definite functions and is responsible for specific tasks, so that the maintainability and expandability of the algorithm and the flexibility of performance optimization are improved.

Description

Technical Field

[0001] The present invention relates to a federated learning Krum algorithm hardware acceleration and optimization system and method, and belongs to the technical field of federated learning and hardware acceleration. Background Art

[0002] As the demand for data privacy protection continues to increase, Federated Learning, as a distributed machine learning framework, has gradually received widespread attention and application. Federated Learning enables the construction of a global model by allowing multiple parties to train their own data locally and only share model parameter updates. This method not only effectively reduces the risk of data leakage and privacy exposure, but also alleviates the data island problem to a certain extent. However, in practical applications, the open federated learning environment brings new security and stability challenges, especially threats from malicious participants.

[0003] In federated learning scenarios, the trust foundation between participants is usually weak, and there is a possibility that individual malicious participants can interfere with model training in various ways. Among them, Byzantine attacks are a common and serious threat. Malicious participants can manipulate the optimization process of the global model by uploading maliciously designed model updates. These attacks may manifest as uploading random noise, forged gradients that deviate from the global goal, or even carefully designed adversarial updates. The purpose may be to destroy the convergence of the global model and cause model training failure.

[0004] To deal with Byzantine attacks, the Krum algorithm was proposed as a robust aggregation algorithm and is widely used in federated learning. The Krum algorithm calculates the Euclidean distance between the model uploaded by each participant and the models of other participants, and selects the one that is closest to the update of other models as the update result of the global model, thereby effectively identifying and excluding malicious participants whose updates deviate greatly from most models. In this way, Krum can significantly improve the robustness and stability of the federated learning system in the presence of Byzantine attacks, avoid interference of malicious updates on the global model, and ensure that the model can converge normally under harsh conditions.

[0005] However, the efficiency and robustness of the Krum algorithm also bring computational challenges. Since the algorithm needs to calculate the Euclidean distance between the model uploaded by each participant and all other models, this process usually involves a large number of matrix operations and distance calculations. Especially when the number of participants is large, the computational complexity of the Krum algorithm grows exponentially, resulting in a significant increase in the required computing resources and time. For example, when the number of participants reaches hundreds or thousands, the algorithm needs to perform thousands of distance calculations, and each calculation needs to process large-scale model parameters, which greatly prolongs the execution time of the algorithm.

[0006] Therefore, although the Krum algorithm can effectively deal with Byzantine attacks in theory, its performance bottleneck in practical applications has become a major challenge facing the federated learning system. When executing the Krum algorithm on a traditional CPU, due to the lack of sufficient parallel computing power, the calculation speed becomes relatively slow, which seriously affects the efficiency of the entire federated learning process. This computing bottleneck limits the promotion and deployment of the Krum algorithm in practical applications, especially in systems that require high throughput and real-time performance, where its performance problems are more prominent. Therefore, how to achieve efficient Krum algorithm calculations and significantly improve its computing performance has become a key issue that needs to be solved in current federated learning research.

[0007] Hardware acceleration technology, especially FPGA (field programmable gate array), has been widely used in the field of high-performance computing due to its excellent parallel computing capabilities and high customizability. However, hardware acceleration research on the Krum algorithm is still relatively scarce. Existing solutions mainly focus on software-level optimization and cannot give full play to the advantages of hardware in computing performance. Therefore, developing a Krum algorithm implementation method based on hardware acceleration can speed up the algorithm execution and improve the overall efficiency and reliability of the federated learning system. Summary of the invention

[0008] In view of the shortcomings of the prior art, the present invention provides a hardware acceleration and optimization system for the federated learning Krum algorithm, that is, the algorithm is implemented using the Verilog HDL language on a field programmable gate array (FPGA). The present invention greatly optimizes the algorithm execution performance by introducing an efficient distance calculation module and parallel design; secondly, the pipeline architecture design of the present invention introduces a data control module, supports data back pressure, does not require advance storage or storage after calculation, and can be calculated online in real time; finally, the hardware design also supports flexible parameter configuration, which can adapt to federated learning tasks of different scales and the number of participants, thereby improving the applicability and scalability in practical applications. The proposal of the present invention will effectively make up for the CPU performance bottleneck and provide important technical support for improving the performance of federated learning.

[0009] The present invention also provides a hardware acceleration and optimization method for the federated learning Krum algorithm.

[0010] The technical solution of the present invention is: The federated learning Krum algorithm hardware acceleration and optimization system includes a data control module, a data FIFO module and an algorithm calculation module; the data control module, the data FIFO module and the algorithm calculation module are connected in sequence, and the data control module is connected to the algorithm calculation module; The data control module is used for pipeline control of the entire Krum algorithm; the data FIFO module is used to cache the gradient parameters of the client model and perform cyclic reading; the algorithm calculation module is used to calculate the Krum algorithm, including Euclidean distance calculation and minimum gradient calculation.

[0011] Preferably, according to the present invention, a data control module is used to control the orderly flow of data and support back pressure calculation; Finite State Machine (FSM) is used to achieve orderly control of data flow; The state jump condition is dynamically adjusted according to the input data volume in_sum and the number of logic operation units ALU_MEM; In each state, there is a ppen enable signal trigger condition to control data flow and back pressure; After receiving the start signal start, the data control module uses a finite state machine to drive the transition of the data processing stage and accurately tracks the progress of the data in each processing stage through a counter; according to the current stage of the data, the ppen enable signal generated by the data control module is passed to the algorithm calculation module to control the orderly flow of data between the buffering, processing, clearing and other links to achieve efficient data transmission.

[0012] Preferably, according to the present invention, the data control module implements pipeline control of data through a finite state machine; The finite state machine includes seven states: idle state IDLE, buffering state BUFFING and BUFFING1, pipeline processing state PIPEING and PIPEING1, clearing state CLRING and CLRING1; When the input data volume in_sum is not greater than the number of logic operation modules ALU_MEM, the finite state machine enters the path buffer state BUFFING1, the pipeline processing state PIPEING1 and the clearing state CLRING1, otherwise, it enters the path buffer state BUFFING, the pipeline processing state PIPEING and the clearing state CLRING.

[0013] Three output signals are determined in each state, namely the ppen enable signal, the in_ready signal and the out_vaild signal; the ppen enable signal indicates whether the current data is calculated, that is, whether to enter the algorithm calculation module; the in_ready signal indicates whether there is still data in the algorithm calculation module, that is, whether there is data in the algorithm calculation module being calculated or whether there is data that has been calculated but not transmitted to the next module to continue calculation; the out_valid signal indicates whether there is data output.

[0014] Preferably, according to the present invention, the data control module further includes two input signals: an in_valid signal and an out_ready signal; the in_valid signal indicates whether there is data waiting to be calculated, and is a sign of data input; the out_ready signal indicates whether the backend can receive data, and is a sign of the back pressure signal; After receiving the start signal start, the data control module chooses to enter the cache state (BUFFING or BUFFING1) first according to the relationship between the input data volume in_sum and the number of logic operation modules ALU_MEM; specifically, if in_sum is less than or equal to ALU_MEM, it enters the cache state BUFFING1, otherwise, it enters the cache state BUFFING; If it is detected that there is data input waiting for calculation, that is, the in_valid signal is high, the data control module will adjust the output signals ppen enable, in_ready and out_vaild signals according to the current state (BUFFING or BUFFING1); When the data stored in the cache state is equal to the number of logical operation units ALU_MEM, and there is still data input waiting for calculation, that is, the in_valid signal continues to be high, the data control module switches to the processing state PIPEING or PIPEING1, and the output signal changes again with the state; when there is no new data input waiting for calculation, that is, the in_valid signal is low, and only data is left in the cache, the data control module enters the clearing state CLRING or CLRING1, and the output signals ppen enable signal, in_ready signal and out_vaild signal are adjusted according to the clearing state.

[0015] Preferably according to the present invention, the data FIFO module is a FIFO buffer supporting multiple readouts; The FIFO buffer is responsible for caching one bit of client model gradient and completing the calculation of the client model score by repeated reading.

[0016] Further preferably, the FIFO buffer is responsible for caching a client model gradient and completing the calculation of the client model score by repeated reading; including: Assume the number of clients is , want to calculate the client The score of the model gradient is cached in the FIFO buffer on the client side The model gradient , and Repeated reading to calculate With other clients The Euclidean distance of the corresponding model gradient; The number of readouts is controlled by a counter. After reading n-1 times, the gradient Cache until the algorithm finishes running.

[0017] Further preferably, in the data FIFO module, data caching and calculation are performed simultaneously; there is no need to wait for the client The model gradient All caching is completed, and Euclidean distance calculation with model gradients of other clients is allowed after the first gradient parameter is cached; the data FIFO module also includes a read enable signal rd_allow and a write enable quote wr_allow; when the write enable is high and the FIFO buffer is not full of data, the write enable quote wr_allow is high, and the data is written into the data FIFO module; when the read enable is high and the FIFO is not an empty signal, the data is read out.

[0018] Preferably, according to the present invention, the data calculation module includes an accumulation module, a square root module and a minimum gradient calculation module; The accumulation module is used to calculate the addition and multiplication operations of the gradient Euclidean distance between two participants; The square root module is used to perform a square root operation on the square sum result output by the accumulation module, so as to obtain the true Euclidean distance between the participants; The minimum gradient calculation module is used to select the smallest nf-1 valid values ​​from the Euclidean distances calculated by multiple participants, accumulate the selected smallest nf-1 valid values, and calculate the effective distance sum as the basis for model updating.

[0019] Further preferably, the accumulation module is used to calculate the addition operation and the multiplication operation of the gradient Euclidean distance between two participants; including: The accumulation module realizes the start control of the calculation process and the synchronization management of the data flow through the ppen enable signal generated by the data control module; specifically, when the ppen enable signal is valid, first, the absolute difference between the two input data is generated, and then the square of the current difference is obtained through the square operation; then, the input data is accumulated point by point until the counter reaches the set number of neurons, and the accumulation result is output.

[0020] Further preferably, the beat operation is delayed by delay_ppen.

[0021] Preferably, according to the present invention, in the minimum gradient calculation module, First, the Euclidean distance data calculated by each participant is received and stored in a register; Then, a parallel comparison mechanism is used to quickly compare the received distance data in the storage area, and the smallest nf-1 valid distances are selected; Finally, the selected minimum nf-1 effective distances are accumulated, the sum of the effective distances is calculated, and fed back to the front end.

[0022] The hardware acceleration and optimization method of the federated learning Krum algorithm includes: Control data pipeline operation; that is, realize data pipeline control through finite state machine; Cache the data of one participant and read it out multiple times; The Krum algorithm is calculated by reading the parameters in the FIFO buffer and the parameters of another participant in the memory; it includes: first, calculating the addition and multiplication operations of the gradient Euclidean distances of the two participants; then, performing a square root operation on the output square sum result to obtain the true Euclidean distance between the participants; finally, selecting the smallest nf-1 valid values ​​from the Euclidean distances calculated by multiple participants, accumulating the selected smallest nf-1 valid values, calculating the effective distance sum, and feeding it back to the front end.

[0023] The beneficial effects of the present invention are: 1. The present invention implements the hardware of the federated learning Krum algorithm against Byzantine attacks. The implementation adopts a modular design, realizes the data control module, the data FIFO module, and the algorithm calculation module. Each module is independent and has clear functions, and is responsible for specific tasks, which improves the maintainability, scalability and performance optimization flexibility of the algorithm.

[0024] 2. The architecture adopts pipeline architecture design, and through the data control module, the pipeline processing of data can be accurately controlled. In addition, it also supports data back pressure, without the need for pre-storage or post-calculation storage, and can be calculated online in real time.

[0025] 3. This architecture optimizes the traditional FIFO buffer and can read out data multiple times according to the counter control. In addition, this module also supports data caching and calculation at the same time to improve calculation efficiency.

[0026] 4. The architecture design supports flexible parameter configuration and can adapt to federated learning tasks of different scales and numbers of participants, improving the applicability and scalability in practical applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is a schematic diagram of the architecture of the federated learning Krum algorithm hardware acceleration and optimization system of the present invention; Figure 2 It is a schematic diagram of the finite state machine of the data control module; Figure 3 This is a schematic diagram of the federated learning model architecture; Figure 4 This is a schematic diagram for comparing the performance of the Krum algorithm. DETAILED DESCRIPTION

[0028] The present invention will be further defined below in conjunction with the accompanying drawings and embodiments, but is not limited thereto.

[0029] Example 1 The federated learning Krum algorithm hardware acceleration and optimization system includes a data control module, a data FIFO module and an algorithm calculation module; the data control module, the data FIFO module and the algorithm calculation module are connected in sequence, and the data control module is connected to the algorithm calculation module; The data control module is used for pipeline control of the entire Krum algorithm; the data FIFO module is used to cache the gradient parameters of the client model and perform cyclic reading; the algorithm calculation module is used to calculate the Krum algorithm, including Euclidean distance calculation and minimum gradient calculation.

[0030] As shown in Table 1, the Krum algorithm is a robust aggregation method used in federated learning to prevent malicious participants or data pollution from negatively affecting the global model training process. The algorithm calculates the similarity between each client model update and other client model updates, and selects those updates that are closest to most other model updates, thereby ensuring the quality and stability of the global model. This method can effectively identify and exclude abnormal or malicious model updates, thereby improving the robustness and defense capabilities of the system.

[0031] Table 1 Krum algorithm;

[0032] A first-in, first-out buffer (FIFO) is a cache mechanism that accesses data in the order in which it enters. The earliest data is read first. It manages the data flow through write pointers and read pointers to ensure that the data is processed in order. FIFO is widely used in computer systems, hardware design and other fields, especially in pipeline processing, data flow management and buffer storage. The advantages of FIFO are simple implementation, high efficiency, and the ability to maintain data order consistency.

[0033] Example 2 The difference between the federated learning Krum algorithm hardware acceleration and optimization system described in Example 1 is that: The design of the present invention adopts a pipeline architecture design, uses a data control module to be responsible for orderly control of data flow, and supports back pressure calculation; there is no need for advance storage or storage after calculation, and online real-time calculation can be performed and calculation can be paused at any time without losing data.

[0034] Finite State Machine (FSM) is used to realize orderly control of data flow; FSM is widely used in hardware control circuit design. It decomposes complex control logic into a finite number of stable states. Each state corresponds to a specific configuration of the system, and the transition between states is determined by predetermined rules. Finite state machine mainly includes four basic elements: state, input, state transfer and output. Because finite state machine has a finite number of states, it can be implemented in actual engineering. But this does not mean that it can only perform a finite number of processing. On the contrary, finite state machine is a closed-loop system, finite and infinite, and can use finite states to process infinite transactions.

[0035] The state jump condition is dynamically adjusted according to the input data volume in_sum and the number of logic operation units ALU_MEM; In each state, there is a ppen enable signal trigger condition to control data flow and back pressure; After receiving the start signal start, the data control module uses a finite state machine to drive the transition of the data processing stage and accurately tracks the progress of the data in each processing stage through a counter; according to the current stage of the data, the ppen enable signal generated by the data control module is passed to the algorithm calculation module to control the orderly flow of data between the buffering, processing, clearing and other links to achieve efficient data transmission.

[0036] like Figure 2 As shown, the data control module realizes the pipeline control of data through a finite state machine; The finite state machine includes seven states: idle state IDLE, buffering state BUFFING and BUFFING1, pipeline processing state PIPEING and PIPEING1, clearing state CLRING and CLRING1; Specifically, the finite state machine can be divided into two paths, IDLE-BUFFING-PIPEING-CLRING and IDLE-BUFFING1-PIPEING1-CLRING1. The path that the data enters is determined by the input data volume in_sum and the number of logic operation modules ALU_MEM. The data volume in_sum is the number of input data, and the logic operation module is the module unit that needs to be entered to perform the entire calculation operation, such as Figure 1 The number of modules required to execute the Krum algorithm is 3 (accumulation, square root, minimum gradient calculation), so ALU_MEM=3. When the input data volume in_sum is not greater than the number of logic operation modules ALU_MEM, that is, if in_sum<=3 in this algorithm, the finite state machine enters the path buffer state BUFFING1, the pipeline processing state PIPEING1 and the clearing state CLRING1 to ensure fast processing and resource optimization when the data volume is small; otherwise, it enters the path buffer state BUFFING, the pipeline processing state PIPEING and the clearing state CLRING. Processing is performed in the conventional pipeline mode.

[0037] Three output signals are determined in each state, namely, the ppen enable signal, the in_ready signal, and the out_vaild signal; the ppen enable signal indicates whether the current data is calculated, that is, whether it enters the algorithm calculation module; the in_ready signal indicates whether there is still data in the algorithm calculation module, that is, whether there is data in the algorithm calculation module being calculated or whether there is data that has been calculated but not transferred to the next module for further calculation; the out_valid signal indicates whether there is data output. The three signals cooperate with each other to determine the order in which data flows into the algorithm calculation module.

[0038] The data control module also includes two very important input signals: in_valid signal and out_ready signal; the in_valid signal indicates whether there is data waiting to be calculated, which is a sign of data input; the out_ready signal indicates whether the backend can receive data, which is a sign of the back pressure signal; The data control module generates a ppen enable signal through different states of the state machine and passes it to the computing module to dynamically schedule computing resources, thereby accurately controlling the pipeline processing of data. Through this mechanism, the module can efficiently coordinate the input, processing and output of data in different states, ensuring the orderly execution of computing tasks and the optimal use of resources, significantly improving the overall computing performance and system throughput.

[0039] After receiving the start signal start, the data control module chooses to enter the cache state (BUFFING or BUFFING1) first according to the relationship between the input data volume in_sum and the number of logic operation modules ALU_MEM; specifically, if in_sum is less than or equal to ALU_MEM, it enters the cache state BUFFING1, otherwise, it enters the cache state BUFFING; If it is detected that there is data input waiting for calculation, that is, the in_valid signal is high, the data control module will adjust the output signals ppen enable, in_ready and out_vaild signals according to the current state (BUFFING or BUFFING1); In the current state, whether it is BUFFING or BUFFING1, ppen is equal to in_valid. When in_valid is high level 1, ppen is also 1. In addition, out_valid is always low level 0, and in_ready is always high level 1 at this time. Because the data has not been cached, out_valid=0 must have no data output, and in_ready=1 must require data for calculation later. When the data stored in the cache state is equal to the number of logical operation units ALU_MEM, and there is still data input waiting for calculation, that is, the in_valid signal continues to be high, the data control module switches to the processing state PIPEING or PIPEING1, and the output signal changes again with the state; when there is no new data input waiting for calculation, that is, the in_valid signal is low, and only data is left in the cache, the data control module enters the clearing state CLRING or CLRING1, and the output signals ppen enable signal, in_ready signal and out_vaild signal are adjusted according to the clearing state.

[0040] In order to optimize the algorithm execution performance and improve the overall algorithm operation speed, the present invention improves the traditional first-in-first-out (FIFO) buffer and designs a FIFO buffer that flexibly supports multiple reads. Specifically, as shown in the formula As shown, each client needs to calculate the Euclidean distance with the local model gradient of other clients. If the model gradient of the client is repeatedly requested for each calculation, the calculation efficiency will be greatly reduced. Therefore, in order to improve the calculation performance, the present invention fixes the model gradient of a client and calculates the Euclidean distance between it and the model gradient of other participants. To this end, the improved FIFO buffer adds a counter to control the number of readouts, and the maximum value is determined by the number n of federated learning participants. In addition, the FIFO buffer also supports configuration of data width and depth to meet the needs of different clients and model gradients.

[0041] The data FIFO module is a FIFO buffer that supports multiple reads; In order to reduce the performance loss caused by repeated reading of memory data, the present invention optimizes the traditional first-in-first-out (FIFO) buffer and designs a data FIFO module. The FIFO buffer is responsible for caching a client model gradient and completing the calculation of the client model score by repeated reading.

[0042] The FIFO buffer is responsible for caching one client model gradient and completing the calculation of the client model score by repeated reading; including: Specifically, as shown in the protocol Krum algorithm, assuming the number of clients is , want to calculate the client The score of the model gradient is cached in the FIFO buffer on the client side The model gradient , and Repeated reading to calculate With other clients The Euclidean distance of the corresponding model gradient; To this end, the improved FIFO buffer adds a counter to control the number of readouts. The maximum value is determined by the number of federated learning participants n. Since the number of federated learning participants is determined before the algorithm is executed, if the number of participants is assumed to be n, the number of readout controls is n-1 times. After reading n-1 times, the gradient Cache until the algorithm finishes running.

[0043] In the data FIFO module, data caching and calculation are performed simultaneously to improve calculation efficiency. Still taking the above example, in order to save time, the data FIFO module does not need to wait for the client The model gradient All caches are completed, allowing the Euclidean distance calculation with other client model gradients after the first gradient parameter is cached; specifically, in addition to the empty signal (empty) and full signal (full) of the traditional FIFO, the data FIFO module also includes a read enable signal rd_allow and a write enable quote wr_allow; when the write enable is high, the write enable is high and is controlled by the host computer. The signal is given to indicate that the write operation can be performed, and the FIFO buffer is not full of data (!full), then the write enable quote wr_allow is high, and the data is written into the data FIFO module; when the read enable (read enable is controlled by the krum calculation module, and the signal is given to indicate that the data is to be read and the data is calculated) is high and the FIFO is not an empty signal (!empty), the data is read out. Through this design, the module can start the calculation process in advance when the gradient has not been fully cached, greatly shortening the intermediate calculation waiting time, thereby further improving the overall calculation performance and efficiency.

[0044] The data calculation module includes an accumulation module, a square root module and a minimum gradient calculation module; The accumulation module is used to calculate the addition and multiplication operations of the gradient Euclidean distance between two participants; The square root module is used to perform the square root operation on the square sum result output by the accumulation module, so as to obtain the real Euclidean distance between the participants; the square root module directly uses the cordic IP core officially provided by Xilinx to implement the square root operation to complete the square root operation of the square sum, and the output is d_data and r_data, which represent the quotient and remainder respectively.

[0045] The minimum gradient calculation module is used to select the smallest nf-1 valid values ​​from the Euclidean distances calculated by multiple participants to eliminate the influence of abnormal participants and ensure the accuracy of model updates. Subsequently, the selected smallest nf-1 valid values ​​are accumulated to calculate the effective distance sum as the basis for model updates.

[0046] The accumulation module is used to calculate the addition and multiplication operations of the gradient Euclidean distance between two participants; including: The accumulation module realizes the start control of the calculation process and the synchronization management of the data flow through the ppen enable signal generated by the data control module; specifically, when the ppen enable signal is valid, first, the absolute difference between the two input data is generated by the difference calculation and absolute value extraction circuit, and the square of the current difference is further obtained by the square operation; then, the input data is accumulated point by point through the cooperation of the counter and the accumulator, until the counter reaches the set number of neurons (NEURON_NUM), and then the accumulation result (o_data) is output.

[0047] To achieve delayed synchronization of the ppen signal, the delay_ppen delay beat operation is used to ensure the correctness of the pipeline operation. The ppen signal is only delayed by one clock beat, which significantly improves the computing efficiency.

[0048] In the minimum gradient calculation module, First, the Euclidean distance data calculated by each participant is received and stored in a register; Then, in order to achieve efficient data screening and comparison, a parallel comparison mechanism is adopted to quickly compare the received distance data in the storage area and screen out the smallest nf-1 valid distances; through this parallel comparison method, the module can exclude the influence of outliers and abnormal participants in the processing process to ensure the reliability of the calculation results.

[0049] Finally, the selected minimum nf-1 effective distances are accumulated, the sum of the effective distances is calculated, and fed back to the front end.

[0050] The front end collects the sum of the effective distances of all clients and selects the minimum gradient data as the model parameters for this round. If the federated learning training paper is completed, the parameters are the final model parameters. If the federated learning task needs to be continued, the model parameters need to be sent down as a new round of global model for training.

[0051] In order to verify the acceleration effect of the present invention, the algorithm was implemented on the host CPU, GPU and FPGA respectively and comparative experiments were carried out. In the experiment, the CPU used Intel(R) Core(TM) i5-8300H @ 2.30GHz, the GPU used NVIDIA GeForce GTX 1060, and the FPGA used Stratix V GX development board. PCIE used gen3x8 and ran at 400MHz. The experimental design aims to evaluate the acceleration performance of the Krum algorithm implemented in hardware. Field Programmable Gate Array (FPGA) is a chip that can change its internal structure through programming, with high flexibility and configurability. It can optimize and accelerate the algorithm at the hardware level. It contains multiple logic cells (Logic Cell), each of which consists of components such as lookup tables (LUTs) and flip-flops (Flip-Flops), and can implement complex combinational and sequential logic. Users write programs in hardware description languages ​​(such as Verilog or VHDL) to define the functions of logic circuits, and FPGA configures its hardware resources according to these programs to achieve efficient parallel processing and customized computing. Due to its flexibility and efficient parallel computing capabilities, FPGA is widely used in accelerated data processing, communications, image processing, artificial intelligence and other fields.

[0052] Implement the federated learning algorithm on the host PC and generate local model gradients. This experiment uses the classic MNIST dataset, which contains handwritten digit images covering 10 categories, and the size of each image is 28x28 pixels. Figure 3 As shown in the figure, a simple convolutional neural network (CNN) suitable for the federated learning framework was selected. The model consists of a convolutional layer (Convolutional Layer 1) with a convolution kernel of 5x5 and 32 channels, followed by a 2x2 max pooling layer (Max Pooling 1) with ReLU activation function, followed by another convolutional layer (Convolutional Layer 2) with a convolution kernel of 5x5 and 64 channels, followed by a 2x2 max pooling layer (Max Pooling 2), and finally connected by two fully connected layers (Fully Connected Layer 1 and Fully Connected Layer 2). In the experiment, the model parameters are distributed among multiple clients. In order to evaluate the performance, 10 clients are set for model training. Each client only accesses local data and generates its own local model gradient. During the training process, 10 rounds of local training are performed on each client.

[0053] The Krum algorithm aims to calculate the Euclidean distance between the local model gradients of each participant and calculate their scores. The local model gradient is determined by the neural network model architecture, such as Figure 3 As shown in the figure, the amount of gradient parameters of this architecture is about 35MB.

[0054] Figure 4 The experimental results show that the CPU execution time is more than 1 second, and the stability is poor. The GPU execution time is about 0.44 seconds, which is about 2.27 times faster than the CPU, and the stability is good. The FPGA execution time is about 0.12 seconds, which is about 8.33 times faster than the CPU, about 3.67 times faster than the GPU, and the stability is the best. However, running on the FPGA involves floating-point fixed-point conversion. For this experiment, the gradient conversion time does not exceed 0.18 seconds. If the conversion time is added, the execution efficiency is still higher than that of the CPU and GPU. Therefore, compared with the CPU and GPU, the FPGA also performs well in scalability and flexibility, and can significantly improve the execution efficiency of the krum algorithm.

[0055] Example 3 The hardware acceleration and optimization method of the federated learning Krum algorithm includes: Control data pipeline operation; that is, realize data pipeline control through finite state machine; Cache the data of one participant and read it out multiple times; The Krum algorithm is calculated by reading the parameters in the FIFO buffer and the parameters of another participant in the memory; it includes: first, calculating the addition and multiplication operations of the gradient Euclidean distances of the two participants; then, performing a square root operation on the output square sum result to obtain the true Euclidean distance between the participants; finally, selecting the smallest nf-1 valid values ​​from the Euclidean distances calculated by multiple participants, accumulating the selected smallest nf-1 valid values, calculating the effective distance sum, and feeding it back to the front end.

Claims

1. The federated learning Krum algorithm hardware acceleration and optimization system is characterized by: It includes a data control module, a data FIFO module and an algorithm calculation module; the data control module, the data FIFO module and the algorithm calculation module are connected in sequence, and the data control module is connected to the algorithm calculation module; The data control module is used for pipeline control of the entire Krum algorithm; the data FIFO module is used to cache the gradient parameters of the client model and perform cyclic reading; the algorithm calculation module is used to calculate the Krum algorithm, including Euclidean distance calculation and minimum gradient calculation.

2. The federated learning Krum algorithm hardware acceleration and optimization system according to claim 1, characterized in that: The data control module is used to control the orderly flow of data and supports back pressure calculation; Finite state machine is used to realize orderly control of data flow; The state jump condition is dynamically adjusted according to the input data volume in_sum and the number of logic operation units ALU_MEM; In each state, there is a ppen enable signal trigger condition to control data flow and back pressure; After receiving the start signal start, the data control module uses a finite state machine to drive the transition of the data processing stage and accurately tracks the progress of the data in each processing stage through a counter; according to the current stage of the data, the ppen enable signal generated by the data control module is passed to the algorithm calculation module to control the orderly flow of data between the buffering, processing, and clearing links to achieve efficient data transmission.

3. The federated learning Krum algorithm hardware acceleration and optimization system according to claim 1, characterized in that: The data control module realizes the pipeline control of data through the finite state machine; The finite state machine includes seven states: idle state IDLE, buffering state BUFFING and BUFFING1, pipeline processing state PIPEING and PIPEING1, clearing state CLRING and CLRING1; When the input data volume in_sum is not greater than the number of logic operation modules ALU_MEM, the finite state machine enters the path buffer state BUFFING1, the pipeline processing state PIPEING1 and the clearing state CLRING1, otherwise, it enters the path buffer state BUFFING, the pipeline processing state PIPEING and the clearing state CLRING; Three output signals are determined in each state, namely the ppen enable signal, the in_ready signal and the out_vaild signal; the ppen enable signal indicates whether the current data is calculated, that is, whether to enter the algorithm calculation module; the in_ready signal indicates whether there is still data in the algorithm calculation module, that is, whether there is data in the algorithm calculation module being calculated or whether there is data that has been calculated but not transmitted to the next module to continue calculation; the out_valid signal indicates whether there is data output.

4. The federated learning Krum algorithm hardware acceleration and optimization system according to claim 1, characterized in that: The data control module also includes two input signals: in_valid signal and out_ready signal; the in_valid signal indicates whether there is data waiting to be calculated, which is a sign of data input; the out_ready signal indicates whether the backend can receive data, which is a sign of the back pressure signal; After receiving the start signal start, the data control module chooses to enter the cache state first according to the relationship between the input data volume in_sum and the number of logic operation modules ALU_MEM; specifically, if in_sum is less than or equal to ALU_MEM, it enters the cache state BUFFING1, otherwise, it enters the cache state BUFFING; If it is detected that there is data input waiting for calculation, that is, the in_valid signal is high, the data control module will adjust the output signals ppen enable, in_ready and out_vaild signals according to the current state; When the data stored in the cache state is equal to the number of logical operation units ALU_MEM, and there is still data input waiting for calculation, that is, the in_valid signal continues to be high, the data control module switches to the processing state PIPEING or PIPEING1, and the output signal changes again with the state; when there is no new data input waiting for calculation, that is, the in_valid signal is low, and only data is left in the cache, the data control module enters the clearing state CLRING or CLRING1, and the output signals ppen enable signal, in_ready signal and out_vaild signal are adjusted according to the clearing state.

5. The federated learning Krum algorithm hardware acceleration and optimization system according to claim 1, characterized in that: The data FIFO module is a FIFO buffer that supports multiple reads; The FIFO buffer is responsible for caching one client model gradient and completing the calculation of the client model score by repeated reading; including: Assume the number of clients is , want to calculate the client The score of the model gradient is cached in the FIFO buffer on the client side The model gradient , and Repeated reading to calculate With other clients The Euclidean distance of the corresponding model gradient; The number of readouts is controlled by a counter. After reading n-1 times, the gradient Cache until the algorithm runs to the end; In the data FIFO module, data caching and calculation are performed simultaneously; no need to wait for the client The model gradient All caching is completed, and Euclidean distance calculation with model gradients of other clients is allowed after the first gradient parameter is cached; the data FIFO module also includes a read enable signal rd_allow and a write enable quote wr_allow; when the write enable is high and the FIFO buffer is not full of data, the write enable quote wr_allow is high, and the data is written into the data FIFO module; when the read enable is high and the FIFO is not an empty signal, the data is read out.

6. The federated learning Krum algorithm hardware acceleration and optimization system according to claim 1, characterized in that: The data calculation module includes an accumulation module, a square root module and a minimum gradient calculation module; The accumulation module is used to calculate the addition and multiplication operations of the gradient Euclidean distance between two participants; The square root module is used to perform a square root operation on the square sum result output by the accumulation module, so as to obtain the true Euclidean distance between the participants; The minimum gradient calculation module is used to select the smallest nf-1 valid values ​​from the Euclidean distances calculated by multiple participants, accumulate the selected smallest nf-1 valid values, and calculate the effective distance sum as the basis for model updating.

7. The federated learning Krum algorithm hardware acceleration and optimization system according to claim 1, characterized in that: The accumulation module is used to calculate the addition and multiplication operations of the gradient Euclidean distance between two participants; including: The accumulation module realizes the start control of the calculation process and the synchronization management of the data flow through the ppen enable signal generated by the data control module; specifically, when the ppen enable signal is valid, first, the absolute difference between the two input data is generated, and then the square of the current difference is obtained through the square operation; then, the input data is accumulated point by point until the counter reaches the set number of neurons, and the accumulation result is output.

8. The federated learning Krum algorithm hardware acceleration and optimization system according to claim 1, characterized in that: Delay the tap operation via delay_ppen.

9. The federated learning Krum algorithm hardware acceleration and optimization system according to any one of claims 1 to 8, characterized in that: In the minimum gradient calculation module, first, the Euclidean distance data calculated by each participant is received and stored through registers; then, a parallel comparison mechanism is used to quickly compare the received distance data in the storage area to screen out the smallest nf-1 effective distances; finally, the selected smallest nf-1 effective distances are accumulated, the sum of the effective distances is calculated, and fed back to the front end.

10. Hardware acceleration and optimization method of federated learning Krum algorithm, characterized in that: include: Control data pipeline operation; That is: realize the pipeline control of data through finite state machine; Cache the data of one participant and read it out multiple times; The Krum algorithm is calculated by reading the parameters in the FIFO buffer and the parameters of another participant in the memory; including: first, calculating the addition operation and multiplication operation of the gradient Euclidean distance of the two participants; Afterwards, the square root of the output sum of squares is taken to obtain the true Euclidean distance between the participants. Finally, the smallest nf-1 valid values ​​are selected from the Euclidean distances calculated by multiple participants, the selected smallest nf-1 valid values ​​are added up, the effective distance sum is calculated, and fed back to the front end.

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