Continuous time self-return-to-zero comparator suitable for FinFet technology

Abstract

The invention aims to provide a continuous-time self-zeroing comparator suitable for a FinFet process. The self-zeroing comparator comprises at least one group of comparator circuits, the plurality of comparator circuits are connected in parallel; the comparator circuit is used for sampling an input voltage in a sampling period and comparing the input voltage with a reference voltage in an amplification period. Compared with a traditional static comparator, the static comparator can work under very low power supply voltage (0.4 V), is based on standard units such as a transmission gate and a phase inverter, is very small in area, is very good in portability in an advanced process, can work continuously by using pin-pong operation, and reduces the influence of imbalance on the precision of the comparator.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a continuous-time self-zeroing comparator suitable for FinFet technology. Background Art

[0002] The main function of the auto-zero comparator is to dynamically cancel the offset voltage and offset voltage drift, thereby reducing the impact of offset voltage and drift and improving the stability and accuracy of the circuit. Specifically, the auto-zero comparator introduces an automatic calibration mechanism in the circuit so that the offset voltage at the input is reduced to the mV level and the offset voltage drift is reduced to the nV / ℃ level. The basic working principle of the auto-zero comparator is to cancel the offset voltage and drift through dynamic calibration. When the input of the comparator is short-circuited to ground, a calibration coefficient is applied to the zeroing terminal to correct its own bias error. This calibration process is usually performed thousands of times per second. For example, Microchip's MCP6V01 auto-zero amplifier calibrates the main amplifier every 100 μs. The advantages of the auto-zero comparator include: Low offset voltage: Since the zeroing amplifier continuously eliminates its own offset voltage and applies a correction coefficient to the main amplifier, the offset voltage is much lower than that of traditional amplifiers. Low temperature and time drift: The auto-zero structure can effectively reduce temperature and time drift and improve the stability and accuracy of the circuit. Low noise: Low-frequency noise, especially 1 / f noise, can be effectively reduced through a dynamic calibration mechanism. Auto-zero comparators are widely used in circuits that require high precision and low noise, such as portable devices, medical equipment, industrial control, etc. Due to their excellent performance, auto-zero comparators can provide more reliable and stable signal processing capabilities in these applications.

[0003] Traditional static comparators have a certain hysteresis effect, which reduces the accuracy of the comparator. In advanced processes, the accuracy of traditional static comparators will be seriously reduced due to the increase in offset. Reducing the offset requires increasing the input tube area, which will not only lead to a significant increase in area overhead, but also increase in parasitic capacitance will reduce the slew rate, resulting in a reduction in comparator speed. In advanced processes, the gain and slew rate of the op amp will decrease due to the reduction in power supply voltage, resulting in a serious reduction in the accuracy and speed of the comparator. In advanced processes, traditional static comparators have poor portability under different processes. Summary of the invention

[0004] The purpose of the present invention is to provide a continuous time self-zeroing comparator suitable for FinFet process. Compared with the traditional static comparator, the self-zeroing comparator can operate at a very low power supply voltage (0.4V), and is based on standard units such as transmission gates, inverters, etc., with a very small area and good portability in advanced processes. In addition, when using ping-pong operation, the self-zeroing comparator can reduce the influence of offset on the accuracy of the comparator while working continuously.

[0005] A continuous time self-zeroing comparator suitable for FinFet process, comprising: at least one set of comparator circuits; A plurality of said comparator circuits are connected in parallel; The comparator circuit is used for sampling the input voltage in a sampling period and comparing the input voltage with a reference voltage in an amplification period.

[0006] Preferably, the comparator circuit comprises: a first transmission gate, a second transmission gate, a third transmission gate, a first capacitor, a first inverter, a second inverter, a first MOS transistor and a second MOS transistor; The first transmission gate is connected to the second transmission gate and the first capacitor; The first capacitor is connected to the third transmission gate and the input terminal of the first inverter; The third transmission gate is connected to the output end of the first inverter; The output terminal of the first inverter is connected to the input terminal of the second inverter; The second transmission gate is connected to the first capacitor; The drain of the first MOS tube is connected to the drain of the second MOS tube; The source of the second MOS tube is grounded.

[0007] Preferably, the inverters form an array arranged concentrically.

[0008] Preferably, the phases of the transmission gates in the comparator circuit are opposite, and there is a comparator circuit in an amplification cycle at any time.

[0009] A continuous time self-zeroing comparator control method suitable for FinFet process is applied to a continuous time self-zeroing comparator suitable for FinFet process, comprising: Get the phase condition of the transmission gate; Determining the operation cycle of the circuit according to the phase condition of the transmission gate; The input voltage is sampled according to the operation cycle of the circuit, and the input voltage is compared with a reference voltage.

[0010] Preferably, the operation cycle of the circuit is determined according to the phase condition of the transmission gate, including: When the phase of the transmission gate is low, the circuit is in the sampling period.

[0011] Preferably, the operation cycle of the circuit is determined according to the phase condition of the transmission gate, including: When the phase of the transmission gate is high, the circuit is in the amplification cycle.

[0012] Preferably, sampling the input voltage according to the operation cycle of the circuit and comparing the input voltage with a reference voltage comprises: When the circuit is in the sampling period, the phase of the transmission gate is low, and the voltage at the left end of the first capacitor is Equal to the input voltage of the second transmission gate ; The input and output of the first inverter are reversely connected, so that the voltage at the right end of the first capacitor is equal to the flip voltage of the second inverter. The flip voltage of the second inverter is expressed as: ; in and are the threshold voltages of the first MOS tube and the second MOS tube respectively. , are process parameters of the first MOS tube and the second MOS tube respectively; At this time, the voltage difference between the left and right ends of the first capacitor is expressed as: .

[0013] Preferably, sampling the input voltage according to the operation cycle of the circuit and comparing the input voltage with a reference voltage comprises: When the circuit is in the amplification cycle, the phase of the transmission gate is high, and the voltage at the left end of the first capacitor Equal to the input voltage V of the first transmission gate IN , since the voltage across the capacitor cannot change suddenly, ignoring the leakage current at the voltage V2 on the right end of the first capacitor, then: ; in, is the voltage difference between the left and right ends of the first capacitor; The input voltage of the first transmission gate is V IN and the input voltage of the second transmission gate The difference is added to the flip voltage of the second inverter by the first capacitor and used as the gate voltage of the inverter. If the input voltage of the first transmission gate is V IN Greater than the input voltage of the second transmission gate , then the inverter output is 1, if the input voltage of the first transmission gate VIN Less than the input voltage of the second transmission gate , the inverter output is 0.

[0014] An electronic device comprises: a chip, a processor and a memory, wherein the memory is used to store computer program code, the computer program code comprises computer instructions, and when the chip executes the computer instructions, the electronic device executes a continuous time self-zeroing comparator control method suitable for FinFet process.

[0015] The beneficial effects of the present invention are as follows: 1. Compared with the traditional static comparator, the self-zero comparator of the present invention can work at a very low power supply voltage (0.4V), has a wider application range, and can adapt to more circuit layouts; 2. The self-zero editor of the present invention is based on standard units, such as transmission gates, inverters, etc., and has a very small area, which can not only reduce the workload of design and layout, but also has good portability under different processes and can work at low voltage; 3. The present invention uses ping-pong operation, which can ensure that there is always one comparator in working state, allowing the circuit to work continuously while reducing the impact of offset on the accuracy of the comparator. 4. The present invention uses the principle that the voltage at both ends of the capacitor cannot change suddenly, samples the input voltage in the sampling period, and compares the input voltage with the reference voltage in the amplification period. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0018] Figure 1 It is a structural schematic diagram of a continuous-time self-zero comparator suitable for FinFet process of the present invention; Figure 2 It is a schematic diagram of the structure of a conventional static comparator of the present invention; Figure 3 is a control timing diagram of the self-zeroing comparator of the present invention; Figure 4 The figure is a schematic diagram of the hardware structure of an electronic device of the present invention. DETAILED DESCRIPTION

[0019] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0020] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0021] In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0022] Traditional static comparators have a certain hysteresis effect, which reduces the accuracy of the comparator. Figure 2 . In advanced processes, the accuracy of traditional static comparators will be seriously reduced due to increased offset. Reducing the offset requires increasing the input tube area, which will not only lead to a significant increase in area overhead, but also increase in parasitic capacitance will reduce the slew rate, resulting in a reduction in comparator speed. In advanced processes, the gain and slew rate of the op amp will decrease due to the reduction in power supply voltage, resulting in a serious reduction in the accuracy and speed of the comparator. In advanced processes, traditional static comparators have poor portability under different processes.

[0023] Compared with the traditional static comparator, the self-zero comparator of the present invention can work at a very low power supply voltage (0.4V), has a wider application range, and can adapt to more circuit layouts; the self-zero editor of the present invention is based on standard units, such as transmission gates, inverters, etc., and has a very small area, which can not only reduce the workload of design and layout, but also has good portability under different processes and can work at low voltage; the present invention uses ping-pong operation, which can make one comparator always in working state, so that the circuit can work continuously while reducing the impact of offset on the accuracy of the comparator. The present invention uses the principle that the voltage at both ends of the capacitor cannot change suddenly, samples the input voltage in the sampling period, and compares the input voltage with the reference voltage in the amplification period.

[0024] Example 1 A continuous-time self-zeroing comparator suitable for FinFet process, reference Figure 1 , comprising: at least one set of comparator circuits; A plurality of comparator circuits are connected in parallel; The ‌Auto-Zeroing Comparator circuit‌ is a circuit used to measure, sample and calibrate the offset voltage. It is mainly used to reduce the input offset voltage of the op amp, thereby improving the accuracy and stability of the circuit. The basic working principle of the auto-zeroing comparator circuit is to measure, sample and calibrate the offset voltage of the offset input transconductance through an auto-zeroing system. The system consists of input and output transconductance stages Gm1 and Gm2, switches S1-8, auto-zeroing transconductance stages Gmaz, and auto-zeroing capacitors Caz1-2. Switches S1-8 are driven by complementary clocks ΦAZ and ΦAZINV and operate at the auto-zeroing frequency fAZ. In the auto-zeroing phase ΦAZ, the differential input of Gm1 is shorted to the input common-mode voltage VCM, and its output is connected to the input of Gmaz to form an auto-zeroing feedback loop. Through this loop, the offset voltage Vos1 is calibrated by Gmaz and sampled by the auto-zeroing capacitors Caz1-2 during the sampling phase. Next, the op amp amplifies the input signal, and the offset voltage generated is theoretically zero because Vos1 is offset by Gmaz and the sampled voltage Vcorr of the previous auto-zero stage. The auto-zero comparator has high precision. Through the auto-zero system, the offset voltage can be effectively calibrated to improve the accuracy of the circuit. Stability reduces the input offset voltage and improves the stability and reliability of the circuit. Noise suppression, low-frequency noise components are sampled and offset together with the offset, and high-frequency noise components change rapidly after sampling and will not have a significant impact on the output.

[0025] The comparator circuit is used to sample the input voltage in a sampling period and compare the input voltage with a reference voltage in an amplification period.

[0026] The sampling period of the comparator circuit refers to the time interval between each on and off of the sampling switch. The sampling period is a key parameter of periodic sampling, which determines the frequency and accuracy of signal sampling. In the comparator circuit, the sampling period is usually achieved by setting the sampling time. The longer the sampling time, the higher the sampling accuracy, but it will also increase the response time of the system. In an embodiment of the present invention, the setting of the sampling period needs to consider multiple factors, including the characteristics of the signal, the response speed requirements of the system, and the processing power of the processor. Through reasonable settings and adjustments, accurate acquisition and processing of signals can be ensured to meet the needs of the system.

[0027] The amplification cycle of a comparator circuit usually refers to the time required from the input signal changing to the output signal stabilizing. In a comparator circuit, when the input signal changes, the comparator needs a certain amount of time to respond to this change and reach a stable state. The amplitude and rate of change of the input signal will affect the length of the amplification cycle. Because the comparator circuit is relatively stable during the amplification cycle, the input voltage and the reference voltage must be compared during the amplification cycle.

[0028] Preferably, the comparator circuit comprises: a first transmission gate, a second transmission gate, a third transmission gate, a first capacitor, a first inverter, a second inverter, a first MOS transistor and a second MOS transistor; The first transmission gate is connected to the second transmission gate and the first capacitor; The first capacitor is connected to the third transmission gate and the input terminal of the first inverter; ‌In the comparator circuit, the main functions of capacitors include: ‌Decoupling: Remove noise and interference signals in the comparator circuit and prevent them from returning to the power supply, thereby maintaining the stability and reliability of the circuit. Decoupling capacitors are usually connected in parallel to the power supply pins of the comparator to reduce the impact of power supply fluctuations on the circuit. ‌Filtering‌: Capacitors can smooth voltage signals and filter out unwanted frequency components, thereby improving the quality of the signal. In the comparator circuit, filtering can help eliminate noise and interference in the input signal and improve the signal-to-noise ratio. ‌Phase compensation‌: In some cases, capacitors can be used for phase compensation to improve the phase characteristics of the circuit. By adjusting the value and position of the capacitor, the phase response of the circuit can be changed to optimize the performance of the circuit. ‌Energy storage‌: Capacitors can store electrical energy and release it when needed, which is particularly useful for circuits that require fast response. In the comparator circuit, the energy storage function can help the circuit provide enough energy in a short time to meet the needs of rapid changes. ‌Stabilize the oscillation frequency‌: In the oscillator circuit, capacitors are used in conjunction with inductors to determine the oscillation frequency. By adjusting the value of the capacitor, the frequency of the oscillator can be controlled to ensure its stable operation. ‌

[0029] The third transmission gate is connected to the output terminal of the first inverter; The output terminal of the first inverter is connected to the input terminal of the second inverter; The second transmission gate is connected to the first capacitor; The drain of the first MOS tube is connected to the drain of the second MOS tube; The source of the second MOS tube is grounded.

[0030] The main functions of MOS tubes include the following aspects: Switching function: MOS tubes can be used as electronic switches. By controlling the gate voltage, they can quickly switch between the on and off states, thereby realizing the on-off control of the circuit. This feature allows MOS tubes to be used in comparator circuits to control the transmission path of signals. Amplification function: MOS tubes can be used as amplifiers to amplify the input signal and output it. Due to their high input impedance and low noise, MOS tubes have significant advantages in amplifying weak signals. In comparator circuits, this can be used to amplify input signals for further comparison and processing. Protection function: MOS tubes have high off impedance and can be used as protection elements in circuits. When a circuit fails or is overloaded, by controlling the switching state of the MOS tube, the current can be quickly cut off to protect other electronic devices from damage. This protection function is particularly important in the fields of power management, battery protection, etc. Signal modulation and demodulation: In the field of communications, MOS tubes can be used for signal modulation and demodulation. By changing the gate voltage of the MOS tube, the amplitude and frequency of the signal can be modulated to achieve signal transmission and processing. In comparator circuits, this can be used to process and transmit modulated signals.

[0031] Power supply control: In the power supply circuit, the MOS tube can be used as a control device for the switching power supply to realize the switching and voltage regulation functions of the power supply. By adjusting the on and off time of the MOS tube, the output voltage and current of the power supply can be controlled. In the comparator circuit, this can be used to accurately control the power supply state of the power supply.

[0032] The comparator circuit is mainly used to compare the magnitudes of two voltage signals and generate a corresponding output signal according to the comparison result. In an embodiment of the present invention, the comparator circuit samples the input voltage in a sampling period and compares the input voltage with a reference voltage in an amplification period.

[0033] In the embodiment of the present invention, the basic unit of the comparator circuit includes: Input stage: The input stage of the comparator is usually composed of two input ports IN+ and IN-, each of which is composed of two pairs of transistors. These transistors are used to receive analog signals and compare voltages. Output stage: The output stage is responsible for outputting the comparison result.

[0034] Preferably, the inverters form an array arranged concentrically.

[0035] The inverter can invert the input signal, that is, change the positive level of the input signal to a negative level, and the negative level to a positive level, while keeping the amplitude of the input signal unchanged. In the comparator circuit, the main functions of the inverter include: Signal inversion: Reverse the phase of the input signal by 180 degrees. Buffer link: In the signal processing circuit, the inverter can be used as a buffer link to help stabilize the signal and reduce interference. Waveform modulation: In signal sampling circuits, the inverter can be used to modulate the waveform, turning irregular waveforms into rectangular waves, etc.

[0036] In an embodiment of the present invention, the inverters can be arranged in a homocentric array to reduce the misalignment caused by the process. Homocentric arrangement means that all the particles in an object or system are arranged around a common center of mass.

[0037] Preferably, the phases of the transmission gates in the comparator circuits are opposite, and there is a comparator circuit in an amplification cycle at any time.

[0038] The present invention adopts pingpong operation, so that one of the two groups of comparators always works in the amplification state, so that continuous operation is possible.

[0039] Ping-Pong operation is a technology used to solve the problem of data processing rate mismatch between different modules, aiming to improve data throughput. It uses two or more buffers to perform read and write operations alternately, so that two modules can work at the same time, thereby improving the overall data processing efficiency. Ping-Pong operation connects two functional modules by using two or more buffers. When the read and write rates of the two modules do not match, for example, the write frequency of one module is higher than the read frequency of the other module, or the data sequence is inconsistent, the use of Ping-Pong structure allows the two modules to take turns to read and write different buffers, thereby avoiding one party being idle at a single moment. In this way, the two modules can perform read and write operations simultaneously in different time periods, thereby improving the overall data processing efficiency.

[0040] Example 2 A continuous time self-zeroing comparator control method suitable for FinFet process is applied to a continuous time self-zeroing comparator suitable for FinFet process, comprising: S100, obtaining the phase condition of the transmission gate; The phase of the transmission gate is mainly reflected in the phase relationship of its control signal. The transmission gate is usually composed of a PMOS and an NMOS tube in parallel, and their gates are connected to control levels with opposite phases. When the gate of the PMOS is connected to a high level, the PMOS tube is cut off; when the gate of the NMOS is connected to a high level, the NMOS tube is turned on. Therefore, when the gate of the PMOS is connected to a low level and the gate of the NMOS is connected to a high level, the input and output of the transmission gate are turned on to achieve level transmission.

[0041] S200, judging the operation cycle of the circuit according to the phase condition of the transmission gate; Sampling is the process of extracting samples from a continuously changing analog signal during the operating cycle of the circuit. The sample-and-hold circuit (S / H circuit) is a key component to achieve this process. The sample-and-hold circuit consists of switching devices, capacitors, and operational amplifiers. Amplification is the process of gain processing on the signal during the operating cycle of the circuit. Amplifiers play an important role in signal processing.

[0042] In the embodiment of the present invention, the operation cycle of the circuit includes: a sampling cycle and an amplification cycle.

[0043] S300, sampling the input voltage according to the operation cycle of the circuit, and comparing the input voltage with a reference voltage.

[0044] When the circuit is in the sampling period, the input voltage is sampled. Signal sampling is to discretize the continuous signal in time, that is, to take its instantaneous value point by point on the analog signal x(t) at a certain time interval △t. This discretization process allows the signal to be processed and analyzed in the digital system.

[0045] Preferably, S200, judging the operation cycle of the circuit according to the phase condition of the transmission gate includes: When the phase of the transmission gate is low, the circuit is in the sampling period.

[0046] In the embodiment of the present invention, the cycle of the circuit is determined according to the phase of the transmission gate. In the present invention, the phases of the three transmission gates of the same comparator circuit are consistent, while in another comparator circuit, the phases of the three transmission gates are consistent and opposite to the phases of the transmission gates in the first comparator circuit. Therefore, the sampling cycle described in this embodiment is the sampling cycle of a comparator circuit. When the phases of the three transmission gates are all low, it can be determined that the comparator circuit is in the sampling cycle at this time.

[0047] Preferably, S200, judging the operation cycle of the circuit according to the phase condition of the transmission gate includes: When the phase of the transmission gate is high, the circuit is in the amplification cycle.

[0048] When the phases of the three transmission gates are all high, it can be determined that the comparator circuit is in the amplification cycle. Since the phases of the transmission gates in each comparator circuit are opposite, there is always a comparator circuit in the amplification cycle to perform comparison work.

[0049] Preferably, S300, reference Figure 3 , sampling the input voltage according to the circuit's operating cycle and comparing the input voltage with the reference voltage include: When the circuit is in the sampling period, the phase of the transmission gate is low, and the voltage at the left end of the first capacitor is Equal to the input voltage of the second transmission gate ; The input and output of the first inverter are reversely connected, so that the voltage at the right end of the first capacitor is equal to the flip voltage of the second inverter. The flip voltage of the second inverter is expressed as: ; in and are the threshold voltages of the first MOS tube and the second MOS tube respectively. , are process parameters of the first MOS tube and the second MOS tube respectively; During the sampling period, Φ INV,A is low, at this time the voltage V1 at the left end of CAZ1 = VREF, and the input and output ends of the inverter INV1 are reversed, so that the voltage V2 at the right end of CAZ1 = VM, where VM is the inverter flip voltage.

[0050] At this time, the voltage difference between the left and right ends of the first capacitor is expressed as: .

[0051] in and They are the threshold voltages of PMOS and NMOS respectively. , These are the process parameters of PMOS and NMOS respectively.

[0052] Preferably, S300, sampling the input voltage according to the operation cycle of the circuit, and comparing the input voltage with the reference voltage includes: When the circuit is in the amplification cycle, the phase of the transmission gate is high, and the voltage at the left end of the first capacitor Equal to the input voltage V of the first transmission gate IN , since the voltage across the capacitor cannot change suddenly, ignoring the leakage current at the voltage V2 on the right end of the first capacitor, then: ; in, is the voltage difference between the left and right ends of the first capacitor; Φ INV,A is high, and the amplification cycle begins, V1=VIN. Since the voltage across the capacitor cannot change suddenly, if it is assumed that the leakage current at V2 can be ignored, the above formula exists.

[0053] The input voltage of the first transmission gate is V IN and the input voltage of the second transmission gate The difference is added to the flip voltage of the second inverter by the first capacitor and used as the gate voltage of the inverter. If the input voltage of the first transmission gate is V IN Greater than the input voltage of the second transmission gate , then the inverter output is 1, if the input voltage of the first transmission gate V IN Less than the input voltage of the second transmission gate , the inverter output is 0.

[0054] The present invention arranges different comparator circuits, in which the phases of the transmission gates are opposite, so that at any time one of the two groups of comparators is always in an amplification cycle, thereby achieving continuous operation.

[0055] Example 3 An electronic device includes: a chip, a processor and a memory, the memory is used to store computer program code, the computer program code includes computer instructions, and when the chip executes the computer instructions, the electronic device executes a continuous time self-zeroing comparator control method suitable for FinFet process.

[0056] refer to Figure 4 , the electronic device 2 includes a processor 21, a memory 22, an input device 23, and an output device 24. The processor 21, the memory 22, the input device 23, and the output device 24 are coupled via a connector, and the connector includes various interfaces, transmission lines, or buses, etc., which are not limited in the embodiments of the present invention. It should be understood that in various embodiments of the present invention, coupling refers to mutual connection in a specific manner, including direct connection or indirect connection through other devices, for example, through various interfaces, transmission lines, buses, etc.

[0057] The processor 21 may be one or more graphics processing units (GPUs). When the processor 21 is a GPU, the GPU may be a single-core GPU or a multi-core GPU. Optionally, the processor 21 may be a processor group consisting of multiple GPUs, and the multiple processors are coupled to each other via one or more buses. Optionally, the processor may also be other types of processors, etc., which are not limited in the embodiments of the present invention.

[0058] The memory 22 can be used to store computer program instructions and various computer program codes including program codes for executing the scheme of the present invention. Optionally, the memory includes but is not limited to random access memory (RAM), read-only memory (ROM), erasable programmable read only memory (EPROM), or portable read only memory (CD-ROM), which is used for related instructions and data.

[0059] The input device 23 is used to input data and / or signals, and the output device 24 is used to output data and / or signals. The output device 24 and the input device 23 may be independent devices or an integrated device.

[0060] Compared with the traditional static comparator, the self-zero comparator of the present invention can work at a very low power supply voltage (0.4V), has a wider application range, and can adapt to more circuit layouts; the self-zero editor of the present invention is based on standard units, such as transmission gates, inverters, etc., and has a very small area, which can not only reduce the workload of design and layout, but also has good portability under different processes and can work at low voltage; the present invention uses ping-pong operation, which can make one comparator always in working state, so that the circuit can work continuously while reducing the impact of offset on the accuracy of the comparator. The present invention uses the principle that the voltage at both ends of the capacitor cannot change suddenly, samples the input voltage in the sampling period, and compares the input voltage with the reference voltage in the amplification period.

[0061] The foregoing is merely a specific embodiment of the present invention, which enables those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A continuous time self-zeroing comparator suitable for FinFet process, characterized in that: include: at least one set of comparator circuits; A plurality of said comparator circuits are connected in parallel; The comparator circuit is used for sampling the input voltage in a sampling period and comparing the input voltage with a reference voltage in an amplification period.

2. A continuous time self-zero comparator suitable for FinFet process according to claim 1, characterized in that: The comparator circuit comprises: a first transmission gate, a second transmission gate, a third transmission gate, a first capacitor, a first inverter, a second inverter, a first MOS transistor and a second MOS transistor; The first transmission gate is connected to the second transmission gate and the first capacitor; The first capacitor is connected to the third transmission gate and the input terminal of the first inverter; The third transmission gate is connected to the output end of the first inverter; The output terminal of the first inverter is connected to the input terminal of the second inverter; The second transmission gate is connected to the first capacitor; The drain of the first MOS tube is connected to the drain of the second MOS tube; The source of the second MOS tube is grounded.

3. A continuous time self-zero comparator suitable for FinFet process according to claim 2, characterized in that: The inverters form a homocentric array.

4. The continuous time self-zero comparator suitable for FinFet process according to claim 1, characterized in that: The phases of the transmission gates in the comparator circuit are opposite, and there is a comparator circuit in an amplification cycle at any time.

5. A control method for a continuous-time self-zeroing comparator suitable for FinFet process, applied to a continuous-time self-zeroing comparator suitable for FinFet process as claimed in any one of claims 1 to 4, characterized in that: include: Get the phase condition of the transmission gate; Determining the operation cycle of the circuit according to the phase condition of the transmission gate; The input voltage is sampled according to the operation cycle of the circuit, and the input voltage is compared with a reference voltage.

6. The continuous time self-zeroing comparator control method suitable for FinFet process according to claim 5, characterized in that: The operation cycle of the circuit determined according to the phase condition of the transmission gate includes: When the phase of the transmission gate is low, the circuit is in the sampling period.

7. The continuous time self-zeroing comparator control method suitable for FinFet process according to claim 5, characterized in that: The operation cycle of the circuit determined according to the phase condition of the transmission gate includes: When the phase of the transmission gate is high, the circuit is in the amplification cycle.

8. The continuous time self-zeroing comparator control method suitable for FinFet process according to claim 6, characterized in that: The step of sampling the input voltage according to the operation cycle of the circuit and comparing the input voltage with a reference voltage comprises: When the circuit is in the sampling period, the phase of the transmission gate is low, and the voltage at the left end of the first capacitor is Equal to the input voltage of the second transmission gate ; The input and output of the first inverter are reversely connected, so that the voltage at the right end of the first capacitor is equal to the flip voltage of the second inverter. The flip voltage of the second inverter is expressed as: ； in and are the threshold voltages of the first MOS tube and the second MOS tube respectively. , are process parameters of the first MOS tube and the second MOS tube respectively; At this time, the voltage difference between the left and right ends of the first capacitor is expressed as: 。 9. The continuous time self-zeroing comparator control method suitable for FinFet process according to claim 7, characterized in that: The step of sampling the input voltage according to the operation cycle of the circuit and comparing the input voltage with a reference voltage comprises: When the circuit is in the amplification cycle, the phase of the transmission gate is high, and the voltage at the left end of the first capacitor Equal to the input voltage V of the first transmission gate IN , since the voltage across the capacitor cannot change suddenly, ignoring the leakage current at the voltage V2 on the right end of the first capacitor, then: ； in, is the voltage difference between the left and right ends of the first capacitor; The input voltage of the first transmission gate is V IN and the input voltage of the second transmission gate The difference is added to the flip voltage of the second inverter by the first capacitor and used as the gate voltage of the inverter. If the input voltage of the first transmission gate is V IN Greater than the input voltage of the second transmission gate , then the inverter output is 1, if the input voltage of the first transmission gate V IN Less than the input voltage of the second transmission gate , the inverter output is 0.

10. An electronic device, characterized in that: include: A chip, a processor and a memory, wherein the memory is used to store computer program codes, wherein the computer program codes include computer instructions. When the chip executes the computer instructions, the electronic device executes a continuous-time self-zeroing comparator control method suitable for FinFet process as described in any one of claims 5 to 9.

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