Slave chip and slave chip address detection updating method

Abstract

The invention provides a slave chip, electronic equipment, a slave chip address detection and updating method and a computer readable storage medium, which can detect and update the address of the slave chip in real time, thereby improving the efficiency, reliability and safety of accessing the chip. The slave chip comprises a digital module, N analog modules and N detection ends; the ith simulation module in the N simulation modules is connected with the ith detection end in the N detection ends and the Mi reference ends, and the ith simulation module is used for detecting the Mi reference ends when the slave chip receives an instruction from the master chip. An ith intermediate address is generated according to logical operation between the input signal of the ith detection end and the level signals of the Mi reference ends and sent to the digital module, N, Mi and i are all positive integers, and i is larger than or equal to 1 and smaller than or equal to N; the N intermediate addresses are used for the digital module to generate a first address of the slave chip, and the first address is different from a second address carried in the instruction.

Description

Technical Field

[0001] The embodiments of the present application belong to the field of chip technology, and in particular, relate to a slave chip, an electronic device, a slave chip address detection and update method, and a computer-readable storage medium. Background Art

[0002] With the continuous development and innovation of portable electronic products, the functions of products are increasing, and the internal circuits are becoming more and more complex. The system often needs more than one power supply chip, detection chip, and protection chip, but there is generally only one main control unit for multiple similar chips, so one-to-many control is often performed through a protocol bus. The power supply chip, detection chip, and protection chip need to have the function of customizing the slave address to ensure that the main control unit can control the same type of chips separately.

[0003] From the chip design perspective, similar chips generally belong to the same batch of designs:

[0004] 1. Projects can be differentiated and managed based on the address. After the project differentiation is done, it is relatively intuitive and can be directly distinguished by the project name. However, as the demand grows, more and more projects will be created, the management cost will also increase, and the chip address will be fixed;

[0005] 2. New pins can be introduced, and then the required slave address can be defined for the chip by configuring the high and low levels of the pins. This can simplify project management, but will cause chip design costs and solidify the chip address;

[0006] 3. In addition, trimming the chip into different versions by burning efuse is also one of the mainstream methods, but it will also increase certain project management costs and solidify the chip address;

[0007] 4. There is also a relatively rare method, which uses software to program the chip-specific register address to define the chip's slave address. However, this method requires configuration one by one when the system is powered on, which increases software costs and power-on time, and requires the main chip to effectively identify when sending instructions. The chip address is variable, but the operation is cumbersome and error-prone, inefficient and unreliable.

[0008] Therefore, how to detect and update the slave chip address in real time, which can make the chip address variable and simplify the software operation process, has become an urgent problem to be solved.

[0009] In addition, the instruction address of the chip may be leaked, posing certain security risks. Summary of the invention

[0010] The embodiments of the present application provide a slave chip, an electronic device, a slave chip address detection and update method, and a computer-readable storage medium, which can detect and update the slave chip address in real time, thereby improving the efficiency, reliability, and security of accessing the slave chip.

[0011] In order to achieve the above purpose, the embodiment of the present application adopts the following technical solution:

[0012] In a first aspect, a slave chip is provided, the chip comprising a digital module, N analog modules and N detection terminals;

[0013] The i-th analog module among the N analog modules is respectively connected to the i-th detection terminal among the N detection terminals and the M i The i-th analog module is used to connect the M reference terminals respectively according to the input signal of the i-th detection terminal when the slave chip receives the instruction from the master chip. i The logic operation between the level signals of the reference terminals generates the i-th intermediate address and sends it to the digital module. i , i are both positive integers, 1≤i≤N;

[0014] The N intermediate addresses are used by the digital module to generate a first address of the slave chip, where the first address is different from the second address carried in the instruction.

[0015] In a possible design solution, the logical operation may be an XENOR operation.

[0016] Optionally, the i-th detection end and M i One of the reference ends is connected, and the i-th intermediate address is M i One-hot encoding;

[0017] The total number of combinations of the N intermediate addresses corresponds to the number of types of values ​​of the first address.

[0018] Optionally, the total number of combinations of the N intermediate addresses and the number of types of values ​​of the first address satisfy:

[0019]

[0020] Optionally, D is the total number of combinations of the N intermediate addresses and the number of types of values ​​of the first address.

[0021] Optionally, if the number of reference terminals that perform logical operations with each of the N detection terminals is M, the total number of combinations D of the N intermediate addresses and the number of types D of values ​​of the first address satisfy:

[0022] D=M N .

[0023] Optionally, the D values ​​of the first address are The value of the preset bit, the first address is The values ​​of the other bits except the preset bits are the same as the second address except The values ​​of the other bits except the preset bits are the same. This is a round-up operation.

[0024] in, The preset bits may be the lower 4 bits of the first address and the second address.

[0025] In one possible design, M i The reference terminals include one or more of the following: a clock input terminal, a data input terminal, a power supply terminal, and a ground terminal.

[0026] Optionally, when the input signal at the clock input terminal is at a high level and the input signal at the data input terminal is at a falling edge, the digital module sends a detection enable signal to N analog modules, and the detection enable signal is used for the i-th analog module to generate the i-th intermediate address according to the logical operation between the input signal at the i-th detection terminal and the input signal at the clock input terminal, the input signal at the data input terminal, the power supply terminal and the ground terminal.

[0027] In a second aspect, an electronic device is provided, the electronic device comprising a master chip and a slave chip as described in any implementation manner in the first aspect.

[0028] In a third aspect, a method for detecting and updating a slave chip address is provided, wherein the slave chip includes N detection terminals, wherein the i-th detection terminal among the N detection terminals is connected to the M i A reference terminal connection;

[0029] The method includes:

[0030] Receive instructions from the main chip;

[0031] According to the input signal of the i-th detection end and M i The logic operation between the level signals of the reference terminals generates the i-th intermediate address among the N intermediate addresses, N, M i , i are both positive integers, 1≤i≤N;

[0032] A first address of the slave chip is generated according to the N intermediate addresses, where the first address is different from a second address carried in the instruction.

[0033] In a possible design solution, the logical operation is an XEN_OR operation.

[0034] Optionally, the i-th detection end and M i One of the reference ends is connected, and the i-th intermediate address is M i One-hot encoding;

[0035] The total number of combinations of the N intermediate addresses corresponds to the number of types of values ​​of the first address.

[0036] Optionally, the total number of combinations of the N intermediate addresses and the number of types of values ​​of the first address satisfy:

[0037]

[0038] Wherein, D is the total number of combinations of the N intermediate addresses and the number of types of values ​​of the first address.

[0039] Optionally, if the number of reference terminals that perform logical operations with each of the N detection terminals is M, the total number of combinations D of the N intermediate addresses and the number of types D of values ​​of the first address satisfy:

[0040] D=M N .

[0041] Optionally, the D values ​​of the first address are The value of the preset bit, the first address is The values ​​of the other bits except the preset bits are the same as the second address except The values ​​of the other bits except the preset bits are the same. This is a round-up operation.

[0042] Optionally, The preset bits are the lower 4 bits of the first address and the second address.

[0043] Optionally, M i The reference terminals include one or more of the following: a clock input terminal, a data input terminal, a power supply terminal, and a ground terminal.

[0044] Optionally, according to the input signal of the i-th detection end and M i Before performing a logical operation between level signals of the reference terminals to generate an i-th intermediate address among the N intermediate addresses, the method further comprises:

[0045] When the input signal of the clock input terminal is at a high level and the input signal of the data input terminal is at a falling edge, the detection enable signal is enabled. The detection enable signal is used to generate the i-th intermediate address according to the logical operation between the input signal of the i-th detection terminal and the input signal of the clock input terminal, the input signal of the data input terminal, the power supply terminal and the ground terminal.

[0046] In a fourth aspect, a computer-readable storage medium is provided, storing a program or instruction. When a computer reads and executes the program or instruction, the computer executes the chip address detection update method as described in any implementation method of the third aspect.

[0047] Based on the slave chip, electronic device, slave chip address detection and update method and computer-readable storage medium provided by the embodiments of the present application, when receiving an instruction from the master chip, the slave chip can respectively communicate with the M according to the input signal of the i-th detection terminal. i The logic operation between the level signals of the reference terminals generates the ith intermediate address among the N intermediate addresses, and the first address of the slave chip is generated based on the N intermediate addresses, and the first address is different from the second address carried in the instruction. In this way, the real-time detection and update of the slave chip address can be realized, the software operation process can be simplified, and the efficiency and reliability of accessing the slave chip can be improved. In addition, the actual address (first address) of the slave chip can be different from the instruction address (second address). Even if the instruction address is leaked, there is no risk of leakage, thereby improving security. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. Some specific embodiments of the present application will be described in detail in an illustrative and non-restrictive manner with reference to the drawings. The same reference numerals in the drawings indicate the same or similar components or parts. It should be understood by those skilled in the art that these drawings are not necessarily drawn to scale. In the drawings:

[0049] Figure 1 It is the I2C principle waveform diagram in the prior art;

[0050] Figure 2 A schematic diagram of the structure of a slave chip provided in an embodiment of the present application;

[0051] Figure 3 A waveform diagram of generating a middle address from a chip provided in an embodiment of the present application;

[0052] Figure 4 A flowchart of a chip address detection update method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0053] In order to enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only embodiments of a part of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work should fall within the scope of protection of the present application.

[0054] The term "and / or" in this article is merely a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0055] The terms "first" and "second" and the like in the specification and drawings of this application are used to distinguish different objects, or to distinguish different processing of the same object, rather than to describe a specific order of objects.

[0056] It should be noted that, in the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0057] First, the prior art related to the embodiments of the present application is described.

[0058] For example, Figure 1 It is the I2C principle waveform diagram in the prior art. The I2C bus can be used for the master chip to access one or more slave chips. Among them, the master chip can also be called a master control unit, a control unit, etc., and can be a chip with a master control function, such as a main processor in an electronic device. The slave chip can be other chips arranged in the same electronic device as the master chip, such as a memory, an application specific integrated circuit, etc. The electronic device can be a computer, a mobile phone, a pad, a server, a network device, etc., and the embodiments of the present application are not limited.

[0059] like Figure 1 As shown, when the slave chip detects that the serial clock (Serial Clock, SCL) signal scl_in of the I2C bus is at a high level and the serial data (Serial Data, SDA) signal sda_in of the I2C bus is at a falling edge, the slave chip starts the instruction reception work and begins to receive the slave chip address carried on the I2C bus (hereinafter referred to as the instruction address) at the rising edge of the next 8 consecutive clock cycles, and receives 1 bit (bit) address in each clock cycle (high level is binary number 1, low level is binary number 0). According to the address transmission method agreed upon by the master and slave chips, the 8-bit address (addr[7:0]) can be received and identified in the order of high first and low later, that is, the value of the 8-bit address detected in 8 consecutive clock cycles is usually expressed in hexadecimal, which can be 0x00~0xFF.

[0060] Generally, the address of the slave chip will not be "0x00" or "0xFF". This is because the serial data line SDA may be normally low or normally high under some abnormal circumstances. To avoid misidentification, when the master chip sends the SDA signal, all connected slave chips will receive it. When and only when the 8-bit address sent by the master chip is equal to the slave address of one of the slave chips, the slave chip will feedback an ACKnowledge (ACK) signal, and then receive the subsequent transmission commands of SDA and respond.

[0061] If the above instruction is a read instruction, the slave chip returns the read data (data, read data) to the master chip; if the above instruction is a write instruction, the slave chip can continue to receive data (write data) from the master chip and store the write data in the storage space corresponding to the instruction address.

[0062] It should be noted that the transmission mode of address and data can be high first and low later (transmitted sequentially from high to low), or low first and high later (transmitted sequentially from low to high), and the number of address bits can also be other values, such as 16 bits, 32 bits, etc., and the bus used for communication between master and slave chips can also be other types of serial buses, such as a serial peripheral interface (Serial Peripheral interface, SPI) bus, etc., which is not limited in the embodiments of the present application.

[0063] It can be seen that in the prior art, the address of a slave chip is usually fixed, and the slave chip will respond only when the instruction address is the same as its own address. Moreover, if the instruction address is stolen, there is a certain risk of leakage.

[0064] In order to solve the above problems, an embodiment of the present application provides a slave chip, which is described in detail below.

[0065] For example, Figure 2 A schematic diagram of the structure of a slave chip provided in an embodiment of the present application. Figure 2 As shown, the slave chip includes a digital module, N analog modules (analog module 1 to analog module N) and N detection terminals (a1_in to aN_in);

[0066] The i-th analog module among the N analog modules is respectively connected to the i-th detection terminal among the N detection terminals and the M i The i-th analog module is used to connect the M reference terminals respectively according to the input signal of the i-th detection terminal when the slave chip receives the instruction from the master chip. i The logic operation between the level signals of the reference terminals generates the i-th intermediate address and sends it to the digital module. i, i are both positive integers, 1≤i≤N;

[0067] The N intermediate addresses are used by the digital module to generate a first address from the chip, and the first address is different from the second address carried in the instruction to avoid address leakage, thereby improving security.

[0068] In a possible design solution, the logical operation may be an XENOR operation.

[0069] Optionally, the i-th detection end and M i One of the reference ends is connected, and the i-th intermediate address is M i One-hot encoding;

[0070] The total number of combinations of the N intermediate addresses corresponds to the number of types of values ​​of the first address.

[0071] Optionally, the total number of combinations of the N intermediate addresses and the number of types of values ​​of the first address satisfy:

[0072]

[0073] Optionally, D is the total number of combinations of the N intermediate addresses and the number of types of values ​​of the first address.

[0074] Optionally, if the number of reference terminals that perform logical operations with each of the N detection terminals is M, the total number of combinations D of the N intermediate addresses and the number of types D of values ​​of the first address satisfy:

[0075] D=M N .

[0076] Optionally, the D values ​​of the first address are The value of the preset bit, the first address is The values ​​of the other bits except the preset bits are the same as the second address except The values ​​of the other bits except the preset bits are the same. This is a round-up operation.

[0077] in, The preset bits may be the lower 4 bits of the first address and the second address.

[0078] For example, assuming there are 3 detection ends, the first detection end corresponds to 8 reference ends, the second detection end corresponds to 2 reference ends, and the third detection end corresponds to 4 reference ends. The first intermediate address is an 8-bit unique-hot code with 8 combinations, the second intermediate address is a 2-bit unique-hot code with 2 combinations, and the third intermediate address is a 4-bit unique-hot code with 4 combinations. The 3 intermediate addresses have a total of 8*2*4=64 combinations, which can correspond to a 6-bit address. The 6-bit address can be used to replace the 6 preset bits in the instruction address (second address), such as the lower 6 bits, to generate the actual access address (first address) from the chip. Even if the second address is leaked, the first address will not be leaked, thereby improving security.

[0079] In one possible design, M i The reference terminals include one or more of the following: a clock input terminal scl_in, a data input terminal sda_in, a power terminal vs and a ground terminal gnd.

[0080] When the input signal of the clock input terminal scl_in is at a high level and the input signal of the data input terminal sda_in is at a falling edge, the digital module sends a detection enable signal da_en_addr_det to N analog modules. The detection enable signal is used by the i-th analog module to generate the i-th intermediate address according to the logic operation between the input signal of the i-th detection terminal ai_in and the input signal of the clock input terminal scl_in, the input signal of the data input terminal sda_in, the power supply terminal vs and the ground terminal gnd.

[0081] The following is an explanation with reference to examples. For example, Figure 3 A waveform diagram for generating an intermediate address from a chip provided in an embodiment of the present application.

[0082] Combination Figure 2 ,like Figure 3As shown, scl_in is the input signal of the clock input terminal, sda_in is the input signal of the data input terminal, da_en_addr_det is when the input signal of the clock input terminal scl_in is high level and the input signal of the data input terminal sda_in is a falling edge, the digital module generates a detection enable signal da_en_addr_det and sends it to N analog modules, the i-th (1≤i≤N) analog module obtains a 4-bit intermediate address (the i-th intermediate address) according to the exclusive OR operation between the i-th detection terminal ai_in and the four reference terminals (the input signal of the clock input terminal scl_in, the input signal of the data input terminal sda_in, the power supply terminal vs and the ground terminal gnd, Mi=4). Assuming that the intermediate address is from high to low, it is: the exclusive OR result of the input signal of the ground terminal gnd and the i-th detection terminal ai_in, the exclusive OR result of the input signal of the power terminal vs and the i-th detection terminal ai_in, the exclusive OR result of the input signal of the clock input terminal scl_in and the i-th detection terminal ai_in, and the exclusive OR result of the input signal of the data input terminal sda_in and the i-th detection terminal ai_in, which can be abbreviated as [ai_gnd, ai_vs, _ai_scl, ai_sda], where ai_gnd = gnd⊙ai_in;

[0083] ai_vs=vs⊙ai_in;

[0084] ai_scl=scl_in⊙ai_in;

[0085] ai_sda=sda_in⊙ai_in;

[0086] Among them, ⊙ is an XOR operation. Since the i-th detection terminal ai_in is connected to one of the four reference terminals and is configurable, the i-th intermediate address generated by the i-th analog module is a 4-bit one-hot code. For example, the i-th detection terminal ai_in is connected to the clock input terminal scl_in, and is not connected to the ground terminal gnd, the power supply terminal vs, and the data input terminal sda_in, then the i-th intermediate address generated by the i-th analog module is a 4-bit binary number 0010. It is easy to understand that if the i-th detection terminal ai_in is connected to the data input terminal sda_in, and is not connected to the ground terminal gnd, the power supply terminal vs, and the clock input terminal scl_in, then the i-th intermediate address generated by the i-th analog module is a 4-bit binary number 0001. Similarly, the i-th intermediate address generated by the i-th analog module can also be a 4-bit binary number 1000 (ai_in is only connected to the ground terminal gnd) and 0100 (ai_in is only connected to the power terminal vs), with a total of 4 combinations of values ​​(4-bit one-hot code).

[0087] by Figure 3For example, the first detection terminal a1_in is connected to the clock input terminal scl_in, and is not connected to the ground terminal gnd, the power supply terminal vs and the data input terminal sda_in. The first intermediate address generated by the analog module 1 is a 4-bit binary number 0010, that is, a1_gnd=0, a1_vs=0, a1_scl=1, a1_sda=0.

[0088] Please continue to refer to Figure 3 , the second detection terminal a2_in is connected to the data input terminal scl_in, and is not connected to the ground terminal gnd, the power supply terminal vs and the clock input terminal scl_in, then the second intermediate address generated by the second analog module is a 4-bit binary number 0001, that is, a2_gnd=0, a2_vs=0, a2_scl=0, a2_sda=1.

[0089] It can be seen that if each detection end corresponds to 4 reference ends (Mi=4), each detection end can generate a 4-bit intermediate address after performing XOR operation with the 4 reference ends, and each intermediate address has 4 combinations (4-bit unique hot code). All value combinations of the N intermediate addresses corresponding to the N detection ends are used to replace the corresponding number of addresses in the instruction address to generate an actual access address (first address) different from the instruction address (second address) to avoid address leakage, thereby improving security.

[0090] Table 2 is a table of correspondence between an intermediate address and a first address provided by an embodiment of the present application. As shown in Table 1, assuming that there are 2 analog modules and 2 detection terminals (a1_in, a2_in), that is, N=2, and each detection terminal corresponds to 4 reference terminals (ground terminal gnd, power terminal vs, clock input terminal scl_in, data input terminal sda_in), that is, Mi=M=4, wherein the first detection terminal a1_in and the four reference terminals perform the same or operation to generate the first intermediate address, and the bits of the second detection terminal a2_in and the four reference terminals perform the same or operation to generate the second intermediate address, and the bits of the second detection terminal a2_in and the four reference terminals perform the same or operation to generate the second intermediate address, and the bits of the first intermediate address and the second intermediate address have a total of 16=4*4 combinations, which can correspond to all values ​​of a 4-bit address. Therefore, the preset bits in the instruction address, such as the lower 4 bits, can be replaced with the 4-bit address corresponding to the two intermediate addresses to generate the actual access address (first address) of the slave chip.

[0091] For example, assuming that an 8-bit instruction address is 0x40, if the detection terminal a1_in is connected to the clock input terminal scl_in, and is not connected to the ground terminal gnd, the power terminal vs, and the data input terminal sda_in, and the detection terminal a2_in is connected to the data input terminal sda_in, and is not connected to the ground terminal gnd, the power terminal vs, and the clock input terminal scl_in, then Figure 3 As shown, the intermediate address corresponding to the detection terminal a1_in is the binary number 0010, and the intermediate address corresponding to the detection terminal a2_in is the binary number 0001. As shown in Table 1, the low 4-bit address corresponding to these two intermediate addresses is 0x4. The low 4-bit address 0x0 in the instruction address 0x40 can be replaced with the low 4-bit address 0x4, and the actual access address 0x44 (i.e., the first address, marked in bold in Table 1) of the slave chip is generated.

[0092] Table 1

[0093]

[0094]

[0095] It should be noted that Table 1 only shows one address encoding scheme, and other address encoding schemes may also be used. For example, the lower 4-bit address may also use a cyclic code, and each intermediate address may also be sorted from high to low in other orders. For example, the second intermediate address may be a2_scl, a2_sda, a2_gnd, a2_vs, or a2_gnd, a2_sda, a2_vs, a2_scl, etc. from high to low, and the embodiments of the present application are not limited thereto.

[0096] In addition, the number of detection terminals shown in Table 1 is 2, and it can also be other numbers, such as 2, 8, etc. The reference terminals shown in Table 1 are the clock input terminal scl_in, the data input terminal sda_in, the power supply terminal vs and the ground terminal gnd. It can also be other numbers and / or different combinations of reference terminals, which are not limited in the embodiments of the present application.

[0097] An embodiment of the present application provides an electronic device, which includes a master chip and a slave chip as described in any of the implementation methods above.

[0098] For example, Figure 4 A flowchart of a method for detecting and updating a slave chip address is provided for an embodiment of the present application. The method can be applied to the slave chip described in any of the above implementations. The slave chip includes N detection terminals, wherein the i-th detection terminal of the N detection terminals is connected to the M i A reference terminal connection;

[0099] like Figure 4 As shown, the method includes:

[0100] S501, the slave chip receives an instruction from the master chip;

[0101] S502, the slave chip communicates with M i The logic operation between the level signals of the reference terminals generates the i-th intermediate address among the N intermediate addresses, N, M i , i are both positive integers, 1≤i≤N;

[0102] S503, generating a first address of the slave chip according to the N intermediate addresses, where the first address is different from the second address carried in the instruction.

[0103] In a possible design solution, the logical operation is an XEN_OR operation.

[0104] Optionally, the i-th detection end and M i One of the reference ends is connected, and the i-th intermediate address is M i One-hot encoding;

[0105] The total number of combinations of the N intermediate addresses corresponds to the number of types of values ​​of the first address.

[0106] Optionally, the total number of combinations of the N intermediate addresses and the number of types of values ​​of the first address satisfy:

[0107]

[0108] Wherein, D is the total number of combinations of the N intermediate addresses and the number of types of values ​​of the first address.

[0109] Optionally, if the number of reference terminals that perform logical operations with each of the N detection terminals is M, the total number of combinations D of the N intermediate addresses and the number of types D of values ​​of the first address satisfy:

[0110] D=M N .

[0111] Optionally, the D values ​​of the first address are The value of the preset bit, the first address is The values ​​of the other bits except the preset bits are the same as the second address except The values ​​of the other bits except the preset bits are the same. This is a round-up operation.

[0112] Optionally, The preset bits are the lower 4 bits of the first address and the second address.

[0113] Optionally, M iThe reference terminals include one or more of the following: a clock input terminal, a data input terminal, a power supply terminal, and a ground terminal.

[0114] Optionally, according to the input signal of the i-th detection end and M i Before performing a logical operation between level signals of the reference terminals to generate an i-th intermediate address among the N intermediate addresses, the method further comprises:

[0115] When the input signal of the clock input terminal is at a high level and the input signal of the data input terminal is at a falling edge, the detection enable signal is enabled. The detection enable signal is used to generate the i-th intermediate address according to the logical operation between the input signal of the i-th detection terminal and the input signal of the clock input terminal, the input signal of the data input terminal, the power supply terminal and the ground terminal.

[0116] An embodiment of the present application provides a computer-readable storage medium storing a program or instruction. When a computer reads and executes the program or instruction, the computer executes the chip address detection update method as described in any implementation method in the third aspect.

[0117] Based on the slave chip, electronic device, slave chip address detection and update method and computer-readable storage medium provided by the embodiments of the present application, when receiving an instruction from the master chip, the slave chip can respectively communicate with the M according to the input signal of the i-th detection terminal. i The logic operation between the level signals of the reference terminals generates the ith intermediate address among the N intermediate addresses, and the first address of the slave chip is generated based on the N intermediate addresses, and the first address is different from the second address carried in the instruction. In this way, the real-time detection and update of the slave chip address can be realized, the software operation process can be simplified, and the efficiency and reliability of accessing the slave chip can be improved. In addition, the actual address (first address) of the slave chip can be different from the instruction address (second address). Even if the instruction address is leaked, there is no risk of leakage, thereby improving security.

[0118] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A slave chip, characterized in that: It includes a digital module, N analog modules and N detection terminals; The i-th analog module in the N analog modules is respectively connected to the i-th detection terminal in the N detection terminals and the M i The i-th analog module is used to respectively connect the M reference terminals according to the input signal of the i-th detection terminal when the slave chip receives the instruction from the master chip. i The logic operation between the level signals of the reference terminals generates the i-th intermediate address and sends it to the digital module, N, M i , i are both positive integers, 1≤i≤N; The N intermediate addresses are used by the digital module to generate a first address of the slave chip, and the first address is different from a second address carried in the instruction.

2. The slave chip according to claim 1, characterized in that: The logic operation is an exclusive OR operation.

3. The slave chip according to claim 2, characterized in that: The i-th detection end and the M i The i-th intermediate address is M i One-hot encoding; The total number of combinations of the N intermediate addresses corresponds to the number of types of values ​​of the first address.

4. The slave chip according to claim 3, characterized in that: The total number of combinations of the N intermediate addresses and the number of types of values ​​of the first address satisfy: Wherein, D is the total number of combinations of the N intermediate addresses and the number of types of values ​​of the first address.

5. The slave chip according to claim 4, characterized in that: If the number of reference terminals that perform logic operations with each of the N detection terminals is M, the total number of combinations D of the N intermediate addresses and the number of types D of values ​​of the first address satisfy: D=M N 。 6. The slave chip according to claim 4, characterized in that: The D values ​​of the first address are The first address is divided by the value of the preset bit. The values ​​of the other bits except the preset bits are the same as the second address except the The values ​​of the other bits except the preset bits are the same. This is a round-up operation.

7. The slave chip according to claim 6, characterized in that: Said The preset bits are the lower 4 bits of the first address and the second address.

8. The slave chip according to any one of claims 1 to 7, characterized in that: The M i The reference terminals include clock input terminal, data input terminal, power supply terminal and ground terminal.

9. The slave chip according to claim 8, characterized in that: When the input signal of the clock input terminal is at a high level and the input signal of the data input terminal is at a falling edge, the digital module sends a detection enable signal to the N analog modules, and the detection enable signal is used by the i-th analog module to generate the i-th intermediate address according to the logic operation between the input signal of the i-th detection terminal and the input signal of the clock input terminal, the input signal of the data input terminal, the power supply terminal and the ground terminal.

10. A method for detecting and updating a slave chip address, characterized in that: The slave chip includes N detection terminals, wherein the i-th detection terminal among the N detection terminals is connected to the M i A reference terminal connection; The method comprises: Receive instructions from the main chip; According to the input signal of the i-th detection end and the M i The logic operation between the level signals of the reference terminals generates the i-th intermediate address among the N intermediate addresses, N, M i , i are both positive integers, 1≤i≤N; A first address of the slave chip is generated according to the N intermediate addresses, where the first address is different from a second address carried in the instruction.

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