Clock circuit
By designing a clock circuit containing a single driving circuit and using PMOS and NMOS tubes to achieve oscillation, the problems of complex structure, high consumption and high cost of traditional oscillators are solved, and the integration is improved and the cost is reduced.
Patent Information
- Application Number
- CN202420630774.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-27
- Publication Date
- 2024-12-13
- Estimated Expiration
- 2034-03-27
AI Technical Summary
Traditional oscillators have complex structures, high power consumption, high cost and short service life, making it difficult to achieve high integration and low cost design.
Design a clock circuit, including a first switching circuit, a second switching circuit, a charge and discharge circuit, a driving circuit and a control circuit, a single driving circuit replaces two comparators, and oscillation is achieved using PMOS and NMOS tubes to control the charge and discharge circuit. Charge and discharge state, reducing device number and power consumption.
Improves oscillator integration, reduces design costs, reduces power consumption and extends service life.
Smart Images
Figure CN222169781U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of oscillators, in particular to a clock circuit. Background Art
[0002] Oscillators are one of the core circuits of communication systems and are widely used in electronic products. Relaxation oscillators are widely used in the market due to their high linearity, easy control, and ability to generate sawtooth waves and square waves at the same time. Figure 3 The working principle of the oscillator is to use the current to periodically charge and discharge the capacitor to complete the oscillation. Figure 3 The voltage-controlled oscillator is mainly based on the voltage-controlled oscillator, which mainly sets two voltage thresholds through two comparators to judge the size of the input voltage, thereby generating oscillation. The working principle of the voltage-controlled oscillator is as follows: when VDD is powered on, the capacitor voltage VC is at a low level. This level generates a logic through the comparator, thereby controlling SW1 to be turned on and SW2 to be turned off. The current I1 provided by the PMOS tube M1 charges the capacitor C, causing VC to continue to rise. When VC is higher than the high-order comparator threshold voltage VH, the output logic jumps, causing SW1 to be turned off and SW2 to be turned on, that is, the current 12 provided by the NMOS tube M2 discharges the capacitor, causing VC to continue to decrease, until VC decreases to below the threshold voltage VL of the low-order comparator, the output logic jumps again, and then enters the charging state again, and this cycle repeats, achieving the output of a continuous oscillation waveform on the capacitor. It can be seen that the determining factors of the oscillation period include current I1, I2, capacitance C, threshold difference VH, VL. Due to the influence of the process, the possibility of deviation when achieving oscillation will increase, resulting in greater errors. In addition, this traditional structure requires two comparators, which has a more complex structure, a larger layout area, and a higher power consumption, which is not conducive to cost savings and reduces the service life. Utility Model Content
[0003] The main purpose of the utility model is to provide a clock circuit, aiming to improve the integration of the oscillator and reduce the design cost of the oscillator.
[0004] Therefore, the utility model proposes a clock circuit, which includes: a first switch circuit, a second switch circuit, a charge and discharge circuit, a drive circuit, a control circuit and an output circuit; the input end of the first switch circuit is used to connect to the power supply end, the output end of the first switch circuit is respectively connected to the input end of the second switch circuit, the input end of the control circuit and the input end of the drive circuit, and the connection point between the first switch circuit and the second switch circuit is connected to the input end of the output circuit; the controlled end of the control circuit is connected to the output end of the output circuit, the output end of the control circuit is connected to the input end of the second switch circuit, and the control end of the control circuit is respectively connected to the controlled end of the drive circuit and the controlled end of the charge and discharge circuit; the output end of the drive circuit is connected to the input end of the first switch circuit, the input end of the second switch circuit The output end of the second switch circuit is used to connect to the ground end; the control circuit is used to connect the path between the first switch circuit and the charge and discharge circuit when the low level signal of the output circuit is connected to the first switch circuit, so as to control the charging of the charge and discharge circuit; the drive circuit is used to drive the first switch circuit to output a low level signal to the second switch circuit and the output circuit when the charging voltage of the charge and discharge circuit reaches a first preset voltage; and the control circuit is also used to disconnect the path between the first switch circuit and the charge and discharge circuit when the high level signal of the output circuit is connected to the first switch circuit, so as to control the discharging of the charge and discharge circuit; the drive circuit is also used to drive the first switch circuit to output a high level signal to the second switch circuit and the output circuit when the discharge voltage of the charge and discharge circuit reaches a second preset voltage.
[0005] Optionally, the first switch circuit includes: a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube and an eighth PMOS tube; the input end of the first PMOS tube is used to connect to the power supply end, the controlled end of the first PMOS tube is used to access the enable signal, and the output end of the first PMOS tube is connected to the input end of the control circuit; the input end of the second PMOS tube is used to connect to the power supply end, the controlled end of the second PMOS tube is used to access the enable signal, and the output end of the second PMOS tube is connected to the input end of the control circuit; the input end of the third PMOS tube is used to connect to the power supply end, the controlled end of the third PMOS tube is used to access the enable signal, and the output end of the third PMOS tube is connected to the input end of the drive circuit; the input end of the fourth PMOS tube is used to connect to the power supply end, and the controlled end of the fourth PMOS tube is connected to the input end of the control circuit, The output end of the fourth PMOS tube is connected to the input end of the driving circuit; the input end of the fifth PMOS tube is used to connect to the power supply end, the controlled end of the fifth PMOS tube is connected to the input end of the control circuit, and the output end of the fifth PMOS tube is connected to the input end of the second switch circuit; the input end of the sixth PMOS tube is used to connect to the power supply end, the controlled end of the sixth PMOS tube is connected to the output end of the fourth PMOS tube, and the output end of the sixth PMOS tube is connected to the input end of the second switch circuit; the input end of the seventh PMOS tube is used to connect to the power supply end, the controlled end of the seventh PMOS tube is connected to the output end of the sixth PMOS tube, and the output end of the seventh PMOS tube is connected to the input end of the second switch circuit; the input end of the eighth PMOS tube is used to connect to the power supply end, the controlled end of the eighth PMOS tube is connected to the input end of the control circuit, and the output end of the eighth PMOS tube is connected to the input end of the control circuit.
[0006] Optionally, the second switch circuit includes: a first inverter, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube and a fifth NMOS tube; the controlled end of the first NMOS tube is connected to the output end of the first inverter, the input end of the first NMOS tube is connected to the output end of the control circuit, and the output end of the first NMOS tube is used to connect to the ground end; the controlled end of the second NMOS tube is connected to the output end of the first inverter, the input end of the second NMOS tube is connected to the control end of the control circuit, and the output end of the second NMOS tube is used to connect to the ground end; the controlled end of the third NMOS tube is connected to the output end of the first NMOS The input end of the third NMOS tube is connected to the output end of the control circuit, and the output end of the third NMOS tube is connected to the controlled end of the second NMOS tube; the controlled end of the fourth NMOS tube is connected to the output end of the fifth PMOS tube, the input end of the fourth NMOS tube is connected to the output end of the sixth PMOS tube, and the output end of the fourth NMOS tube is used to connect to the ground end; the controlled end of the fifth NMOS tube is respectively connected to the output end of the sixth PMOS tube and the controlled end of the seventh PMOS tube, and the input end of the fifth NMOS tube is respectively connected to the output end of the seventh PMOS tube.
[0007] Optionally, the enable signal is a first enable signal / a second enable signal; when the enable signal is the first enable signal, the first PMOS tube is turned on, the second PMOS tube is turned on, the third PMOS tube is turned on, the first NMOS tube is turned on, the second NMOS tube is turned on, the fifth PMOS tube is turned off, the sixth PMOS tube is turned off, the fourth NMOS tube is turned on, the fifth NMOS tube is turned off, and the seventh PMOS tube is turned on, and the output circuit outputs a high-voltage clock signal; when the enable signal is the second enable signal, the first PMOS tube is turned off, the second PMOS tube is turned off, the third PMOS tube is turned off, the first NMOS tube is turned off, the second NMOS tube is turned off, the eighth PMOS tube is turned on, the fourth PMOS tube is turned on, and the fifth PMOS tube is turned on.
[0008] Optionally, the control circuit includes a second switch tube and a third switch tube; the drive circuit includes a first switch tube, a fourth switch tube and a clamp tube; the controlled end of the second switch tube is connected to the controlled end of the third switch tube, and their mutual connection point is connected to the input end of the output circuit; the output end of the second switch tube is connected to the input end of the third switch tube, and their mutual connection points are respectively connected to the input end of the charge and discharge circuit and the controlled end of the first switch tube, and the output end of the charge and discharge circuit is used to connect to the ground end; the input end of the second switch tube is connected to the output end of the eighth PMOS tube; the output end of the third switch tube is connected to the input end of the third NMOS tube; the controlled end of the first switch tube is connected to the input end of the charge and discharge circuit, the controlled end of the fourth switch tube is connected to the input end of the charge and discharge circuit, the input end of the first switch tube is connected to the output end of the fourth PMOS tube, and the output end of the first switch tube is connected to the input end of the clamp tube.
[0009] Optionally, the control circuit is used to disconnect the path between the third switch tube and the third NMOS tube, and connect the path between the second switch tube and the charge and discharge circuit to control the charging of the charge and discharge circuit when a low-level signal of the output circuit is connected; the drive circuit is used to turn on the first switch tube, the fourth switch tube, the sixth PMOS tube, the fourth NMOS tube, the fifth NMOS tube, the seventh PMOS tube, and make the seventh PMOS tube output a low-level signal to the output circuit when the charging voltage of the charge and discharge circuit reaches a first preset voltage.
[0010] Optionally, the control circuit is used to disconnect the path between the second switch tube and the charge and discharge circuit and connect the path between the third switch tube and the third NMOS tube when a high-level signal of the output circuit is connected to control the discharge of the charge and discharge circuit; the drive circuit is used to disconnect the second switch tube, turn on the third switch tube, disconnect the first switch tube, disconnect the sixth PMOS tube when the charge and discharge circuit is discharging, and when the discharge voltage of the charge and discharge circuit reaches a second preset voltage, disconnect the fourth switch tube, turn on the fifth PMOS tube, turn on the fourth NMOS tube, disconnect the fifth NMOS tube, disconnect the sixth PMOS tube, turn on the seventh PMOS tube, disconnect the fifth NMOS tube, and enable the seventh PMOS tube to output a high-level signal to the output circuit.
[0011] Optionally, the charge and discharge circuit includes: a first capacitor, the input end of the first capacitor is connected to the connection point between the control end of the second switch tube and the control end of the third switch tube, and the input end of the first capacitor is used to access the adjustment signal, and the output end of the first capacitor is used to connect to the ground end.
[0012] Optionally, the output circuit includes: a second inverter and a third inverter; the input end of the second inverter is connected to the controlled end of the control circuit, the output end of the second inverter is connected to the input end of the third inverter, and the output end of the third inverter is used to output the clock signal
[0013] The utility model proposes a clock circuit, including a first switch circuit, a second switch circuit, a charge and discharge circuit, a drive circuit, a control circuit and an output circuit. The control circuit receives a low-level signal from the output circuit, conducts the path between the first switch circuit and the charge and discharge circuit, so as to control the charge of the charge and discharge circuit; when the charge voltage of the charge and discharge circuit reaches a first preset voltage, the drive circuit drives the first switch circuit to output a low-level signal to the second switch circuit; the control circuit receives a high-level signal from the output circuit, disconnects the path between the first switch circuit and the charge and discharge circuit, and conducts the path between the second switch circuit and the charge and discharge circuit, so as to control the discharge of the charge and discharge circuit; when the discharge voltage of the charge and discharge circuit reaches a second preset voltage, the drive circuit drives the first switch circuit to output a high-level signal to the second switch circuit. The utility model improves the integration of the oscillator and reduces the design cost of the oscillator. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.
[0015] Figure 1 This is a circuit flow chart of a clock circuit of the utility model;
[0016] Figure 2 This is a circuit structure diagram of a clock circuit of the utility model;
[0017] Figure 3 The circuit structure diagram of the voltage-controlled oscillator described in the background technology.
[0018] The realization of the purpose, functional features and advantages of the utility model will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION
[0019] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.
[0020] It should be noted that if the embodiments of the present invention involve directional indications (such as up, down, left, right, front, back...), the directional indications are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.
[0021] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the utility model, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, if the meaning of "and / or" appearing in the full text is to include three parallel schemes, taking "A and / or B" as an example, it includes scheme A, or scheme B, or a scheme that satisfies both A and B. In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the ability of ordinary technicians in this field to implement. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the utility model.
[0022] It is important to understand that referring to Figure 3 The determining factors of the oscillation period of the existing oscillator include current I1, I2, capacitance C, threshold difference VH, VL. Due to the influence of the process, the possibility of deviation when achieving oscillation will increase, resulting in increased error. In addition, this traditional structure requires two comparators, which has a more complex structure, a larger layout area, and a larger power consumption, which is not conducive to cost saving and reduces the service life.
[0023] Therefore, in order to improve the integration of the oscillator and reduce the design cost of the oscillator, the utility model proposes a clock circuit, referring to Figure 1 , the clock circuit includes: a first switch circuit 10, a second switch circuit 20, a charge and discharge circuit 60, a drive circuit 40, a control circuit 30 and an output circuit 50;
[0024] The input end of the first switch circuit 10 is used to connect to the power supply end, the output end of the first switch circuit 10 is respectively connected to the input end of the second switch circuit 20, the input end of the control circuit 30, and the input end of the drive circuit 40, and the connection point between the first switch circuit 10 and the second switch circuit 20 is connected to the input end of the output circuit 50; the controlled end of the control circuit 30 is connected to the output end of the output circuit 50, the output end of the control circuit 30 is connected to the input end of the second switch circuit 20, and the control end of the control circuit 30 is respectively connected to the controlled end of the drive circuit 40 and the controlled end of the charge and discharge circuit 60; the output end of the drive circuit 40 is connected to the input end of the first switch circuit 10 and the input end of the second switch circuit 20; the output end of the second switch circuit 20 is used to connect to the ground end;
[0025] The control circuit 30 is used to connect the path between the first switch circuit 10 and the charge-discharge circuit 60 when the low level signal of the output circuit 50 is connected, so as to control the charge-discharge circuit 60 to charge;
[0026] The driving circuit 40 is used to drive the first switch circuit 10 to output a low level signal to the second switch circuit 20 when the charging voltage of the charging and discharging circuit 60 reaches a first preset voltage; and
[0027] The control circuit 30 is further used to disconnect the path between the first switch circuit 10 and the charge-discharge circuit 60 when the high level signal of the output circuit 50 is connected, so as to control the charge-discharge circuit 60 to discharge;
[0028] The driving circuit 40 is further configured to drive the first switch circuit 10 to output a high level signal to the second switch circuit 20 when the discharge voltage of the charge and discharge circuit 60 reaches a second preset voltage.
[0029] It is understandable that the existing oscillator is composed of multiple devices, and two comparators are required to work together in the process of realizing oscillation. Therefore, the structure of the existing oscillator is relatively complex, the layout area is large, and the power consumption is also large, which is not conducive to cost saving. The utility model adopts a single drive circuit 40 to replace two comparators to realize the operation of the oscillator in a scenario with a small number of devices, a small occupied area, and low power consumption.
[0030] In this embodiment, the driving circuit 40 is implemented by the first switch tube Q1, the fourth switch tube Q4 and the clamp tube M6. The voltage threshold VgsQ1 of the first switch tube Q1 and the threshold VgsM6 of the clamp tube M6 are used to determine the size of the first preset voltage (VgsQ1+VgsM6); and the voltage threshold VgsQ4 of the fourth switch tube Q4 is used to determine the size of the second preset voltage (VgsQ4), thereby generating oscillation. Among them, the first switch circuit 10 includes a plurality of PMOS tubes, and the second switch circuit 20 includes a plurality of NMOS tubes. The first switch circuit 10 is used to access the enable signal, and the enable signal includes a first enable signal and a second enable signal. The first enable signal corresponds to a low level signal; the second enable signal corresponds to a high level signal. The first enable signal and the second enable signal are used to control the clock circuit to be in a non-working state / working state. It should be noted that the output circuit 50 includes a second inverter D2 and a third inverter D3. When the clock circuit is connected to the first enable signal, the first switch circuit 10 is triggered to output a high-level signal to the second switch circuit 20 and the output circuit 50 respectively, and the high-level signal is output as a high-level signal after passing through the second inverter D2 and the third inverter D3. That is, the output circuit 50 outputs a clock signal with a logic of 1, and at this time, the clock circuit is in a non-working state; when the clock circuit is connected to the second enable signal, the clock circuit starts to work, first triggering the control circuit 30 and the first switch circuit 10, outputting a low-level signal to the second switch circuit 20 and the output circuit 50, and the low-level signal is output as a low-level signal after passing through the second inverter D2 and the third inverter D3; the low-level signal triggers the control circuit 30 and the second switch circuit 20 again, outputting a high-level signal to the second switch circuit 20 and the output circuit 50, and the high-level signal is output as a high-level signal after passing through the second inverter D2 and the third inverter D3; this cycle is repeated to generate a clock signal.
[0031] Specifically, refer to Figure 1 and Figure 2, the control circuit 30 controls the charge and discharge state of the charge and discharge circuit 60 according to the clock signal output to the output circuit 50. It should be noted that the controlled end of the control circuit 30 is connected to the connection point between the second inverter D2 and the third inverter D3, that is, the controlled signal of the control circuit 30 is the inverted signal of the clock signal. In practical applications, when the clock circuit is just connected to the second enable signal (high level signal), the input end of the output circuit 50 receives a high level signal, that is, the input end of the second inverter D2 in the output circuit 50 is connected to the high level signal, and after inversion processing, a low level signal is output to the control circuit 30. The control circuit 30 receives the low level signal, and turns on the path between the first switch circuit 10 and the charge and discharge circuit 60, and outputs the current flowing from the power supply terminal VDD through the eighth PMOS tube P8 in the first switch circuit 10 to the charge and discharge circuit 60, so that the charge and discharge circuit 60 is in a charging state. When the charging voltage of the charge-discharge circuit 60 reaches the first preset voltage, the first switch tube Q1 in the drive circuit 40 is turned on, so that the first switch circuit 10 outputs a low-level signal to the second switch circuit 20 and the output circuit 50. At this time, the input end of the output circuit 50 receives the low-level signal, and the low-level signal is still output after being inverted by the second inverter D2 and the third inverter D3. It can be understood that the clock signal output by the output circuit 50 is flipped from logic 1 to logic 0.
[0032] At the same time, since the input end of the second inverter D2 in the output circuit 50 is connected to a low-level signal, a high-level signal is output to the control circuit 30 after inversion processing. The control circuit 30 receives the high-level signal, that is, disconnects the path between the first switch circuit 10 and the charge-discharge circuit 60, and conducts the path between the second switch circuit 20 and the charge-discharge circuit 60, so that the charge stored in the capacitor in the charge-discharge circuit 60 is discharged to the ground end through the third NMOS tube M3 in the second switch circuit 20, so that the charge-discharge circuit 60 is in a discharge state. The first switch tube Q1 in the drive circuit 40 is disconnected. When the discharge voltage of the charge-discharge circuit 60 reaches the second preset voltage, the fourth switch tube Q4 in the drive circuit 40 is disconnected, so that the first switch circuit 10 outputs a high-level signal to the second switch circuit 20 and the output circuit 50. At this time, the input end of the output circuit 50 is changed back to a high-level signal due to the low-level signal, and the high-level signal is still output after being inverted by the second inverter D2 and the third inverter D3. It can be understood that the clock signal output by the output circuit 50 flips from logic 0 to logic 1.
[0033] At the same time, since the input end of the second inverter D2 in the output circuit 50 is connected to a high-level signal, a low-level signal is output to the control circuit 30 after inversion processing. The control circuit 30 receives the low-level signal, that is, the path between the first switch circuit 10 and the charge-discharge circuit 60 is turned on again, so that the charge-discharge circuit 60 is in a charging state. Therefore, in this embodiment, the control circuit 30 controls the drive circuit 40 to turn on / off the PMOS tube in the first switch circuit 10 and the NMOS tube in the second switch circuit 20, so that the charge-discharge circuit 60 is switched to a charging / discharging state, so that the clock signal output by the output circuit 50 is flipped from a high potential to a low potential, or from a low potential to a high potential, thereby realizing oscillation.
[0034] The utility model provides a clock circuit, which includes: a first switch circuit 10, a second switch circuit 20, a charge and discharge circuit 60, a drive circuit 40, a control circuit 30 and an output circuit 50. The input end of the first switch circuit 10 is used to connect to the power supply end VDD, the output end of the first switch circuit 10 is respectively connected to the input end of the second switch circuit 20, the input end of the control circuit 30 and the input end of the drive circuit 40, the connection point between the first switch circuit 10 and the second switch circuit 20 is connected to the input end of the output circuit 50; the controlled end of the control circuit 30 is connected to the output end of the output circuit 50, the output end of the control circuit 30 is connected to the input end of the second switch circuit 20, and the control end of the control circuit 30 is respectively connected to the controlled end of the drive circuit 40 and the controlled end of the charge and discharge circuit 60; the output end of the drive circuit 40 is connected to the input end of the second switch circuit 20; the output end of the second switch circuit 20 is used to connect to the ground end GND. Under the condition that the clock circuit is connected to the second enable signal, the control circuit 30 is used to connect the path between the first switch circuit 10 and the charge and discharge circuit 60 when the low level signal of the output circuit 50 is connected, so as to control the charge and discharge circuit 60 to charge; the drive circuit 40 is used to drive the first switch circuit 10 to output a low level signal to the second switch circuit 20 and the output circuit 50 when the charging voltage of the charge and discharge circuit 60 reaches the first preset voltage. In addition, the control circuit 30 is also used to disconnect the path between the first switch circuit 10 and the charge and discharge circuit 60 and connect the path between the second switch circuit 20 and the charge and discharge circuit 60 when the high level signal of the output circuit 50 is connected, so as to control the charge and discharge circuit 60 to discharge; the drive circuit 40 is also used to drive the first switch circuit 10 to output a high level signal to the second switch circuit 20 and the output circuit 50 when the discharge voltage of the charge and discharge circuit 60 reaches the second preset voltage. The utility model adopts a single driving circuit 40 to replace two comparators, so that the clock signal output by the clock circuit is flipped from a high potential to a low potential, or from a low potential to a high potential, to realize the operation of the oscillator in a scenario with a small number of devices, a small occupied area and low power consumption.
[0035] Embodiment 1: The first switch circuit 10 includes a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh PMOS transistor P7 and an eighth PMOS transistor P8; the second switch circuit 20 includes a first inverter D1, a first NMOS transistor M1, a third NMOS transistor M3, a second NMOS transistor M2, a fourth NMOS transistor M4 and a fifth NMOS transistor M5; the control circuit 30 includes a second switch transistor Q2 and a third switch transistor Q3; the charge and discharge circuit 60 includes a first capacitor C1, and the clock circuit also includes a trim terminal, and the input terminal of C1 is used to access the trim signal through the trim terminal; the drive circuit 40 includes a first switch transistor Q1, a fourth switch transistor Q4 and a clamping transistor M6; the output circuit 50 includes a second inverter D2 and a third inverter D3.
[0036] In practical applications, refer to Figure 2 When the enable signal en is the first enable signal (low level signal), the first PMOS transistor P1 is turned on, the second PMOS transistor P2 is turned on, the second PMOS transistor P3 is turned on, the eighth PMOS transistor P8 is turned off, the fourth PMOS transistor P4 is turned off, the fifth PMOS transistor P5 is turned off, and the sixth PMOS transistor P6 is turned off. The first enable signal is converted into a high level signal after passing through the first inverter D1. The high level signal turns on the first NMOS transistor M1 and the second NMOS transistor M2. At this time, the level of the connection point between the output end of the second switch transistor Q2 and the output end of the third switch transistor Q3 in the control circuit 30 is pulled down to the ground end by the second NMOS transistor M2, so that the first switch transistor Q1 is turned off and the fourth switch transistor Q4 is turned off. Since the second PMOS transistor P2 is turned on and outputs a high-level signal to the gate of the fourth NMOS transistor M4, the fourth NMOS transistor M4 is turned on, and at the same time, the sixth PMOS transistor P6 is turned off, so that the common drain of the fourth NMOS transistor M4 and the sixth PMOS transistor P6 outputs a low-level signal to the gate of the seventh PMOS transistor P7 and the gate of M5, so that the seventh PMOS transistor P7 is turned on and the fifth NMOS transistor M5 is turned off, so that the seventh PMOS transistor outputs a high-level signal, and the high-level signal is output as a low-level signal after passing through the second inverter D2, that is, the level between the second inverter D2 and the third inverter D3 is a low-level signal, and the level signal input to the output circuit 50 is a low-level signal. The low-level signal is output as a high-level signal after passing through the third inverter D3, that is, the output circuit 50 outputs a clock signal with a logic of 1, and at this time, the clock circuit is in an abnormal working state.
[0037] Embodiment 2: The first switch circuit 10 includes a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh PMOS transistor P7 and an eighth PMOS transistor P8; the second switch circuit 20 includes a first inverter D1, a first NMOS transistor M1, a third NMOS transistor M3, a second NMOS transistor M2, a fourth NMOS transistor M4 and a fifth NMOS transistor M5; the control circuit 30 includes a second switch transistor Q2 and a third switch transistor Q3; the charge and discharge circuit 60 includes a first capacitor C1, and the clock circuit also includes a trim terminal, and the input terminal of C1 is used to access the trim signal through the trim terminal; the drive circuit 40 includes a first switch transistor Q1, a fourth switch transistor Q4 and a clamping transistor M6; the output circuit 50 includes a second inverter D2 and a third inverter D3.
[0038] In practical applications, refer to Figure 2, when the enable signal en is the second enable signal (high level signal), the first PMOS tube P1 is disconnected, the second PMOS tube P2 is disconnected, and the third PMOS tube P3 is disconnected. At this time, the low level signal disconnects the first NMOS tube M1 and the second NMOS tube M2, and at this time, the clock circuit starts to work normally. It can be seen from the above content that when the clock circuit just starts to work normally, the output circuit 50 maintains the clock signal with an output logic of 1. That is, the level signal between the second inverter D2 and the third inverter D3 is a low level signal, and the low level signal is input to the controlled end of the second switch tube Q2 and the controlled end of the third switch tube Q3, so that the second switch tube Q2 is turned on, the third switch tube Q3 is turned off, and the first capacitor C1 starts to charge. The current flowing from the power supply terminal VDD through the eighth PMOS tube P8 is output to the first capacitor C1 through the second switch tube Q2, or the bias current at the ib end passes through the mirror of the eighth PMOS tube P8, flows through the second switch tube Q2 and is output to the first capacitor C1, thereby charging the first capacitor C1. During the first preset time when the first capacitor C1 starts to charge, the fourth PMOS transistor P4 is turned on and outputs a high-level signal, and the high-level signal turns off the sixth PMOS transistor P6. It should be understood that the first switch tube Q1 and the fourth switch tube Q4 are of the same type and size (VgsQ1= VgsQ4), and the voltage on the first capacitor C1 starts to charge from 0, and the charging voltage reaches the second preset voltage value (VgsQ4) first, and the fourth switch tube Q4 (VgsQ4) is turned on before the first switch tube Q1 (VgsQ1+VgsM6), that is, the first switch tube Q1 is turned off, and the fourth switch tube Q4 is turned on, so that the drain output of the fourth switch tube Q4 is low level, and serves as the gate input of the fourth NMOS tube M4, so that the fourth NMOS tube M4 is turned off, and the sixth PMOS tube P6 still remains in the off state, so the input end of the second inverter D2 maintains the previous high potential state, and the output of the output circuit 50 maintains a high potential. Until the first capacitor C1 continues to charge to the first preset voltage (VgsQ1+VgsM6), the first switch tube Q1 is also turned on. Since the first switch tube Q1 is turned on to generate a pull-down signal, the level of the controlled end of the sixth PMOS tube P6 is pulled down to turn on the sixth PMOS tube P6. At this time, the fourth NOMOS tube M4 remains off, so that the common drain of the sixth PMOS tube P6 and the fourth NOMOS tube M4 outputs a high-level signal to the gate controlled end of the fifth NMOS tube M5 and the seventh PMOS tube P7, so that the fifth NMOS tube M5 is turned on and the seventh PMOS tube P7 is turned off, and the common drain of the seventh PMOS tube P7 and the fifth NMOS tube M5 outputs a low-level signal to the second inverter D2, so that the input end of the second inverter D2 jumps from a high potential to a low potential, so that the output of the output circuit 50 flips from a high potential to a low potential.
[0039] At the same time, the potential between the second inverter D2 and the third inverter D3 flips from a low potential to a high potential, that is, the level signal between the second inverter D2 and the third inverter D3 is a high level signal. The high level signal is input to the controlled end of the second switch tube Q2 and the controlled end of the third switch tube Q3, so that the second switch tube Q2 is disconnected, the third switch tube Q3 is turned on, and the first capacitor C1 starts to discharge to the ground end through the third NMOS tube M3. When the discharge voltage on C1 drops to the first preset voltage (VgsQ1+VgsM6), the first switch tube Q1 is disconnected first, and the fourth switch tube Q4 remains in the open state, so that the sixth PMOS tube P6 is disconnected, so that the drain output of the fourth switch tube Q4 is low level, and serves as the gate input of the fourth NMOS tube M4, so that the fourth NMOS tube M4 is disconnected, so that the output circuit 50 maintains the previous output low potential state. Until the discharge voltage on the first capacitor C1 drops to the second preset voltage (VgsQ4), the fourth switch tube Q4 is turned off, the first switch tube Q1 remains in the off state, the fifth PMOS tube P5 is turned on, and the drain of the fifth PMOS tube P5 outputs a high potential, which is used as the gate input voltage of the fourth NMOS tube M4, so that the fourth NMOS tube M4 is turned on, and the sixth PMOS tube P6 is maintained in the off state, so that the common drain of the sixth PMOS tube P6 and the fourth NMOS M4 outputs a low level, thereby turning on the seventh PMOS tube P7 and turning off the fifth NMOS tube M5, so that the common drain of the seventh PMOS tube P7 and the fifth NMOS tube M5 outputs a high level. This high-level signal is input to the second inverter D2, so that the input end of the second inverter D2 jumps from a low potential to a high potential, so that the output of the output circuit 50 flips from a low potential to a high potential.
[0040] At the same time, the potential between the second inverter D2 and the third inverter D3 flips from a high potential to a low potential, turning on the second switch tube Q2 and turning off the third switch tube Q3. The first capacitor C1 starts to charge again, and the next cycle continues, thereby forming a clock signal with a period of 1us.
[0041] It is important to understand that referring to Figure 2 The clock circuit includes an ib terminal, an en terminal and a trim terminal, wherein the en terminal is used to access an enable signal. When VDD is at a high level and the en enable signal is at a low level, that is, when en=0, the eighth PMOS tube P8 is disconnected, the third PMOS tube M3 is disconnected, the first capacitor C1 does not charge or discharge, the clock outputs a high level, and is in a non-working state; when VDD is at a high level and the en enable signal is at a high level, that is, when en=1, the ib terminal is used to access a bias current, that is, it can be considered that the current ib terminal is used to access a fixed bias voltage. The trim terminal is used to access a trim signal to trim the capacitance value of the first capacitor C1. By adjusting different trim values, the corresponding C1 capacitance value can be increased or decreased.
[0042] The above embodiments are only preferred embodiments of the present invention, and do not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.
Claims
1. A clock circuit, characterized in that: The clock circuit includes: a first switch circuit, a second switch circuit, a charge and discharge circuit, a drive circuit, a control circuit and an output circuit; The input end of the first switch circuit is used to connect to the power supply end, the output end of the first switch circuit is respectively connected to the input end of the second switch circuit, the input end of the control circuit, and the input end of the drive circuit, and the connection point between the first switch circuit and the second switch circuit is connected to the input end of the output circuit; the controlled end of the control circuit is connected to the output end of the output circuit, the output end of the control circuit is connected to the input end of the second switch circuit, and the control end of the control circuit is respectively connected to the controlled end of the drive circuit and the controlled end of the charge and discharge circuit; the output end of the drive circuit is connected to the input end of the first switch circuit and the input end of the second switch circuit; the output end of the second switch circuit is used to connect to the ground end; The control circuit is used to conduct the path between the first switch circuit and the charge-discharge circuit when the low-level signal of the output circuit is connected, so as to control the charge-discharge circuit to charge; The driving circuit is used to drive the first switch circuit to output a low level signal to the second switch circuit and the output circuit when the charging voltage of the charging and discharging circuit reaches a first preset voltage; and The control circuit is further used to disconnect the path between the first switch circuit and the charge-discharge circuit when a high-level signal of the output circuit is connected, so as to control the charge-discharge circuit to discharge; The driving circuit is further configured to drive the first switch circuit to output a high level signal to the second switch circuit and the output circuit when the discharge voltage of the charge and discharge circuit reaches a second preset voltage.
2. The clock circuit according to claim 1, wherein: The first switch circuit includes: a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube and an eighth PMOS tube; The input end of the first PMOS tube is used to connect to the power supply end, the controlled end of the first PMOS tube is used to access the enable signal, and the output end of the first PMOS tube is connected to the input end of the control circuit; The input end of the second PMOS tube is used to connect to the power supply end, the controlled end of the second PMOS tube is used to access the enable signal, and the output end of the second PMOS tube is connected to the input end of the control circuit; The input end of the third PMOS tube is used to connect to the power supply end, the controlled end of the third PMOS tube is used to access the enable signal, and the output end of the third PMOS tube is connected to the input end of the driving circuit; The input end of the fourth PMOS tube is used to connect to the power supply end, the controlled end of the fourth PMOS tube is connected to the input end of the control circuit, and the output end of the fourth PMOS tube is connected to the input end of the driving circuit; The input end of the fifth PMOS tube is used to connect to the power supply end, the controlled end of the fifth PMOS tube is connected to the input end of the control circuit, and the output end of the fifth PMOS tube is connected to the input end of the second switch circuit; The input end of the sixth PMOS tube is used to connect to the power supply end, the controlled end of the sixth PMOS tube is connected to the output end of the fourth PMOS tube, and the output end of the sixth PMOS tube is connected to the input end of the second switch circuit; The input end of the seventh PMOS tube is used to connect to the power supply end, the controlled end of the seventh PMOS tube is connected to the output end of the sixth PMOS tube, and the output end of the seventh PMOS tube is connected to the input end of the second switch circuit; The input end of the eighth PMOS tube is used to connect to the power supply end, the controlled end of the eighth PMOS tube is connected to the input end of the control circuit, and the output end of the eighth PMOS tube is connected to the input end of the control circuit.
3. The clock circuit according to claim 2, characterized in that: The second switch circuit includes: a first inverter, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor and a fifth NMOS transistor; The controlled end of the first NMOS tube is connected to the output end of the first inverter, the input end of the first NMOS tube is connected to the output end of the control circuit, and the output end of the first NMOS tube is used to connect to the ground end; The controlled end of the second NMOS tube is connected to the output end of the first inverter, the input end of the second NMOS tube is connected to the control end of the control circuit, and the output end of the second NMOS tube is used to connect to the ground end; The controlled end of the third NMOS tube is connected to the input end of the first NMOS tube, and the mutual connection point is used to connect the power supply end, the input end of the third NMOS tube is connected to the output end of the control circuit, and the output end of the third NMOS tube is connected to the controlled end of the second NMOS tube; The controlled end of the fourth NMOS tube is connected to the output end of the fifth PMOS tube, the input end of the fourth NMOS tube is connected to the output end of the sixth PMOS tube, and the output end of the fourth NMOS tube is used to connect to the ground end; The controlled end of the fifth NMOS tube is respectively connected to the output end of the sixth PMOS tube and the controlled end of the seventh PMOS tube, and the input end of the fifth NMOS tube is respectively connected to the output end of the seventh PMOS tube.
4. The clock circuit according to claim 3, characterized in that: The enable signal is a first enable signal / a second enable signal; When the enable signal is the first enable signal, the first PMOS tube is turned on, the second PMOS tube is turned on, the third PMOS tube is turned on, the first NMOS tube is turned on, the second NMOS tube is turned on, the fifth PMOS tube is turned off, the sixth PMOS tube is turned off, the fourth NMOS tube is turned on, the fifth NMOS tube is turned off, and the seventh PMOS tube is turned on, and the output circuit outputs a high-potential clock signal; When the enable signal is the second enable signal, the first PMOS tube is turned off, the second PMOS tube is turned off, the third PMOS tube is turned off, the first NMOS tube is turned off, the second NMOS tube is turned off, the eighth PMOS tube is turned on, the fourth PMOS tube is turned on, and the fifth PMOS tube is turned on.
5. The clock circuit according to claim 3, characterized in that: The control circuit includes a second switch tube and a third switch tube; the drive circuit includes a first switch tube, a fourth switch tube and a clamp tube; The controlled end of the second switch tube is connected to the controlled end of the third switch tube, and the interconnection point thereof is connected to the input end of the output circuit; the output end of the second switch tube is connected to the input end of the charge and discharge circuit and the controlled end of the first switch tube, respectively, and the output end of the charge and discharge circuit is used to connect to the ground end; the input end of the second switch tube is connected to the output end of the eighth PMOS tube; the output end of the third switch tube is connected to the input end of the third NMOS tube; the controlled end of the first switch tube is connected to the input end of the charge and discharge circuit, the controlled end of the fourth switch tube is connected to the input end of the charge and discharge circuit, the input end of the first switch tube is connected to the output end of the fourth PMOS tube, and the output end of the first switch tube is connected to the input end of the clamp tube.
6. The clock circuit according to claim 5, characterized in that: The control circuit is used to disconnect the path between the third switch tube and the third NMOS tube and connect the path between the second switch tube and the charge-discharge circuit when the low-level signal of the output circuit is connected, so as to control the charge-discharge circuit to charge; The driving circuit is used to turn on the first switch tube, turn on the fourth switch tube, turn on the sixth PMOS tube, turn off the fourth NMOS tube, turn on the fifth NMOS tube, turn on the seventh PMOS tube, and turn off the seventh PMOS tube when the charging voltage of the charging and discharging circuit reaches a first preset voltage, and make the seventh PMOS tube output a low-level signal to the output circuit.
7. The clock circuit according to claim 5, characterized in that: The control circuit is used to disconnect the path between the second switch tube and the charge-discharge circuit and connect the path between the third switch tube and the third NMOS tube when the high level signal of the output circuit is connected, so as to control the discharge of the charge-discharge circuit; The driving circuit is used to disconnect the second switch tube, turn on the third switch tube, disconnect the first switch tube, and disconnect the sixth PMOS tube when the charge and discharge circuit is discharging; and when the discharge voltage of the charge and discharge circuit reaches a second preset voltage, disconnect the fourth switch tube, turn on the fifth PMOS tube, and turn on the fourth NMOS tube; disconnect the fifth NMOS tube, disconnect the sixth PMOS tube, turn on the seventh PMOS tube, disconnect the fifth NMOS tube, and enable the seventh PMOS tube to output a high-level signal to the output circuit.
8. The clock circuit according to claim 5, characterized in that: The charging and discharging circuit comprises: A first capacitor, wherein an input end of the first capacitor is connected to a connection point between a control end of the second switch tube and a control end of a third switch tube, and the input end of the first capacitor is used to access a trimming signal, and an output end of the first capacitor is used to connect to a ground end.
9. The clock circuit according to claim 1, wherein: The output circuit comprises: A second inverter and a third inverter; the input end of the second inverter is connected to the controlled end of the control circuit, the output end of the second inverter is connected to the input end of the third inverter, and the output end of the third inverter is used to output a clock signal.