Bonding pad structure of semiconductor chip for copper lead bonding packaging
The pad structure with raised bumps on the passivation layer addresses the issue of chip damage and electrical degradation in copper wire bonding by enhancing the bonding process yield and stability through effective buffering and reduced pad spacing.
Patent Information
- Application Number
- CN202420744056.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-11
- Publication Date
- 2024-12-31
- Estimated Expiration
- 2034-04-11
AI Technical Summary
Wire bonding with copper wires can damage the chip structure and cause electrical performance degradation due to crater formation and metal splashing during the bonding process, leading to short circuits.
A pad structure with raised bumps on the inner side wall of the passivation layer increases the surface area, providing a buffer for metal droplets and preventing splashing, thus avoiding short circuits and optimizing pad spacing.
The pad structure enhances the bonding process yield and stability by preventing metal splashing and short circuits, allowing for closer pad arrangements without increasing the metal pad area.
Smart Images
Figure CN222281987U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the field of semiconductor devices, in particular to a pad structure of a semiconductor chip for copper wire bonding packaging. Background Art
[0002] Among the existing chip packaging technologies, wire bonding is the dominant method of semiconductor connection due to its simple process, low cost, and applicability to a variety of packaging forms. Wire bonding is divided into ball bonding and wedge bonding, and the materials used for bonding wires are mainly gold, silver, aluminum, and copper. Because copper has higher thermal and electrical conductivity and gold is expensive, wire bonding mostly uses copper and copper alloys as bonding wire materials, such as the common palladium-coated copper wire.
[0003] However, during wire bonding, since the material of copper wire is harder than gold and aluminum, when wire bonding and packaging the copper wire, the copper wire may be squeezed on the pad to form craters due to the relatively hard copper and the influence of various parameters in the wire bonding and packaging process, which may affect the structure under the chip, or the squeeze may cause the Al material in the pad to splash out onto the passivation protective film, causing a short circuit between the two pads.
[0004] Therefore, how to prevent wire bonding from damaging the chip structure or causing a degradation in electrical performance has become a technical problem that needs to be urgently solved by those skilled in the art. Summary of the invention
[0005] The utility model provides a pad structure of a semiconductor chip for copper wire bonding packaging, so as to solve the problems that wire bonding damages the chip structure or causes a decrease in electrical performance.
[0006] According to a first aspect of the utility model, there is provided a pad structure of a semiconductor chip for copper wire bonding packaging, comprising:
[0007] The metal pad is a rectangular structure and is the lead-out terminal of the semiconductor chip;
[0008] A passivation layer covers the surface of the semiconductor chip, and an opening having a size close to that of the metal pad is arranged at a position corresponding to the metal pad; a plurality of raised bumps are arranged on the inner wall surface of the opening to increase the surface area of the inner wall.
[0009] Optionally, the metal pad is a square pad, and the corresponding opening is a square opening. The passivation layer is retained at four top corners of the square opening and is spliced with bumps perpendicular to two sides to form a stepped bump.
[0010] Optionally, a plurality of the protrusions are distributed at equal intervals on the inner side walls of the four sides of the square opening.
[0011] Optionally, a plurality of the protrusions are distributed at equal intervals on the inner side wall outside the inscribed circle of the square opening.
[0012] Optionally, the height of the bump is equal to the thickness of the passivation layer.
[0013] Optionally, the shape of the protrusion is approximately a cuboid or a cube.
[0014] Optionally, the spacing between adjacent bumps is 2um to 4um; and the protruding length of the bump relative to the inner wall surface is 2um to 6um.
[0015] Optionally, the main metal component of the metal pad is aluminum.
[0016] Compared with the prior art, the technical solution of the utility model has the following advantages:
[0017] The utility model provides a pad structure for a semiconductor chip for copper wire bonding packaging, which increases the surface area of the inner side wall of the passivation layer by setting a plurality of raised bumps on the side wall of the original flat passivation layer, and provides a buffer for metal droplets splashing and impacting the passivation layer, thereby eliminating the phenomenon of metal splashing out of the opening of the metal pad. Furthermore, it can also avoid the phenomenon of short circuit between other metal pads caused by metal splashing out of the metal pad. In addition, compared with the traditional solution of setting a larger spacing between metal pads in order to avoid short circuit, in the technical solution provided by the utility model, since the problem of short circuit is avoided, a smaller arrangement spacing between metal pads can be set, thereby optimizing the arrangement design.
[0018] Furthermore, the pad structure of the semiconductor chip for copper wire bonding packaging provided by the utility model, for copper wires with larger wire diameters, provides an effective buffering of the speed at which the molten copper metal impacts the side wall of the passivation layer of the metal pad without increasing the area of the metal pad by setting bumps only on the inner side wall outside the inscribed circle, thereby playing a certain role in preventing sputtering and facilitating the bonding process on the metal pad. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.
[0020] Figure 1 A top view of a pad structure of a semiconductor chip for copper wire bonding packaging provided by an embodiment;
[0021] Figure 2 An embodiment provides Figure 1 A cross-sectional view of a pad structure of a semiconductor chip for copper wire bonding packaging along the a or b axis;
[0022] Figure 3 It is a top view of a pad structure of a semiconductor chip for copper wire bonding packaging provided by an embodiment of the utility model;
[0023] Figure 4 The utility model is provided by an embodiment of the invention Figure 3 The cross-sectional view of the a-axis in ;
[0024] Figure 5 The utility model is provided by an embodiment of the invention Figure 3 The cross-section diagram along the b-axis in FIG.
[0025] Figure 6 It is a top view of a pad structure of a semiconductor chip for copper wire bonding packaging provided by another embodiment of the utility model;
[0026] Figure 7 Another embodiment of the present invention provides Figure 6 The cross-section diagram along the c-axis in ;
[0027] Figure 8 Another embodiment of the present invention provides Figure 6 The cross-sectional view of the d-axis in ;
[0028] Description of reference numerals:
[0029] 1, 2-pad structure for semiconductor chips packaged with copper wire bonding;
[0030] 10, 20-metal pad;
[0031] 11, 21-passivation layer;
[0032] 110, 210-opening;
[0033] 111, 211-bump;
[0034] 212-inscribed circle;
[0035] 1110-stepped bump;
[0036] 12, 22-first conductive layer;
[0037] 13, 23- second conductive layer;
[0038] 14, 24-conductive plug. DETAILED DESCRIPTION
[0039] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0040] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices. The terms "on" and "above" and any variations thereof are intended to describe positional relationships and do not represent a relationship of direct contact between the described objects.
[0041] As described in the background art, during wire bonding, wire bonding may damage the chip structure or reduce the electrical performance. This will be described in detail below with reference to the accompanying drawings.
[0042] Figure 1-2 An embodiment provides a structure of a semiconductor chip lead-out terminal; wherein: Figure 1 is a top view of the structure of a semiconductor chip lead-out terminal provided by an embodiment; Figure 2 yes Figure 1 A cross-sectional view of the structure of the semiconductor chip lead-out terminal along the a or b axis is provided.
[0043] Please refer to Figure 1-2 , is a structure of a semiconductor chip lead-out terminal, comprising: a first conductive layer 12 and a second conductive layer 13, and a conductive plug 14 connecting the first conductive layer 12 and the second conductive layer 13. A metal pad 10 is located on the surface of the first conductive layer 12; a passivation layer 11 covers the surface and sidewall of the first conductive layer 12, and the passivation layer 11 exposes a portion of the metal pad 10, so that an opening 110 of a size close to that of the metal pad 10 is provided at a position corresponding to the metal pad 10.
[0044] exist Figure 1-2In the structure of the lead-out terminal of the semiconductor chip shown, when the metal copper wire is bonded to the metal pad 10 at the opening 110, due to the relatively hard material of copper and the influence of various parameters in the wire bonding process, pits will be formed on the surface of the metal pad 10, causing the molten copper to splash, resulting in a short circuit problem between different metal pads 10.
[0045] In order to solve the above problems, the inventors of the present application found that: Figure 1-2 In the structure of the lead-out terminal of the semiconductor chip shown, the passivation layer is a passivation layer 11 with smooth edges, so the structure cannot effectively prevent the splashing of metal copper.
[0046] Therefore, the utility model provides a pad structure of a semiconductor chip for copper wire bonding packaging, comprising: a rectangular metal pad serving as a lead-out end of the semiconductor chip; a passivation layer covering the surface of the semiconductor chip, having an opening close in size to the metal pad at a position corresponding to the metal pad; and a plurality of raised bumps on the inner side wall surface of the opening to increase the surface area of the inner side wall.
[0047] In the above technical solution provided by the utility model, a plurality of bumps are arranged on the smooth edge of the passivation layer to increase the surface area of the side wall of the passivation layer, and when aluminum splashes due to the extrusion of the pad, the plurality of bumps can buffer the speed of aluminum impacting the side wall of the passivation layer, thereby playing a certain role in preventing sputtering. The technical solution provided by the utility model is applicable to metal bonding processes with a wire diameter of 0.6 mil, 0.8 mil or 1.0 mil for metal leads.
[0048] It can be seen that the technical solution provided by the utility model solves the problem that wire bonding damages the chip structure or causes a decrease in electrical performance, and improves the yield of wire bonding.
[0049] The technical solution of the present invention is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.
[0050] Figures 3 to 5 The present invention is a schematic diagram of a pad structure of a semiconductor chip for copper wire bonding packaging provided by an embodiment of the utility model; wherein: Figure 3 It is a top view of a pad structure of a semiconductor chip for copper wire bonding packaging provided by an embodiment of the utility model; Figure 4 The pad structure provided by an embodiment of the utility model is along Figure 3 The cross-sectional view of the a-axis in ; Figure 5 The utility model is provided by an embodiment of the invention Figure 3 Cross-sectional view along the b-axis.
[0051] Please refer to Figures 3 to 5 The utility model provides a pad structure for a semiconductor chip for copper wire bonding packaging, comprising:
[0052] The metal pad 10 is a rectangular structure and is a lead-out terminal of the semiconductor chip.
[0053] The passivation layer 11 covers the surface of the semiconductor chip, and an opening 110 of a size close to that of the metal pad 10 is arranged at the position corresponding to the metal pad 10; a plurality of raised bumps 111 are arranged on the inner wall surface of the opening 110 to increase the surface area of the inner wall.
[0054] The utility model provides a pad structure for a semiconductor chip for copper wire bonding packaging, which increases the surface area of the inner side wall of the passivation layer by setting a plurality of raised bumps on the side wall of the original flat passivation layer, and provides a buffer for metal droplets splashing and impacting the passivation layer, thereby eliminating the phenomenon of metal splashing out of the opening of the metal pad. Furthermore, it can also avoid the phenomenon of metal splashing out of the metal pad and causing a short circuit with other metal pads. At the same time, compared with the larger spacing between metal pads designed to avoid short circuits, the utility model can reduce the spacing between metal pads while avoiding metal splashing, thereby optimizing the design distance.
[0055] The embodiments of the pad structure of the semiconductor chip for copper wire bonding packaging will be described in detail below in conjunction with the above drawings.
[0056] The metal pad 10 is a rectangular structure, used as the lead-out terminal of the semiconductor chip. The rectangular structure here refers to the shape of the projection of the metal pad 10 on the surface of the substrate in the semiconductor chip. Specifically, the rectangular structure may include a rectangle or a square. In a specific embodiment, the main metal component of the metal pad 10 is aluminum, that is, a common aluminum metal pad.
[0057] A passivation layer 11 covers the surface of the semiconductor chip, and an opening 110 of a size close to that of the metal pad 10 is arranged at the position corresponding to the metal pad 10; a plurality of raised bumps 111 are arranged on the inner side wall surface of the opening 110, and the arrangement of the bumps 111 increases the surface area of the inner side wall relative to the flat side wall surface.
[0058] In some specific embodiments, the material of the passivation layer 11 may be any one of inorganic materials such as SiO 2 , Al 2 O 3 , Si 3 N 4 , and Ta 2 O 5 .
[0059] In one embodiment, the material of the bonding metal lead is copper, and during the bonding process, solute-like copper metal will be in contact with the metal pad. In some specific embodiments, the metal pad 10 is a square pad, and the opening 110 of the corresponding upper passivation layer is a square opening 110. From the perspective of the manufacturing process of the bump 111, considering the convenience of the manufacturing process, in one embodiment, the height of the bump 111 is equal to the thickness of the passivation layer 11. In a specific embodiment, the preparation process of the passivation layer includes: using a semiconductor vapor deposition process to cover the surface of the metal pad with a passivation layer; subsequently, photolithography and etching processes can be used to etch the opening above the metal pad and the bump 111 located at the edge of the opening 110.
[0060] The height of the bump 111 being equal to the height of the passivation layer 11 means that before etching the bump 111 and the opening 110, the height of the passivation layer 11 covering the surface of the metal pad 10 is uniform, so that the bump 111 and the opening 110 can be fabricated by depositing and etching the passivation layer 11 once. In this embodiment, the thickness of the bump 111 is consistent with the thickness of the passivation layer 11, and only one photolithography and etching are required, so the preparation process is simple and convenient.
[0061] In this embodiment, the shape of the protrusion 111 is approximately a cuboid or a cube.
[0062] In other implementations, the shape of the protrusion 111 formed on the inner wall may also be other shapes, which will not be described in detail in the present invention.
[0063] Taking the metal pad 10 with a size of 50um*50um as an example, the length of the protrusion of the bump 111 relative to the inner wall surface is: 2um~6um. When the bump is used in the photolithography process of the passivation layer, the pattern of the bump can be added to the exposed mask. The specific size of the bump can be adjusted according to the manufacturing capacity of the machine implemented by the photolithography process, and can also be combined with the margin of the opening on the metal pad relative to the copper wire diameter in the copper wire bonding process. In this embodiment, the bumps 111 are evenly spaced on the inner walls of the four sides of the square opening 110. The bumps 111 are evenly spaced on the inner walls of the four sides of the square opening 110, and several of the bumps 111 are evenly spaced along the inner wall. When the corresponding opening 110 is a square opening 110, the passivation layer 11 is retained at the four top corners of the square opening 110 and the bumps 111 perpendicular to the two sides are spliced into a stepped bump 1110.
[0064] In summary, the arrangement of the bumps with equal spacing provided in this embodiment is relatively suitable for use in the copper wire bonding process for copper wires with smaller diameters. Under the premise of not increasing the corresponding opening area above the metal pad, when the margin of the opening area relative to the wire diameter of the copper wire is sufficient, the inner side wall of the opening can be filled with bumps as much as possible, which can effectively buffer the speed of the solute copper metal impacting the side wall of the passivation layer of the metal pad during the bonding process, play a certain role in preventing sputtering, and improve the yield and stability of the bonding process.
[0065] Another embodiment of the present invention is introduced here. In this embodiment, the metal pad 20 is also taken as a square pad for illustration.
[0066] Figures 6 to 8 1 is a schematic diagram of a pad structure 2 of a semiconductor chip for copper wire bonding packaging provided by another embodiment of the utility model; wherein: Figure 6 It is a top view of a pad structure 2 of a semiconductor chip for copper wire bonding packaging provided by another embodiment of the utility model; Figure 7 Another embodiment of the present invention provides a pad structure along the Figure 6 The cross-section diagram along the c-axis in ; Figure 8 Another embodiment of the utility model provides Figure 6 The difference between this embodiment and the above-mentioned embodiment is that the arrangement of the bumps 211 is different.
[0067] Please refer to Figures 6 to 8 The pad structure 2 of the semiconductor chip packaged by copper wire bonding includes: a metal pad 20, a rectangular structure, which is the lead-out end of the semiconductor chip; a passivation layer 21, covering the surface of the semiconductor chip, and an opening 210 with a size close to that of the metal pad 20 is arranged at a position corresponding to the metal pad 20; a plurality of raised bumps 211 are arranged on the inner side wall surface of the opening 210 to increase the surface area of the inner side wall.
[0068] In this embodiment, the bump 211 is disposed outside the inscribed circle 212 of the square opening 210 of the passivation layer 21 .
[0069] This embodiment can apply a bonding process with a copper wire with a thicker wire diameter. Taking a metal pad with a square size of 50um*50um as an example, the length of the protrusion of the bump 211 relative to the inner wall surface can be slightly greater than or equal to 2um. In this way, as many bumps as possible can be arranged. When bonding with a copper wire with a larger wire diameter, the bump does not occupy the area of the inscribed circle, which can alleviate the sputtering problem caused by bonding with copper wire to a certain extent. Outside the inscribed circle, the bumps 211 are also distributed on the inner wall outside the inscribed circle at equal intervals. When the bumps 211 are at the four corners of the square metal pad, they form stepped bumps with the bumps at the corners.
[0070] In summary, two different specific embodiments of pad structures for semiconductor chips for copper wire bonding packaging are provided above. A bump is added to the inner side wall of the pad structure provided by the utility model. In the above embodiments, the exemplified bumps are exemplified in a manner that facilitates production and reduces production costs, and specific bump shapes and sizes are exemplified. However, as a technician in this field, it should be understood that the bumps actually formed may not be as regular as the shapes in the attached drawings provided by the utility model, and the corners may be rounded. The shape of the bumps should not be limited to the shapes or structures exemplified in the above embodiments. The added bumps are mainly used to increase the surface area of the inner side of the pad without increasing the area of the metal pad, so as to alleviate the sputtering of Al in the material of the pad structure in the copper wire bonding packaging process, and improve the yield of the bonding package and the stability of the bonding process.
[0071] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A pad structure for a semiconductor chip for copper wire bonding packaging, characterized in that: include: The metal pad is a rectangular structure and is the lead-out terminal of the semiconductor chip; A passivation layer covers the surface of the semiconductor chip, and an opening having a size close to that of the metal pad is arranged at a position corresponding to the metal pad; a plurality of raised bumps are arranged on the inner wall surface of the opening to increase the surface area of the inner wall.
2. The pad structure of a semiconductor chip for copper wire bonding packaging according to claim 1, characterized in that: The metal pad is a square pad, and the corresponding opening is a square opening. The passivation layer is retained at the four top corners of the square opening and is spliced with the bumps perpendicular to the two sides to form a stepped bump.
3. The pad structure of a semiconductor chip for copper wire bonding packaging according to claim 2, characterized in that: A plurality of the protrusions are distributed at equal intervals on the inner side walls of the four sides of the square opening.
4. The pad structure of a semiconductor chip for copper wire bonding packaging according to claim 2, characterized in that: A plurality of the protrusions are distributed at equal intervals on the inner side wall outside the inscribed circle of the square opening.
5. The pad structure of a semiconductor chip for copper wire bonding packaging according to any one of claims 2 to 4, characterized in that: The height of the bump is equal to the thickness of the passivation layer.
6. The pad structure of a semiconductor chip for copper wire bonding packaging according to claim 5, characterized in that: The shape of the protrusion is approximately a cuboid or a cube.
7. The pad structure of a semiconductor chip for copper wire bonding packaging according to claim 1, characterized in that: The spacing between adjacent protrusions is 2um to 4um; the protrusion length of the protrusion relative to the inner wall surface is 2um to 6um.
8. The pad structure of a semiconductor chip for copper wire bonding packaging according to claim 1, characterized in that: The main metal component of the metal pad is aluminum.