Design method for judging out-of-step separation based on application compensating impedance principle
A technology of compensating impedance and design method, which is applied in the design field of judging out-of-phase decoupling based on the principle of applying compensating impedance, can solve the problems of difficulty in calculating accurate impedance values, high requirements for synchronization time scale, and complicated device implementation, and achieves Solve the effects of very high communication reliability requirements, poor adaptability to grid structure changes, and inaccurate judgment ranges
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[0028] The following is a preferred embodiment of the present invention, including the description of the criterion of the out-of-synchronization de-sequencing device of the power system realized by the method of the present invention. Other characteristics, objects and advantages of the present invention can also be seen from the description of the embodiments and from the accompanying drawing 2 .
[0029] As shown in Figure 2, there is a high-speed communication channel between the out-of-synchronization de-serialization device A and the out-of-synchronization de-serialization device B, and the clock of device A is synchronized with the clock of device B through the high-speed communication channel.
[0030] (1) Device A samples and calculates bus voltage phasor U A and the line current phasor I A , and label the phasor U A , I A Time scale; device B samples and calculates bus voltage phasor U B and the line current phasor I B , and label the phasor U B , I B time sca...
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