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Method, device and system for controlling read and write of synchronous dynamic memory

A technology of synchronous dynamic, read and write control, applied in the field of memory

Active Publication Date: 2014-09-10
ZTE CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Constrained by cost and capacity, it is impractical to use the fastest memory to alleviate the shortage of cache capacity

Method used

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  • Method, device and system for controlling read and write of synchronous dynamic memory
  • Method, device and system for controlling read and write of synchronous dynamic memory
  • Method, device and system for controlling read and write of synchronous dynamic memory

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no. 1 example

[0045] In the first embodiment of the present invention, a synchronous dynamic memory read and write control method, such as figure 2 shown, including the following specific steps:

[0046] Step S101 , when an instruction for accessing the synchronous dynamic memory is generated in the instruction cache, it is judged whether it is an instruction for accessing the same data stream, if yes, go to step S103 , otherwise go to step S102 . The command can be a write command or a read command.

[0047] In this field, if the generated instruction to access the synchronous dynamic memory is a write instruction, there will be a data packet input at the same time, and the input data packet will be split into fixed-length data slices, and the fixed length of the data slice is 64-1.5K Choose between bytes, usually 64 bytes. The write command includes the corresponding relationship between the data slice and the internal body.

[0048] If the generated command to access the synchronous ...

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Abstract

Disclosed in the present invention are read-write controlling method, device and system for synchronous dynamic memory. And the method comprises: when a command of accessing the synchronous dynamic memory is generated, carrying out time compression on the command and then executing the command in the case of an inner-bank corresponding to the command meeting an inner-bank average distribution. The device comprises a command buffer module and a buffer control module. The present invention has the beneficial effect of substantially improving the bandwidth utilization efficiency of the synchronous dynamic memory of route switching equipment at a lower hardware cost on the basis of the prior intellectual property (IP) cores.

Description

technical field [0001] The invention relates to the technical field of memory, in particular to a method, device and system for synchronous dynamic memory read and write control. Background technique [0002] With the development of network technology, the increase in the bandwidth of routing and switching equipment makes the demand for data dynamic cache capacity more and more large, so the cost, capacity, speed and storage bandwidth of the memory have become issues that have to be considered comprehensively. Constrained by cost and capacity, it is impractical to use the fastest memory to alleviate the shortage of cache capacity. [0003] At present, the industry generally regards synchronous dynamic memory as the first choice for data caching. In routing and switching equipment, the data packet is usually divided into multiple data slices according to certain rules and written into the internal bank of the synchronous dynamic memory. When the data packet is output, multip...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/16
CPCG06F13/16G06F13/1668G06F2213/0038G11C7/22
Inventor 陈红旗周昶
Owner ZTE CORP
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