Divider and realization method thereof

A technology of a divider and an adder, applied in the field of digital signal processing circuits, can solve the problems of large hardware resource occupation, difficult porting of dividers, long operation time, etc. Effect

Inactive Publication Date: 2012-01-11
SHENZHEN STATE MICROELECTRONICS CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0008] In view of the above problems, the present invention proposes a divider implemented in a microprocessor or an ASIC and an implementation method thereof to solve the pr

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  • Divider and realization method thereof
  • Divider and realization method thereof
  • Divider and realization method thereof

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Embodiment Construction

[0049] like figure 1 As shown, the fast 32-bit integer divider proposed by the present invention includes: the dividend register 11 for storing the dividend A; the divisor register 12 for storing the divisor B; the intermediate result register 13 for storing the intermediate result P; Processing unit 14; Three-way parallel adder array 15; Judgment unit 16 for sign processing / quotient judgment / partial remainder judgment; Selection unit 17 for quotient selection / partial remainder selection; Comparator 18, by dividing the dividend Compare with the sign of the divisor to determine whether the comparison operation of the next iterative quotient process is addition or subtraction. If the two signs are the same, the subtraction operation will be performed. If the two signs are different, the addition operation will be performed.

[0050] Wherein, after the division operation ends, the obtained quotient will be stored in the dividend register 11 .

[0051] combine figure 2 Shown, t...

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Abstract

The invention discloses a divider and a realization method thereof. The divider comprises a dividend register, a divisor register, an intermediate result register, a data pre-processing unit, a comparator, a three-path parallel adder array, a determining unit and a selecting unit; the three-path parallel adder array is used for carrying out iterative operation of respectively adding or subtracting a two-digit dividend which is shifted into the intermediate result register and a one-time divisor, a two-time divisor and a three-time divisor in the data pre-processing unit, so as to respectively generate three two-digit quotients and three remainders; and the selecting unit is used for determining the two-digit quotients in an operation cycle and some corresponding remainders when judging the symbols of the three remainders being consistent with the symbol of the dividend, and shifting some corresponding remainders which are calculated from the lowest two digits of the two-digit quotient dividend register leftwards for two digits into the intermediate result register. The invention is suitable to be realized in a microprocessor or an ASIC (application specific integrated circuit), and has stronger universality; and because the number of used devices is smaller, the operation efficiency is high.

Description

technical field [0001] The invention relates to a digital signal processing circuit, in particular to a divider capable of rapidly processing any 32-bit signed or unsigned integer division operation realized by a microprocessor or an ASIC and its realization method. Background technique [0002] Among the various operations of digital processing, division is the most complex algorithm implementation and the largest hardware overhead operation, but it is also the part with the most mining potential for high-performance computing. [0003] In digital signal processing, division operations are often involved, such as the calculation of the normalized minimum mean square error. However, there is no chip that realizes the division function in the existing chips, and there is no synthesizable division statement in the high-level hardware description language, such as the design software package provided by Synopsy (SYNOPSY). [0004] The traditional division algorithm only produc...

Claims

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Application Information

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IPC IPC(8): G06F7/535
Inventor 刘燚
Owner SHENZHEN STATE MICROELECTRONICS CO LTD
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