Multiplexed Amplifier with Glitch Reduction

A multiplexer and multiplexing technology, applied to DC coupled DC amplifiers, differential amplifiers, circuits, etc., can solve problems such as power consumption

Active Publication Date: 2016-01-06
TEXAS INSTR INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Specifically, the residual amplifier 116 for each stage 102-1 through 102-N operates at a duty cycle of less than 50%, which consumes excess power

Method used

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  • Multiplexed Amplifier with Glitch Reduction
  • Multiplexed Amplifier with Glitch Reduction
  • Multiplexed Amplifier with Glitch Reduction

Examples

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Embodiment Construction

[0020] Figure 2A An example ADC 200 is shown in accordance with the principles of the invention. ADC200 has the same general functions as ADC100. However, there are differences in the pipeline; namely, stages 102-1 to 102-N are replaced by stages 202-1 to 202-N.

[0021] exist Figure 2B , stages 202-1 through 203-N (hereinafter referred to as 202) can be seen in more detail. In operation, T / H circuits 203-1 and 203-2 are coupled to receive an analog input signal IN (which is either an analog input signal AIN or a residual signal from a previous stage). Since these T / H circuits 203-1 and 203-2 are arranged in parallel with each other, the timing of the T / H circuits 203-1 and 203-2 can be designed such that at substantially non-overlapping logic stages or phases of the clock signals Take a sample. T / H circuits 203-1 and 203-2 are coupled to ADCs 204-1 and 204-2, respectively, and ADCs 204-1 and 204-2, DACs 206-1 and 206-2, adders 208-1 and 208-2, and residual Difference a...

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Abstract

The first multiplexer (216-1) is coupled to the first input (INP1 / INP2) of the folded cascode differential amplifier (210), and the second multiplexer (216-2) is coupled To its second input (INM1 / INM2), the differential amplifier (210) includes transistors (Q1 to Q4) and current sources (222-228). Switching between the differential input signals (INP1 / INM1) and (INP2 / INM2) is controlled by a selection signal SELECT provided by the controller (214). The reset mechanism includes a switch (Q5) coupled between the outputs (OUTP, OUTM) of the amplifier (210) and controlled by a pulse generator (XOR gate 218 and delay circuit 220). On the rising or falling edge of the select signal SELECT, a pulse is provided to activate the switch (Q5) to briefly short the outputs (OUTP, OUTM). This avoids glitches and results in faster settling times.

Description

technical field [0001] The present invention relates generally to amplifiers, and more particularly to residual amplifiers. Background technique [0002] Referring to FIG. 1A of the drawings, reference numeral 100 generally designates a conventional analog-to-digital converter (ADC) 100 . ADC 100 generally includes several stages 102 - 1 through 102 -N, ADC 106 (which is typically a blinker ADC), and digital output circuit 104 . Stages 102-1 through 102-N are typically coupled in series with each other in a sequence wherein a first stage 102-1 receives an analog input signal, and wherein each of subsequent stages 102-2 through 102-N receives an analog input signal from a previous Residual signals of stages 102-1 to 102-(N-1). ADC 106 is coupled to the final stage 102-N (receives its residual signal). Based on their input signal (residual signal or analog input signal), stages 102 - 1 to 102 -N and ADC 106 are able to resolve a portion of the analog input signal, which is ...

Claims

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Application Information

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Patent Type & AuthorityPatents(China)
IPC IPC(8): H03F3/45H03K17/62H03M1/12
CPCH03M1/0872H03M1/1215H03M1/1225H03M1/164H03M1/44
InventorR·F·佩恩
OwnerTEXAS INSTR INC