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Equipment exception handling method and device

A technology of equipment exception and processing method, which is applied in the field of equipment exception processing method and device, can solve problems such as processing time difference, address exception, trigger exception, etc., and achieve the effect of improving stability and reducing abnormal crash of equipment

Active Publication Date: 2013-09-18
XINHUASAN INFORMATION TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

When a device, such as a multi-core router, uses a Linux system based on a MIPS central processing unit (CPU, Central Processing Unit), when the CPU of the router accesses certain addresses, for example, there is no corresponding Peripheral Component Interconnection (PCI, Peripheral Component Interconnection) card When a certain section of PCI address space is used, an address exception will be triggered, causing the system to crash and restart.
Among them, the address that causes the system to crash and restart may be a legal address and can be accessed normally, but it becomes an illegal address after some operations. As a result, the CPU will still access the PCI address space in the future, thus triggering an exception
[0003] Generally, the CPU of the router can handle the event that the PCI card on the multi-core router is pulled out, so that the PCI address space is no longer accessed, but due to the existence of processing time difference, some special modules, such as timers, will still Access, which will eventually be prohibited, but the resulting system crash is unnecessary

Method used

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  • Equipment exception handling method and device
  • Equipment exception handling method and device
  • Equipment exception handling method and device

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Embodiment Construction

[0029] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0030] figure 1 The flow chart of the device exception handling method provided by the embodiment of the present invention, such as figure 1 The specific steps are as follows:

[0031] Step 101: The device finds that it has generated an abnormal event, wherein the abnormal event carries an abnormal cause and an instruction code that triggers the abnormal event.

[0032] Step 102: The device judges whether the cause of the abnormality is access to an illegal address, if so, execute step 103; otherwise, execute step 106.

[0033] Step 103: The device obtains the real instruction that triggers the abnormal event, and judges whether the instruction is a read / write instruction, and if so, executes step 104; otherwise, executes step 106.

[0034] Step 104: The device obtains the address triggering the abnormal event from the read and write...

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Abstract

The invention provides an equipment exception handling method and a device. The method comprises the steps that equipment has an exceptional event which carries an exceptional reason and an instruction code triggering the exceptional event; the equipment judges whether the exceptional reason is illegal address visiting; a true instruction triggering the exceptional event is acquired if so; whether the instruction is a read-write instruction is judged; an address triggering the exceptional event is acquired from the instruction if so; whether the address is a legal address configured by a system is judged; the next instruction in an internal memory is processed continuously if so; and the exception handling is performed if not. The method and the device can reduce abnormal crash of the equipment.

Description

technical field [0001] The invention relates to the technical field of system abnormality processing, in particular to a method and device for processing abnormality of equipment. Background technique [0002] Microprocessor without Interlocked Piped Stages (MIPS, Microprocessor without Interlocked Piped Stages) architecture is a processor architecture that adopts Reduced Instruction Set Computing (RISC, Reduced Instruction Set Computing). When a device, such as a multi-core router, uses a Linux system based on a MIPS central processing unit (CPU, Central Processing Unit), when the CPU of the router accesses certain addresses, for example, there is no corresponding Peripheral Component Interconnection (PCI, Peripheral Component Interconnection) card When a certain section of PCI address space is used, an address exception will be triggered and the system will crash and restart. Among them, the address that causes the system to crash and restart may be a legal address and ca...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/07
Inventor 王厚雪吴斌
Owner XINHUASAN INFORMATION TECH CO LTD