Harq data caching device and method

Abstract

Disclosed is an HARQ data caching device. A collection module collects decoded data and transmits same, and a de-2nd rate matching module receives data transmitted from the collection module, subjects the received data to de-2nd rate matching and then writes same into an HARQ cache module in a time division manner, or reads data stored in the HARQ cache module in a time division manner, combines same with the data subjected to the de-2nd rate matching, and then writes same into the HARQ cache module; the HARQ cache module adopts a plurality of RAMs, and stores data transmitted from the de-2nd rate matching module in a time division manner; and a de-1st rate matching module reads data stored in the HARQ cache module in a time division manner, and performs de-1st rate matching on the data. At the same time, also disclosed is an HARQ data caching method. RAMs of the embodiments of the present invention all adopt a single-port RAM, which reduces the data stream delay, and simplifies the read-write operation control logic, under the premise of ensuring that the HARQ data stream is uninterrupted.

Description

technical field [0001] The present invention relates to a hybrid automatic repeat request (HARQ, Hybrid Automatic Repeat Request) data caching technology, in particular to a HARQ data caching device and method. Background technique [0002] High Speed ​​Downlink Packet Access (HSDPA, High Speed ​​Downlink Packet Access) is a mobile communication protocol that provides packet data services for the downlink of Time Division Synchronous Code Division Multiple Access (TD-SCDMA) Make the downlink transmission rate reach 8-10 megabits per second (Mbps, Million bits per second). The main technologies used in the HSDPA system include: adaptive modulation and coding AMC (Adaptive Modulation and Coding), HARQ, multiple-input multiple-output MIMO (Multiple-Input Multiple-Output), fast scheduling, fast cell selection and other technologies. [0003] The HARQ mechanism is a combination of a Forward Error Correction (FEC, Forward Error Correction) technology and an Automatic Repeat Reque...

AI Technical Summary

Problems solved by technology

[0005] As can be seen from the above description, it is necessary to write and decode correct data and merged data to the cache module, and also need to read the historical data and merged data stored in the cache module, that is to say, it is necessary to write to the cache module And read operation, adopt single-port random access memory (RAM, RandomAccess Memory) as cache module in the above-mentioned scheme, and set RAM to be 48 bits width, each data is 6 bits width; Then when writing data, need 8 The parallel data can only be written into the single-port RAM after parallel-to-serial conversion to form a 48-bit wide data; when reading data, it is necessary to perform serial-to-parallel conversion on the 8 data stored in series and then output to the rate matching unit once ; Obviously, because only one single-port RAM is used to control the read and write operations of data, the control logic is more complicated; at the same time, because the data needs to be converted between parallel and serial, the data processing time of the HARQ storage unit is extended

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