Low delay writing priority decoding circuit

Abstract

To eliminate writing conflict with two or more writing openings, the invention provides a low delay writing priority decoding circuit. The decoding circuit is provided with two or more writing line input signals and two or more writing line output signals with priority; all the writing line input signals and writing line output signals are efficient; the given writing line input signals have priority sequence from high to low and each writing line input signal corresponds to one writing opening; when two or more writing line input signals are 1 simultaneously, only the writing opening corresponding to the writing line input signal with the highest priority executes writing operation on the current line register and other writing line input signals with low priority are shielded. The writing operation is sequenced according to the given writing priority sequence, at most one signal output by a decoder is 1, and writing conflict is eliminated. Meanwhile, the decoding circuit has the advantages of low delay and capability of saving area.

Description

technical field [0001] The invention belongs to the field of digital circuit design, in particular to a realization method of a multi-port register file writing and decoding circuit. Background technique [0002] Decoding is to convert the binary code into a specific One-Hot signal. The decoding circuit can translate various states of the input binary code into corresponding output signals according to its original meaning. The logic circuit that converts the input binary code into a specific high (low) level signal output is called a decoder. [0003] The register file is a high-speed storage unit inside the central processing unit (CPU, Central Processing Unit). It is a special static random access memory (SRAM, Static Random Access Memory), which has the advantages of large number of ports, fast speed, and small area. The register file is the core component of the data path of the CPU core, providing source operands and saving operation results for functional components ...

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