Data parallel interleaving method, terminal equipment and computer storage medium

Abstract

The invention discloses a data parallel interleaving method, terminal equipment and a computer storage medium. The method comprises the following steps: determining ROM1 for storing an RAM write address, ROM2 for storing an RAM read enable pattern and data parallel information corresponding to a processing unit through configuration information; in data writing, storing each bit of data in to-be-input data of which the maximum input parallelism degree is n into different RAMs in the same clock period; during storage, using the maximum output parallelism degree k as a basic storage unit and thus reading out each group of to-be-output data in sequence according to the head address of the ROM2 during reading; and finally, extracting effective data of OV bits from each group of to-be-output data according to the output parallelism degree OV required by the to-be-output data to finish data parallel interleaving. According to the method, different input parallelism degrees, output parallelism degrees and interleaved output parallelism degrees under various configurations can be compatible, the flexibility is improved, the data processing rate can be effectively increased, and the sendingdelay is reduced.

Description

technical field [0001] The present invention relates to the technical field of wireless communication, in particular to a data parallel interleaving method, terminal equipment and computer storage medium. Background technique [0002] In the field of wireless communication, after the information passes through the channel, there will be a continuous long-term bit error state, resulting in demodulation errors. In order to reduce the probability of errors, it is necessary to split the continuous long-segment errors into intermittent short-segment errors, so that these intermittent short-segment errors can be recovered during signal demodulation. Interleaving is a method of adjusting the data position without changing the data content, preventing the impact of continuous bit errors on demodulation, and solving the above problems. The rule generally followed by interleaving is: change adjacent bits into non-adjacent bits, and adjacent bits alternately appear in the upper and lo...

AI Technical Summary

Problems solved by technology

In order to realize the above scheme, the number of RAMs consistent with the modulation order needs to be used, and the data of all RAMs needs to be combined when outputting, which is not very flexible.

Moreover, due to the cumbersome process of the above-mentioned parallel interleaving method, the interleaving efficiency is not high in actual operation, and it cannot be compatible with different input parallelism, output parallelism and interleaving output parallelism under multiple configurations.

Images