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Storage device, CPLD device, reset method of storage device and storage medium

A technology of a storage device and a reset method, applied in the fields of storage devices and storage media, can solve problems such as complex operations and achieve the effect of reducing bandwidth

Active Publication Date: 2021-12-28
SUZHOU LANGCHAO INTELLIGENT TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

At present, the most commonly used methods to solve the problem of bandwidth reduction are BIOS (Basic Input Output System, basic input and output system) solution, PCIE driver solution, and CPU manufacturers modify their own CPU internal firmware. However, these solutions are more complicated to operate.

Method used

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  • Storage device, CPLD device, reset method of storage device and storage medium
  • Storage device, CPLD device, reset method of storage device and storage medium
  • Storage device, CPLD device, reset method of storage device and storage medium

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Embodiment Construction

[0036] In order to make the purpose, technical solutions and advantages of the present application more clearly understood, the present application will be described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, but not to limit the present application.

[0037] In one embodiment, as figure 1 shown, figure 1 A block diagram showing the structure of the storage device in one embodiment, figure 1 The storage device includes a storage motherboard, the storage motherboard is provided with a CPU, a CPLD device and a PCIE device, the input pin of the CPLD device is connected with the signal output pin of the CPU, and the output pin of the CPLD device is connected with the signal of the PCIE device. Input pin connections where:

[0038] The above CPLD device is used to collect the de-reset signal of the CPU, collect the edg...

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Abstract

The invention relates to a storage device, a CPLD device, a reset method of the storage device and a storage medium. The method comprises the steps that a storage mainboard is provided with a CPU, a CPLD device and a PCIE device, an input pin of the CPLD device is connected with a signal output pin of the CPU, an output pin of the CPLD device is connected with a signal input pin of the PCIE device, the CPLD device is used for collecting a reset removing signal of the CPU and collecting an edge signal in the reset removing signal at a specified clock rate, and after a preset time is delayed, reset operation is carried out on PCIE equipment according to the edge signal. According to the method, the CPLD device is connected with the CPU and the PCIE device, the CPLD device collects the reset solving signal of the CPU, the edge signal in the reset solving signal is collected at the specified clock rate, and after the preset time is delayed, the reset operation is executed on the PCIE device according to the edge signal, so that the problem of bandwidth reduction of the storage device can be simply and conveniently solved.

Description

technical field [0001] The present application relates to the technical field of electronic circuits, and in particular, to a storage device, a CPLD device, a reset method for a storage device, and a storage medium. Background technique [0002] In current server products, the PCIE (peripheral component interconnect express, high-speed serial computer expansion bus standard) technology is used as the PCIE control signal of the network and the hard disk, and the PCIE signal directly comes from the pins of the CPU (central processing unit, central processing unit). In actual use, due to problems such as CPU defects, bandwidth reduction may occur between the host on the CPU side and the device connected to the downlink port. For example, the X8 bandwidth is configured, but the X1 bandwidth is actually successfully negotiated. At present, the most common methods to solve the problem of bandwidth reduction are BIOS (Basic Input Output System), PCIE driver, and CPU manufacturers m...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F1/24
CPCG06F1/24Y02D10/00
Inventor 周加洋
Owner SUZHOU LANGCHAO INTELLIGENT TECH CO LTD
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