Trimming circuit and integrated circuit

Abstract

The invention provides a trimming circuit and an integrated circuit, and the trimming circuit comprises: a band-gap reference module which is used for generating an internal reference voltage; a voltage buffer module, wherein the input end of the voltage buffer module is connected with the output end of the band-gap reference module; a comparator module, wherein the positive input end and the negative input end of the comparator module are respectively connected with the output end of the voltage buffer module and input external standard voltage; a logic trimming module which is connected with an oscillator used for generating a test signal, wherein the oscillator is connected with a trigger test signal, the output end of the comparator module and the voltage buffer module are connected with the logic trimming module, and the logic trimming module is used for judging whether the current output voltage of the voltage buffer module is the target reference voltage according to the output result of the comparator module, and outputting a trimming control signal according to the judgment result so as to control the voltage buffer module to automatically adjust the current output voltage. The problem that the trimming mode of an existing integrated circuit can reduce the yield of finished products is solved.

Description

technical field [0001] The present application relates to the technical field of integrated circuits, in particular to a trimming circuit and an integrated circuit. Background technique [0002] In the production of integrated circuits, there is usually a problem of inter-chip deviation. In order to ensure the product yield, it is necessary to test and adjust the chip. At present, a mid-test machine is needed in the finished product test, and it takes time to scan and test the positive IC, calculate the trimming value, and burn out the perfusion signal. This test and trimming method can only be performed before the product is ready. It not only takes up mid-test resources, prolongs the testing and adjustment time, and increases the cost of the chip, but also the package after product adjustment may be affected by the packaging stress, resulting in deviation of the adjusted chip parameters. Thereby reducing the yield of finished products. Contents of the invention [0003...

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