Timing sequence optimization method, system and device after layout and wiring, and storage medium

A technology of layout and routing and optimization methods, applied in computer-aided design, special data processing applications, instruments, etc., can solve problems such as differences in the influence of routing paths and inability of path timing to meet requirements, so as to achieve a clear optimization effect, improve timing, increase The effect of stability

Pending Publication Date: 2022-03-11
SHENZHEN PANGO MICROSYST CO LTD
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Problems solved by technology

[0004] Based on this, the present invention provides a timing optimization method after layout and wiring, which solves the problem that the timing of the path cannot meet the requirements due to the difference in the degree of influence of timing and congestion on the routing path in the late stage of optimization.

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  • Timing sequence optimization method, system and device after layout and wiring, and storage medium
  • Timing sequence optimization method, system and device after layout and wiring, and storage medium
  • Timing sequence optimization method, system and device after layout and wiring, and storage medium

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Embodiment Construction

[0047] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0048] The terms "first", "second", and "third" in this application are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, features defined as "first", "second", and "third" may explicitly or implicitly include at least one of these features. In the description of the present application, "plurality" means at least ...

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Abstract

The invention discloses a time sequence optimization method after layout and wiring. The method comprises the following steps: storing a current wiring result; searching a to-be-optimized net of a wiring result; setting a forbidden special node in a wiring result; searching a new path for the load to be optimized; searching points occupied by other nets on the new path, marking the points as conflict points, and removing all conflicting nets; collecting the net with the incomplete solution path, searching a legal solution path for the net with the incomplete solution path, and preferentially searching for the net with the poor time sequence; and re-wiring. The problem that the optimal solution of the key path is occupied by other paths is solved, the time sequence of the key path is improved, and the stability of layout and wiring is improved. The invention also discloses a time sequence optimization system and device after layout and wiring, and a storage medium, which have the above beneficial effects.

Description

technical field [0001] The invention relates to the field of field programmable gate array (Field Programmable Gate Array) integrated circuit software tool design field, in particular to a timing optimization method, system, device and storage medium after layout and wiring. Background technique [0002] At present, there is no definite timing optimization method after placement and routing, and most of the changes after placement and routing results are tentative and uncertain modifications that will have positive effects. At the same time, timing optimization based on placement and routing results has many difficulties, for example, it is difficult to find a new feasible solution after disturbance, and it is uncertain that the timing result of the searched feasible solution is better than the previous one. [0003] When the existing routing method considers timing and congestion at the same time, when there are many iterations, the congestion factor usually overwhelms the ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/347
CPCG06F30/347
Inventor 李思源雷洋张鑫夏炜
Owner SHENZHEN PANGO MICROSYST CO LTD
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