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DRAM-NVM hybrid memory predictor based on dynamic access

A DRAM-NVM and hybrid memory technology, applied in memory systems, memory address/allocation/relocation, instruments, etc., can solve problems affecting memory access performance, improve access performance, reduce time and space costs, and solve access problems delayed effect

Pending Publication Date: 2022-07-01
CHONGQING UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] In the hierarchical architecture of the hybrid memory system, the serial access mode and the parallel access mode have their own advantages and disadvantages. Therefore, using any one access mode alone will seriously affect the memory access performance.

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  • DRAM-NVM hybrid memory predictor based on dynamic access
  • DRAM-NVM hybrid memory predictor based on dynamic access
  • DRAM-NVM hybrid memory predictor based on dynamic access

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Embodiment Construction

[0039] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0040] In a first aspect, an embodiment of the present invention provides a DRAM-NVM hybrid memory predictor based on dynamic access, see figure 1 , is a schematic structural diagram of a DRAM-NVM hybrid memory predictor based on dynamic access provided by an embodiment of the present invention. The predictor 2 is located between the last level cache 1 and the DRAM cache 3, and includes: a prediction module 21 and an adaptive update ...

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Abstract

The invention provides a DRAM-NVM (Dynamic Random Access Memory-Non-Volatile Memory) hybrid memory predictor based on dynamic access. The DRAM-NVM hybrid memory predictor comprises a prediction module and a self-adaptive updating module, the prediction module is used for mapping a memory address of the memory access request to the filter unit; the self-adaptive updating module is used for replaying the historical access information when the memory access behavior changes to obtain a latest updating rule so as to update the prediction state value according to the latest updating rule; and the prediction module is also used for predicting the hit state of the DRAM cache according to the prediction state value in the filter unit. By adopting the embodiment of the invention, accurate prediction is carried out at extremely low time and space cost, the change of the memory access behavior is dynamically adapted, and the prediction precision of future prediction is improved. Besides, by adapting to different access behaviors and dynamically selecting a serial access mode or a parallel access mode, the problem of access delay in the hierarchical hybrid storage system is effectively solved, so that the access performance of the whole memory is improved.

Description

technical field [0001] The present invention relates to the technical field of memory access, in particular to a DRAM-NVM hybrid memory predictor based on dynamic access. Background technique [0002] At present, DRAM (Dynamic Random Access Memory, dynamic random access memory) and NVM (Non-Volatile Memory, non-volatile memory) are being considered to combine to build a DRAM-NVM hybrid memory system to provide the same large memory capacity as NVM And high memory access speed comparable to DRAM. Among them, the hierarchical architecture is one of the most representative architectures of hybrid DRAM-NVM memory. It uses NVM as the main memory and caches NVM content through DRAM. In this architecture, DRAM and NVM usually work in serial access mode. The advantage of serial access mode is that it provides very fast data access on DRAM hits. However, when a DRAM miss occurs, accessing both DRAM and NVM at the same time results in longer access latency, preventing comparable pe...

Claims

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Application Information

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IPC IPC(8): G06F12/06G06F12/02G06F12/0802G06F12/0884G06F12/0897G06F3/06
CPCG06F12/0623G06F12/0238G06F12/0802G06F12/0884G06F12/0897G06F3/068G06F3/061G06F3/0616
Inventor 谭玉娟陈伟肖丹晏志超刘铎
Owner CHONGQING UNIV