Communication method, device and equipment for SPI (Serial Peripheral Interface) bus and storage medium

Abstract

The invention discloses a communication method, device and equipment for an SPI bus and a storage medium, and the method comprises the steps: carrying out the CRC operation of target data of a data package, and obtaining a first verification value; starting SPI communication, and sequentially sending each byte data in the target data to the FPGA, so that the FPGA performs CRC operation again on the received current byte data and a second check value obtained by performing CRC operation on the received previous byte data to update the second check value; after the target data is sent, receiving a second verification value updated by the FPGA, and judging whether the first verification value is consistent with the updated second verification value or not; if yes, determining that the target data received by the FPGA is valid; and if not, restarting the operation of SPI communication until the target data received by the FPGA is judged to be valid. According to the communication method, whether writing succeeds or not can be known only through one communication process, and then efficient and reliable communication can be achieved.

Description

technical field [0001] The present invention relates to the field of communication technologies, and in particular, to a communication method, apparatus, device and storage medium for an SPI bus. Background technique [0002] A Microcontroller Unit (MCU) and a Field Programmable Gate Array (FPGA) communicate through a Serial Peripheral Interface (SPI) bus, the MCU acts as a communication master, and the FPGA acts as a communication slave. When the MCU reads data through the SPI bus, it does not know whether the read data is correct or has errors; when the MCU writes data through the SPI bus, it does not know whether the FPGA of the opposite end has received the correct data, and the FPGA of the opposite end does not know whether it has received the correct data. Whether the data is correct, which leads to unreliable communication. [0003] At present, in order to solve the above problems, the existing method is to add a Cyclic Redundancy Check (Cyclic Redundancy Check, CRC)...

AI Technical Summary

Problems solved by technology

When writing data, the MCU first calculates the CRC_MCU of the data sent this time and appends it to the data. After the FPGA receives it, it calculates the CRC_FPGA of the received data. If the CRC_MCU and CRC_FPGA are equal, the data received by the FPGA is correct; However, at this time, the MCU does not know whether the FPGA has received the data normally, so the MCU needs to start the data reading process to read the data back. If the read value is equal to the written value, then the data writing is successful, otherwise the data writing fails. Start the process of writing data again, for example: MCU wants to write register 0x12 as 0xaabbccdd, then, even if MCU adds CRC to the data, after sending, you need to read whether register 0x12 is 0xaabbccdd to know whether the last write data was successful or failed , that is to go through a "write data, read back data" that is, the second communication, this method is inefficient

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