Network-on-chip congestion control method, system and device and storage medium

A congestion control, network-on-chip technology, applied in the computer field, can solve problems such as blanks, and achieve the effect of high transmission efficiency
CN114866475APending Publication Date: 2022-08-05SUN YAT SEN UNIV
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Patent Information

Authority / Receiving Office
CN Β· China
Current Assignee / Owner
SUN YAT SEN UNIV
Publication Date
2022-08-05

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Abstract

The invention discloses a network-on-chip congestion control method, system and device and a storage medium. The network-on-chip congestion control method comprises the following steps: S101, recording a first bandwidth and a first congestion amount of a routing node; s102, according to the first congestion amount, determining whether the second congestion amount is greater than or equal to a first threshold; if yes, performing congestion control on the routing node through first processing, and returning to S102; and if not, returning to the step S101. According to the invention, the congestion monitoring of each routing node in the network-on-chip is realized by recording the first bandwidth and the first congestion amount of each routing node in real time and judging whether the network congestion occurs in the routing node; according to the invention, the data flow control is carried out on the routing nodes with network congestion, so that the congestion control is realized, each routing node has higher transmission efficiency, the throughput rate of the network-on-chip is improved, the transmission delay is reduced, and the transmission performance of the network-on-chip is maintained near the optimal performance.
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Description

technical field

[0001] The present application relates to the field of computer technology, and in particular, to a method, system, device, and storage medium for controlling network-on-chip congestion. Background technique

[0002] With the increasing integration scale of SoCs, processors have also developed from single-core to multi-core and many-core. Compared with the traditional bus architecture, Network-on-Chip (NoC) can provide higher throughput in highly integrated scenarios, and has been more and more widely used in multi-core processors.

[0003] Because on-chip resources are very limited, and a large amount of data transmission is often localized, in practical application scenarios, on-chip network load imbalance is likely to occur, that is, network congestion. From a performance point of view, network congestion will lead to a decrease in throughput and an increase in transmission delay. However, application scenarios with higher throughput requirements are mor...

Claims

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