Monolithic integrated diode amplitude limiting unit based on quasi-vertical MPS and preparation method

Abstract

The invention discloses a monolithic integrated diode amplitude limiting unit based on quasi-vertical MPSs and a preparation method thereof. The amplitude limiting unit comprises two silicon-based GaN quasi-vertical MPSs located on a silicon substrate, and a forward amplitude limiting diode and a reverse amplitude limiting diode are formed; the passivation layer covers the two MPSs and the silicon substrate; the thin film protection resistor is located in the passivation layer; the first interconnection metal connects the first end of the resistor with the cathode of the reverse amplitude limiting diode; the second interconnection metal forms a voltage input end, a voltage output end, a first reference voltage end and a second reference voltage end, the cathode of the forward amplitude limiting diode is connected with the first reference voltage end, and the anode of the forward amplitude limiting diode, the cathode of the reverse amplitude limiting diode and the first end of the thin film protection resistor are connected with the voltage output end. And the anode of the reverse amplitude limiting diode is connected with a second reference voltage end, and the second end of the resistor is connected with the voltage input end 1. The diode amplitude limiting unit provided by the invention has relatively high voltage resistance and can be applied to a high-power condition.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuits, and in particular relates to a monolithic integrated diode limiting unit based on a quasi-vertical MPS (Merged PIN Schottky, mixed PIN / Schottky diode) and a preparation method thereof. Background Art

[0002] Diode clipping units are commonly used in radio frequency systems and power electronic systems. Most power devices use high-power silicon single tubes in the form of discrete devices for diode clipping units. However, with the increasing requirements for the power handling capacity, miniaturization and reliability of rectifier systems, the existing board-level integrated diode clipping units will become increasingly difficult to adapt to the needs of the times.

[0003] Existing diode clipping units mainly use Si-based devices, which have low device power density and are difficult to miniaturize under high-power conditions. As the efficiency, power density, and device volume requirements of power processing equipment become higher and higher, Si-based devices are rapidly approaching the theoretical limits of their intrinsic material properties. In addition, the voltage application range of existing small-sized diode clipping units is relatively narrow, and the withstand voltage of the core device diode is relatively low.

[0004] Therefore, there is an urgent need for a diode limiting unit with higher voltage resistance and capable of being applied to high-power conditions. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a monolithic integrated diode clipping unit based on quasi-vertical MPS.

[0006] The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0007] A monolithic integrated diode clipping unit based on quasi-vertical MPS, comprising:

[0008] Silicon substrate;

[0009] Two silicon-based GaN quasi-vertical MPSs are located on a silicon substrate; the two silicon-based GaN quasi-vertical MPSs respectively form a forward limiting diode and a reverse limiting diode;

[0010] Passivation layer; the passivation layer covers the two silicon-based GaN quasi-vertical MPSs and the silicon substrate;

[0011] A thin film protection resistor; the thin film protection resistor is located inside the passivation layer;

[0012] A first interconnection metal; the first interconnection metal is used to connect the first end of the thin film protection resistor to the cathode of the reverse limiting diode;

[0013] The second interconnecting metal is used to form the voltage input terminal, the voltage output terminal, the first reference voltage terminal and the second reference voltage terminal of the monolithic integrated diode limiting unit, and is also used to connect the cathode of the forward limiting diode to the first reference voltage terminal, connect the anode of the forward limiting diode, the cathode of the reverse limiting diode, and the first end of the thin film protection resistor to the voltage output terminal, connect the anode of the reverse limiting diode to the second reference voltage terminal, and connect the second end of the thin film protection resistor to the voltage input terminal.

[0014] Optionally, the silicon-based GaN quasi-vertical MPS comprises: a silicon substrate, a GaN conducting layer, a GaN diffusion layer, one or more Mg-doped P-type BN field limiting rings, a cathode ohmic metal and an anode Schottky metal;

[0015] The GaN conductive layer is superimposed on the silicon substrate, and the GaN diffusion layer is superimposed on the middle area of ​​the upper surface of the GaN conductive layer; one or more annular grooves are provided on the top layer of the GaN diffusion layer; a plurality of the annular grooves are concentrically arranged; Mg-doped P-type BN material is deposited in the annular groove to form the Mg-doped P-type BN field limiting ring; the anode Schottky metal is located on the upper surface of the GaN diffusion layer and is in contact with the one or more Mg-doped P-type BN field limiting rings; the cathode ohmic metal is located on the upper surface of the GaN conductive layer that is not covered by the GaN diffusion layer, and surrounds the GaN diffusion layer.

[0016] Optionally, the Mg doping concentration of the Mg doped P-type BN field limiting ring is 1.7×10 16 cm -3 ~3.0×10 17 cm -3 .

[0017] Optionally, the Mg-doped P-type BN field limiting ring has a width of 2 μm to 4 μm and a depth of 0.5 μm to 4 μm.

[0018] Optionally, when a plurality of annular grooves are provided, a distance between adjacent annular grooves is 1 μm to 2.5 μm.

[0019] Optionally, the Si doping concentration of the GaN diffusion layer is 1.8×10 16 cm -3 ~5.0×10 17 cm -3 .

[0020] Optionally, the Si doping concentration of the GaN conducting layer is 1.0×10 18 cm -3 ~1.0×10 20 cm -3 .

[0021] The present invention also provides a method for preparing a monolithic integrated diode limiting unit based on quasi-vertical MPS, comprising:

[0022] Prepare two silicon-based GaN quasi-vertical structures on a silicon substrate; the two silicon-based GaN quasi-vertical structures are used to subsequently form two silicon-based GaN quasi-vertical MPSs;

[0023] Depositing a first passivation layer on the surface of the current device, and opening the passivation layer to expose an anode region and a cathode region; the anode region corresponds to the anode of the silicon-based GaN quasi-vertical MPS; the cathode region corresponds to the cathode of the silicon-based GaN quasi-vertical MPS;

[0024] An anode Schottky metal is deposited in the anode region, and a cathode ohmic metal is deposited in the cathode region, so that the two silicon-based GaN quasi-vertical structures form two silicon-based GaN quasi-vertical MPSs, and a thin film protection resistor is deposited on the surface of the current passivation layer; wherein the two silicon-based GaN quasi-vertical MPSs serve as a forward limiting diode and a reverse limiting diode respectively;

[0025] Depositing a second passivation layer on the surface of the current device, and opening the passivation layer to expose the anode and cathode of the forward limiting diode, the anode and cathode of the reverse limiting diode, and the first end and the second end of the thin film protection resistor;

[0026] Preparing a first interconnect metal on the current device to connect a first end of the thin film protection resistor to a cathode of the reverse limiting diode;

[0027] Depositing a third passivation layer on the surface of the current device, and opening the passivation layer to expose the anode and cathode of the forward limiting diode, the anode and cathode of the reverse limiting diode, and the second end of the thin film protection resistor;

[0028] A second interconnect metal is prepared on the current device to form a voltage input terminal, a voltage output terminal, a first reference voltage terminal and a second reference voltage terminal of the monolithic integrated diode limiting unit, and the cathode of the forward limiting diode is connected to the first reference voltage terminal, the anode of the forward limiting diode, the cathode of the reverse limiting diode, and the first end of the thin film protection resistor are connected to the voltage output terminal, the anode of the reverse limiting diode is connected to the second reference voltage terminal, and the second end of the thin film protection resistor is connected to the voltage input terminal.

[0029] Optionally, two silicon-based GaN quasi-vertical structures are prepared on a silicon substrate, including:

[0030] Epitaxially growing a GaN conduction layer and a GaN diffusion layer on a silicon substrate in sequence, performing mesa etching on the GaN diffusion layer, and performing device isolation etching on the etched GaN diffusion layer and the GaN conduction layer to form two silicon-based gallium nitride substrates; in the silicon-based gallium nitride substrate, the GaN diffusion layer is superimposed on the middle region of the GaN conduction layer;

[0031] Etching one or more annular grooves on the top layers of the GaN diffusion layers of the two silicon-based gallium nitride substrates respectively; wherein the plurality of annular grooves are concentrically arranged;

[0032] Depositing Mg-doped P-type BN material along the surface of the current GaN diffusion layer until the Mg-doped P-type BN material in each annular groove is higher than the upper edge of the annular groove, and performing thermal annealing to activate the impurities;

[0033] The Mg-doped P-type BN material that is higher than the upper edge of the annular groove is removed, so that the remaining Mg-doped P-type BN material forms a Mg-doped P-type BN field limiting ring in the annular groove, thereby obtaining two silicon-based GaN quasi-vertical structures.

[0034] Compared with the prior art, the monolithic integrated diode clipping unit based on quasi-vertical MPS provided by the present invention has the following beneficial effects:

[0035] (1) In the prior art, most power devices still use high-power silicon single tubes in the form of discrete devices for use in diode limiter units. However, as the requirements for the power processing capacity, equipment miniaturization, and equipment reliability of the rectifier system become increasingly higher, the existing board-level integrated diode limiter units will become increasingly difficult to adapt to the needs of the times. In the monolithic integrated diode limiter unit based on quasi-vertical MPS provided by the present invention, two silicon-based GaN quasi-vertical MPS and thin-film protection resistors are integrated on a monolithic silicon substrate, and a monolithic integrated diode limiter unit based on GaN devices is formed by interconnecting metals, thereby achieving an improvement in device integration, greatly reducing the circuit volume, having smaller parasitic effects, higher power density, and being able to work stably under more complex working conditions. Its excellent electrical performance and stability are suitable for use in high-frequency, high-power, strong radiation, and other occasions, as well as in high-power power conversion systems with limited volume.

[0036] (2) Most diode limiter units in the prior art are made of Si-based materials. However, as the efficiency, power density, and device volume requirements of power processing equipment become increasingly higher, Si-based devices are rapidly approaching the theoretical limits of their intrinsic material properties. The monolithic integrated diode limiter unit provided by the present invention is a GaN device. Compared with Si-based materials, GaN has a larger bandgap, a higher critical breakdown electric field, and a higher saturation speed. Therefore, the monolithic integrated diode limiter unit provided by the present invention has better electrical properties, and its thermal conductivity, temperature stability, and corrosion resistance are far superior to Si devices, and can work stably under more complex working conditions.

[0037] (3) The voltage application range of the existing small-sized diode limiting unit is relatively narrow, and the withstand voltage of the core device diode is relatively low. The monolithic integrated diode limiting unit provided by the present invention uses silicon-based GaN material, and while reducing the circuit cost, it uses a quasi-vertical diode with Mg-doped P-type BN MPS field limiting ring to replace the traditional Schottky diode. The high breakdown field strength of the BN material and the electric field regulation ability of the MPS ring structure are used to greatly improve the withstand voltage level of the Schottky diode while ensuring the forward conduction ability of the diode as much as possible, broadening the power application window of the miniaturized integrated diode limiting unit, improving the withstand voltage of the diode, and enhancing the power handling capacity of the diode limiting unit.

[0038] The present invention will be further described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 It is a schematic diagram of the three-dimensional structure of a monolithic integrated diode limiting unit based on quasi-vertical MPS provided by an embodiment of the present invention;

[0040] Figure 2 yes Figure 1 A top view of the diode limiting unit shown;

[0041] Figure 3 is a schematic structural diagram of a silicon-based gallium nitride substrate exemplarily shown in an embodiment of the present invention;

[0042] Figure 4 is a schematic diagram of a three-dimensional structure of a GaN quasi-vertical MPS on silicon shown exemplarily in an embodiment of the present invention;

[0043] Figure 5 yes Figure 4 The cross-sectional view of the GaN quasi-vertical MPS on silicon is shown;

[0044] Figure 6 It is a circuit schematic diagram of a monolithic integrated diode limiter unit based on quasi-vertical MPS provided by an embodiment of the present invention;

[0045] Figure 7 It is shown in Figure 6 The working principle of the circuit shown;

[0046] Figures 8 to 19 It is a flow chart of a method for preparing a monolithically integrated diode limiting unit based on quasi-vertical MPS provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0047] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0048] In order to enable the diode clipping unit to have a higher withstand voltage performance and be applicable to high power conditions, the embodiment of the present invention provides a monolithic integrated diode clipping unit based on quasi-vertical MPS, see Figure 1 and Figure 2 As shown, the device includes: a silicon substrate (Si-substrate) 10, two silicon-based GaN quasi-vertical MPSs located on the silicon substrate 10, a passivation layer 20, a thin film protection resistor R, a first interconnection metal and a second interconnection metal.

[0049] Among them, two silicon-based GaN quasi-vertical MPSs form a forward limiting diode D1 and a reverse limiting diode D2 respectively. Here, both limiting units adopt a quasi-vertical diode structure, which is convenient for circuit connection using on-chip wiring, thereby realizing the circuit construction of the entire monolithic integrated diode limiting unit.

[0050] Optionally, in one implementation, the silicon-based GaN quasi-vertical MPS may include: a silicon substrate 10 , a GaN conducting layer, a GaN diffusion layer, a cathode ohmic metal, and an anode Schottky metal.

[0051] Among them, the GaN conduction layer (N+GaN) is superimposed on the silicon substrate, and the GaN diffusion layer (N GaN) is superimposed on the middle area of ​​the upper surface of the GaN conduction layer to form a silicon-based gallium nitride bottom. Figure 3 The anode Schottky metal (Anode) is located on the upper surface of the GaN diffusion layer; the cathode ohmic metal (Cathode) is located on the upper surface of the GaN conductive layer not covered by the GaN diffusion layer and surrounds the GaN diffusion layer, such as Figure 4 .

[0052] In another implementation, see Figure 4 and Figure 5 The GaN quasi-vertical MPS on silicon may include: a silicon substrate 10, a GaN conducting layer, a GaN diffusion layer, one or more Mg-doped P-type BN field limiting rings, a cathode ohmic metal, and an anode Schottky metal.

[0053] Among them, the GaN conductive layer is superimposed on the silicon substrate 10, and the GaN diffusion layer is superimposed on the middle area of ​​the upper surface of the GaN conductive layer; one or more annular grooves are provided on the top layer of the GaN diffusion layer; multiple annular grooves are concentrically arranged; Mg-doped P-type BN material is deposited in the annular groove to form a Mg-doped P-type BN field limiting ring; the anode Schottky metal (Anode) is located on the upper surface of the GaN diffusion layer and contacts with one or more Mg-doped P-type BN field limiting rings; the cathode ohmic metal (Cathode) is located on the upper surface of the GaN conductive layer not covered by the GaN diffusion layer and surrounds the GaN diffusion layer.

[0054] Preferably, the Si doping concentration of the GaN conductive layer is 1.0×10 18 cm -3 ~1.0×10 20 cm -3 .

[0055] Preferably, the Si doping concentration of the GaN diffusion layer is 1.8×10 16 cm -3 ~5.0×10 17 cm -3 .

[0056] Preferably, the Mg doping concentration of the Mg-doped P-type BN field limiting ring is 1.7×10 16 cm -3 ~3.0×10 17 cm -3 .

[0057] Preferably, the width of the Mg-doped P-type BN field limiting ring is 2μm to 4μm, and the depth is 0.5μm to 4μm. In practice, the specific width and depth of the Mg-doped P-type BN field limiting ring can be determined according to the withstand voltage and forward conduction capability, and the number of rings can be determined according to the current requirement, which can be one or more. Among them, when multiple annular grooves are provided, the spacing between adjacent annular grooves is preferably 1μm to 2.5μm.

[0058] Continue to see Figure 1 and Figure 2 , the passivation layer 20 covers the two silicon-based GaN quasi-perpendicular MPSs and the silicon substrate 10; specifically, the passivation layer 20 is formed by multiple growths, which covers the entire silicon-based GaN quasi-perpendicular MPS, on the one hand to achieve component protection and electrical isolation, on the other hand to form a relatively flat plane on the upper surface of the overall structure of the diode limiting unit, so as to facilitate metal interconnection between internal devices on this plane, which will be described in detail later.

[0059] Preferably, the material of the passivation layer 20 may be SiN, but is certainly not limited thereto.

[0060] See also Figure 1 and Figure 2 The thin film protection resistor is located inside the passivation layer; the material constituting the thin film protection resistor may be TaN, NiCr, etc. In practice, different resistance values ​​may be achieved by setting different aspect ratios according to the required resistance value, thereby obtaining the corresponding current carrying capacity.

[0061] The first interconnection metal is used to connect the first end of the thin film protection resistor R to the cathode of the reverse limiting diode D2. The embodiment of the present invention does not limit the material of the first interconnection metal. In practice, the first interconnection metal is located inside the passivation layer.

[0062] The second interconnection metal is used to form the voltage input terminal 1, the voltage output terminal 2, the first reference voltage terminal 3 and the second reference voltage terminal 4 of the monolithic integrated diode limiter unit, see Figure 1 and Figure 2 The second interconnect metal is also used to connect the cathode of the forward limiting diode D1 to the first reference voltage terminal 3, connect the anode of the forward limiting diode D1, the cathode of the reverse limiting diode D2, and the first end of the thin film protection resistor R to the voltage output terminal 2, connect the anode of the reverse limiting diode D2 to the second reference voltage terminal 4, and connect the second end of the thin film protection resistor R to the voltage input terminal 1.

[0063] In practice, the second interconnect metal includes two parts, one part is located on the top of the passivation layer, including metals forming the voltage input terminal 1, the voltage output terminal 2, the first reference voltage terminal 3 and the second reference voltage terminal 4, and also including metals connecting the anode of the forward limiting diode D1 to the voltage output terminal 2; the other part of the second interconnect metal is located inside the passivation layer, and is used to connect the part of the second interconnect metal located on the top of the passivation layer to the first interconnect metal of the lower layer, including: metal connecting the cathode of the forward limiting diode D1 to the first reference voltage terminal 3, metal connecting the first interconnect metal to the anode of the forward limiting diode D1 and the voltage output terminal 2, and metal connecting the second end of the thin film protection resistor R to the voltage input terminal 1.

[0064] Thus, the thin film protection resistor and the two limiting diodes are connected together through the first interconnection metal and the second interconnection metal to form a Figure 6 The following is based on the circuit shown in Figure 6 The circuit shown illustrates the working principle of the monolithic integrated diode limiter unit provided in the embodiment of the present invention.

[0065] See also Figure 7, assuming that the turn-on voltages of the forward limiting diode D1 and the reverse limiting diode D2 are both Vth, the second reference voltage terminal 4 is connected to the forward limiting reference voltage Uf, the first reference voltage terminal 3 is connected to the reverse limiting reference voltage Ur, the input voltage of the voltage input terminal 1 is Uin, and is a sinusoidal AC signal, and its amplitude is U0.

[0066] When the input voltage Uin of the voltage input terminal 1 is in the positive polarity cycle, the reverse limiting diode D2 must be reversely cut off. When Uin is less than the sum of Uf and Vth, the forward limiting diode D1 remains cut off, and the voltage of the voltage output port 2 is consistent with the voltage of the voltage input port 1. When the value of Uin is greater than the sum of Uf and Vth, the forward limiting diode D1 is turned on. Due to the clamping characteristics of the diode, the voltage of the anode of D1 is limited to Vth+Uf, that is, the output voltage remains unchanged, triggering the limit. As the input voltage value gradually falls below the sum of Uf and Vth, the forward limiting diode D1 is cut off again, and the voltage of the voltage output terminal 2 is synchronized with the voltage of the voltage input terminal 1 again, completing the forward limiting process.

[0067] When the input voltage Uin of the voltage input terminal 1 is in the negative polarity cycle, the forward limiting diode D1 is reversely cut off. When Uin is greater than the sum of Ur and Vth, the reverse limiting diode D2 remains cut off, and the voltage of the voltage output port 2 is consistent with the voltage of the voltage input port 1. When the value of Uin is less than the sum of Ur and Vth, the reverse limiting diode D2 is turned on. Due to the clamping characteristics of the diode, the voltage of the cathode of D2 is limited to Vth+Ur, that is, the output voltage remains unchanged, triggering the limit. As Uin gradually rises below the sum of Ur and Vth, the reverse limiting diode D2 is cut off again, and the voltage of the voltage output terminal 2 is synchronized with the voltage of the voltage input terminal 1 again, completing the reverse limiting process.

[0068] In the monolithic integrated diode limiter unit based on quasi-vertical MPS provided in the embodiment of the present invention, two silicon-based GaN quasi-vertical MPSs and a thin film protection resistor are integrated on a monolithic silicon substrate, and a monolithic integrated diode limiter unit based on GaN devices is formed by interconnecting metals, thereby achieving an improvement in device integration, greatly reducing the circuit volume, having smaller parasitic effects, higher power density, and being able to work stably under more complex working conditions. Its excellent electrical performance and stability are suitable for application in high-frequency, high-power, strong radiation and other occasions as well as high-power power conversion systems with limited volume.

[0069] The monolithic integrated diode limiting unit provided in the embodiment of the present invention is a GaN device. Compared with Si-based materials, GaN has a larger bandgap width, a higher critical breakdown electric field and a higher saturation speed. Therefore, the monolithic integrated diode limiting unit provided in the present invention has better electrical properties, and its thermal conductivity, temperature stability, corrosion resistance and other properties are far superior to Si devices, and it can work stably under more complex working conditions.

[0070] The monolithic integrated diode limiting unit provided in the embodiment of the present invention uses silicon-based GaN material. While reducing circuit costs, a quasi-vertical diode with Mg-doped P-type BN MPS field limiting ring enhancement is used to replace the traditional Schottky diode. The high breakdown field strength of the BN material and the electric field adjustment capability of the MPS ring structure are utilized to greatly improve the withstand voltage level of the Schottky diode while ensuring the forward conduction capability of the diode as much as possible, thereby broadening the power application window of the miniaturized integrated diode limiting unit, improving the withstand voltage of the diode, and enhancing the power processing capability of the diode limiting unit.

[0071] Based on the same inventive concept, an embodiment of the present invention further provides a method for preparing a monolithically integrated diode limiting unit based on quasi-vertical MPS, comprising the following steps:

[0072] Step 1: prepare two GaN on silicon quasi-vertical structures on the silicon substrate 10; the two GaN on silicon quasi-vertical structures are used to subsequently form two GaN on silicon quasi-vertical MPSs.

[0073] Specifically, two silicon-based GaN quasi-vertical structures are prepared on the silicon substrate 10, including:

[0074] (1) A GaN conducting layer and a GaN diffusion layer are sequentially epitaxially grown on a silicon substrate 10, and the GaN diffusion layer is subjected to mesa etching, such as Figure 8 Sub-figure (a); then the etched GaN diffusion layer and GaN conduction layer are subjected to device isolation etching, such as Figure 8 As shown in sub-figure (b), two silicon-based gallium nitride substrates can be formed; in the silicon-based gallium nitride substrate, the GaN diffusion layer is superimposed on the middle region of the GaN conductive layer.

[0075] (2) Etching one or more annular grooves on the top layer of the GaN diffusion layer of the two silicon-based gallium nitride substrates, such as Fig. 9 Sub-figure (c) of FIG; wherein a plurality of annular grooves are arranged concentrically, see Figure 5 ;

[0076] (3) Mg-doped P-type BN material is deposited along the surface of the current GaN diffusion layer until the Mg-doped P-type BN material in each annular groove is higher than the upper edge of the annular groove, and thermal annealing is performed to activate the impurities, such as Fig. 9 Subgraph (d).

[0077] (4) The Mg-doped P-type BN material that is higher than the upper edge of the annular groove is removed, so that the remaining Mg-doped P-type BN material forms a Mg-doped P-type BN field limiting ring in the annular groove, and two silicon-based GaN quasi-vertical structures are obtained, such as Fig.10 Subgraph (e) in .

[0078] Step 2: deposit a first passivation layer 20 on the surface of the current device, such as Fig.10 Sub-figure (f) in FIG. 1 ; the passivation layer is opened to expose the anode region and the cathode region, as shown in FIG. Fig.11 Sub-figure (g) in FIG. 1 ; the anode region corresponds to the anode of the silicon-based GaN quasi-perpendicular MPS; the cathode region corresponds to the cathode of the silicon-based GaN quasi-perpendicular MPS.

[0079] The anode region is located on the upper surface of the GaN diffusion layer and includes the regions where the Mg-doped P-type BN field limiting rings are located; the cathode region is located on the upper surface of the GaN conductive layer not covered by the GaN diffusion layer and surrounds the GaN diffusion layer.

[0080] Step 3: deposit an anode Schottky metal in the anode region and a cathode ohmic metal in the cathode region, so that the two silicon-based GaN quasi-vertical structures form two silicon-based GaN quasi-vertical MPSs, and deposit a thin film protection resistor on the surface of the current passivation layer.

[0081] Specifically, a Schottky metal is first deposited in the anode region. The anode Schottky metal is located on the upper surface of the GaN diffusion layer and is in contact with each Mg-doped P-type BN field limiting ring, such as Fig.11 Sub-figure (h) in the figure; illustratively, the anode Schottky metal is, for example, a Ni / Au stacked structure, but is certainly not limited thereto.

[0082] Then, a cathode ohmic metal is deposited in the cathode region. The cathode ohmic metal is located on the upper surface of the portion of the GaN conductive layer not covered by the GaN diffusion layer and surrounds the GaN diffusion layer. Fig.12 Sub-figure (i) in the figure; illustratively, the cathode ohmic metal is, for example, a stacked structure of Ti / Al / Ni / Au, but is not limited thereto.

[0083] Thus, the two silicon-based GaN quasi-vertical structures form two silicon-based GaN quasi-vertical MPSs, and the two silicon-based GaN quasi-vertical MPSs serve as a forward limiting diode D1 and a reverse limiting diode D2, respectively.

[0084] Then, a thin film protection resistor R is deposited next to the two GaN quasi-vertical MPS on silicon, as shown in FIG. Fig.13 .

[0085] Step 4: deposit a second passivation layer 20 on the surface of the current device, such as Fig.14The passivation layer is opened to expose the anode and cathode of the forward limiting diode D1, the anode and cathode of the reverse limiting diode D2, and the first and second ends of the thin film protection resistor R, such as Fig.15 .

[0086] Step 5: Prepare a first interconnect metal on the current device to connect the first end of the thin film protection resistor to the cathode of the reverse limiting diode D2, such as Fig.16 .

[0087] Fig.16 In the process, the first metal interconnection is performed to obtain the first interconnection metal.

[0088] It should be noted that Fig.16 and follow-up Figures 17 to 19 The metal interconnection lines shown in the figure are only to show the preparation time and approximate location of the interconnection metal, and do not represent the actual metal interconnection relationship. The actual metal interconnection relationship is Figure 6 , Figure 1 , Figure 2 The ones shown in the table shall prevail.

[0089] Step 6: deposit a third passivation layer 20 on the surface of the current device, such as Fig.17 The passivation layer is opened to expose the anode and cathode of the forward limiting diode D1, the anode and cathode of the reverse limiting diode D2, and the second end of the thin film protection resistor, such as Fig.18 .

[0090] Step 7: Prepare a second interconnect metal on the current device to form a voltage input terminal 1, a voltage output terminal 2, a first reference voltage terminal 3, and a second reference voltage terminal 4 of the monolithic integrated diode limiting unit, and connect the cathode of the forward limiting diode D1 to the first reference voltage terminal 3, connect the anode of the forward limiting diode D1, the cathode of the reverse limiting diode D2, and the first end of the thin film protection resistor to the voltage output terminal 2, connect the anode of the reverse limiting diode D2 to the second reference voltage terminal 4, and connect the second end of the thin film protection resistor to the voltage input terminal 1, as shown in FIG. Fig.19 .

[0091] Fig.19 In the process, the second-layer metal interconnection is performed to obtain the second interconnection metal.

[0092] It should be noted that, for the preparation method embodiment, since the structure prepared therein is basically similar to that of the device embodiment, the description is relatively simple, and the relevant parts may refer to the partial description of the device embodiment.

[0093] It should be noted that the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present disclosure described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices and methods consistent with some aspects of the present disclosure.

[0094] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0095] Although the present application is described herein in conjunction with various embodiments, in the process of implementing the claimed application, those skilled in the art can understand and implement other changes to the disclosed embodiments by viewing the drawings and the disclosed content. In the description of the present invention, the term "comprising" does not exclude other components or steps, "one" or "an" does not exclude multiple situations, and the meaning of "multiple" is two or more, unless otherwise clearly and specifically limited. In addition, certain measures are recorded in different embodiments, but this does not mean that these measures cannot be combined to produce good results.

[0096] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0097] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0098] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0099] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A monolithic integrated diode clipping unit based on quasi-vertical MPS, characterized in that: include: Silicon substrate; Two GaN-on-Si quasi-vertical MPSs on a silicon substrate; The two silicon-based GaN quasi-vertical MPSs respectively form a forward limiting diode and a reverse limiting diode; Passivation layer; the passivation layer covers the two silicon-based GaN quasi-vertical MPSs and the silicon substrate; A thin film protection resistor; the thin film protection resistor is located inside the passivation layer; A first interconnection metal; the first interconnection metal is used to connect the first end of the thin film protection resistor to the cathode of the reverse limiting diode; The second interconnecting metal is used to form the voltage input terminal, the voltage output terminal, the first reference voltage terminal and the second reference voltage terminal of the monolithic integrated diode limiting unit, and is also used to connect the cathode of the forward limiting diode to the first reference voltage terminal, connect the anode of the forward limiting diode, the cathode of the reverse limiting diode, and the first end of the thin film protection resistor to the voltage output terminal, connect the anode of the reverse limiting diode to the second reference voltage terminal, and connect the second end of the thin film protection resistor to the voltage input terminal.

2. The monolithic integrated diode clipping unit based on quasi-vertical MPS according to claim 1, characterized in that: The silicon-based GaN quasi-vertical MPS comprises: a silicon substrate, a GaN conducting layer, a GaN diffusion layer, one or more Mg-doped P-type BN field limiting rings, a cathode ohmic metal and an anode Schottky metal; The GaN conductive layer is superimposed on the silicon substrate, and the GaN diffusion layer is superimposed on the middle area of ​​the upper surface of the GaN conductive layer; one or more annular grooves are provided on the top layer of the GaN diffusion layer; a plurality of the annular grooves are concentrically arranged; Mg-doped P-type BN material is deposited in the annular groove to form the Mg-doped P-type BN field limiting ring; the anode Schottky metal is located on the upper surface of the GaN diffusion layer and is in contact with the one or more Mg-doped P-type BN field limiting rings; the cathode ohmic metal is located on the upper surface of the GaN conductive layer that is not covered by the GaN diffusion layer, and surrounds the GaN diffusion layer.

3. The monolithic integrated diode clipping unit based on quasi-vertical MPS according to claim 2, characterized in that: The Mg doping concentration of the Mg-doped P-type BN field limiting ring is 1.7×10 16 cm -3 ~3.0×10 17 cm -3 .

4. The monolithic integrated diode clipping unit based on quasi-vertical MPS according to claim 2, characterized in that: The Mg-doped P-type BN field limiting ring has a width of 2 μm to 4 μm and a depth of 0.5 μm to 4 μm.

5. The monolithic integrated diode clipping unit based on quasi-vertical MPS according to claim 2, characterized in that: When a plurality of annular grooves are provided, the interval between adjacent annular grooves is 1 μm to 2.5 μm.

6. The monolithic integrated diode clipping unit based on quasi-vertical MPS according to claim 2, characterized in that: The Si doping concentration of the GaN diffusion layer is 1.8×10 16 cm -3 ~5.0×10 17 cm -3 .

7. The monolithic integrated diode clipping unit based on quasi-vertical MPS according to claim 2, characterized in that: The Si doping concentration of the GaN conduction layer is 1.0×10 18 cm -3 ~1.0×10 20 cm -3 .

8. A method for preparing a monolithic integrated diode limiter unit based on quasi-vertical MPS, characterized in that: include: Prepare two GaN-on-silicon quasi-vertical structures on a silicon substrate; The two silicon-based GaN quasi-vertical structures are used to subsequently form two silicon-based GaN quasi-vertical MPSs; Depositing a first passivation layer on the surface of the current device, and opening holes in the passivation layer to expose the anode region and the cathode region; The anode region corresponds to the anode of the silicon-based GaN quasi-perpendicular MPS; the cathode region corresponds to the cathode of the silicon-based GaN quasi-perpendicular MPS; An anode Schottky metal is deposited in the anode region, and a cathode ohmic metal is deposited in the cathode region, so that the two silicon-based GaN quasi-vertical structures form two silicon-based GaN quasi-vertical MPSs, and a thin film protection resistor is deposited on the surface of the current passivation layer; wherein the two silicon-based GaN quasi-vertical MPSs serve as a forward limiting diode and a reverse limiting diode respectively; Depositing a second passivation layer on the surface of the current device, and opening the passivation layer to expose the anode and cathode of the forward limiting diode, the anode and cathode of the reverse limiting diode, and the first end and the second end of the thin film protection resistor; Preparing a first interconnect metal on the current device to connect a first end of the thin film protection resistor to a cathode of the reverse limiting diode; Depositing a third passivation layer on the surface of the current device, and opening the passivation layer to expose the anode and cathode of the forward limiting diode, the anode and cathode of the reverse limiting diode, and the second end of the thin film protection resistor; A second interconnect metal is prepared on the current device to form a voltage input terminal, a voltage output terminal, a first reference voltage terminal and a second reference voltage terminal of the monolithic integrated diode limiting unit, and the cathode of the forward limiting diode is connected to the first reference voltage terminal, the anode of the forward limiting diode, the cathode of the reverse limiting diode, and the first end of the thin film protection resistor are connected to the voltage output terminal, the anode of the reverse limiting diode is connected to the second reference voltage terminal, and the second end of the thin film protection resistor is connected to the voltage input terminal.

9. The preparation method according to claim 8, characterized in that: Two GaN-on-silicon quasi-vertical structures are prepared on a silicon substrate, including: Epitaxially growing a GaN conduction layer and a GaN diffusion layer on a silicon substrate in sequence, performing mesa etching on the GaN diffusion layer, and performing device isolation etching on the etched GaN diffusion layer and the GaN conduction layer to form two silicon-based gallium nitride substrates; in the silicon-based gallium nitride substrate, the GaN diffusion layer is superimposed on the middle region of the GaN conduction layer; Etching one or more annular grooves on the top layers of the GaN diffusion layers of the two silicon-based gallium nitride substrates respectively; wherein the plurality of annular grooves are concentrically arranged; Depositing Mg-doped P-type BN material along the surface of the current GaN diffusion layer until the Mg-doped P-type BN material in each annular groove is higher than the upper edge of the annular groove, and performing thermal annealing to activate the impurities; The Mg-doped P-type BN material that is higher than the upper edge of the annular groove is removed, so that the remaining Mg-doped P-type BN material forms a Mg-doped P-type BN field limiting ring in the annular groove, thereby obtaining two silicon-based GaN quasi-vertical structures.

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