Hybrid lead bonding structure and method

Abstract

The invention relates to the technical field of chip packaging, in particular to a mixed lead bonding structure and method. Comprising a carrier plate, a plurality of staggered and stacked chip particles are arranged on the surface of one side of the carrier plate, a substrate is arranged above the chip particles, bonding pads at the same position of every two adjacent chip particles are connected through an arc lead, one bonding pad is connected with one end of a vertical lead, and the other end of the vertical lead is connected with the substrate. Compared with the prior art, the problem that the vertical lead is in contact with the welding needle head when the distance between the bonding pads is very short is avoided.

Description

Technical Field

[0001] The invention relates to the technical field of chip packaging, in particular to a hybrid wire bonding structure and method. Background Art

[0002] The three-dimensional stacking of chip particles is a packaging process that can both reduce the size of the chip package and improve its performance. It is widely used in the packaging process of memory chips (NAND, DRAM, etc.). Its main process flow is as follows: Figure 7 As shown in the figure, after the memory chip wafer is thinned and cut into particles (die), DAF is attached to the back, and then the particles are stacked one by one on an organic or inorganic substrate (substrate). The electrical and information interconnection between particles and between particles and substrates is achieved through wire bonding.

[0003] The usual wires are connected in parallel by arc routing to achieve electrical interconnection. Recently, in order to reduce the parasitic capacitance and resistance of the routing, many manufacturers have begun to develop vertical interconnection wire bonding methods, such as Figure 8 shown.

[0004] One of the difficulties of vertical wire bonding is that when the pad spacing on the same chip is very short (Finepitch, for example, less than 80 µm), the vertical wire is prone to contact with the wire bonding needle, resulting in defects such as Fig. 9 Therefore, it is necessary to invent an effective wire bonding method to solve the problem of contact between the vertical wire and the solder pin. Summary of the invention

[0005] The present invention provides a hybrid wire bonding structure and method to overcome the deficiencies of the prior art.

[0006] To achieve the above purpose, a hybrid wire bonding structure is designed, including a carrier, a surface of one side of the carrier is provided with a plurality of staggered and stacked chip particles, a substrate is provided above the chip particles, the pads at the same position of two adjacent chip particles are connected by an arc lead, and one of the pads is connected to one end of a vertical lead, and the other end of the vertical lead is connected to the substrate.

[0007] The pads that connect the vertical leads are away from the side where the arc leads are bent.

[0008] The vertical leads on the same chip particle are arranged at intervals, and the vertical leads on adjacent chip particles are arranged in a staggered manner.

[0009] In the same chip particle, the directions of the arc leads on adjacent pads are the same.

[0010] The carrier board is provided with a plurality of pads, and the pads on the carrier board are connected with the chip particles at the bottom layer through arc leads, and are interconnected with the substrate through vertical leads.

[0011] In the same chip particle, the directions of the arc leads on adjacent pads are opposite.

[0012] The number of the chip particles is an even number.

[0013] The number of the chip particles is an odd number, and the pads on the carrier are connected to the chip particles on the bottom layer through arc leads and are interconnected with the substrate through vertical leads.

[0014] The staggered distance between adjacent chip particles is 200±100 um; the pad spacing is 50-100 um; the diameter of the arc lead and vertical lead is 15-25 um.

[0015] To achieve the above purpose, a hybrid wire bonding process is designed, comprising the following steps: S1, stacking a number of chip particles alternately on a carrier board to expose a pad of each chip particle; S2, connecting the pads at the same position of adjacent chip particles together through arc wire bonding; S3, among the two pads interconnected by the arc wire, one of the pads is bonded to the substrate by the vertical wire.

[0016] Compared with the prior art, the present invention avoids the problem of vertical lead wires contacting with soldering needles when the spacing between soldering pads is very short. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 The structure of the first embodiment of the present invention is shown in FIG. Figure 1 .

[0018] Figure 2 The structure of the first embodiment of the present invention is shown in FIG. Figure 2 .

[0019] Figure 3 This is a schematic diagram of the process of Embodiment 1 of the present invention.

[0020] Figure 4 This is a schematic diagram of the structure of the second embodiment of the present invention.

[0021] Figure 5 This is a schematic diagram of the process of the second embodiment of the present invention.

[0022] Figure 6 A schematic structural diagram of embodiment 3 of the present invention.

[0023] Figure 7 This is a schematic diagram of the process of three-dimensional stacking of chip particles before the improvement of the present invention.

[0024] Figure 8 This is a schematic diagram of the wire bonding method for vertical interconnection before improvement of the present invention.

[0025] Fig. 9 This is a schematic diagram showing that the vertical lead is easily in contact with the soldering needle head used for wire bonding before the improvement of the present invention. DETAILED DESCRIPTION

[0026] The present invention will be further described below with reference to the accompanying drawings. Example

[0027] like Figure 1 to Figure 2 As shown, a plurality of staggered and stacked chip particles 2 are provided on one surface of a carrier board 1, a substrate is provided above the chip particles 2, and pads 3 at the same position of two adjacent chip particles 2 are connected by an arc lead 4, and one of the pads 3 is connected to one end of a vertical lead 5, and the other end of the vertical lead 5 is connected to the substrate.

[0028] The pad 3 connected to the vertical lead 5 is away from the bent side of the arc lead 4. This prevents the vertical lead 5 from interfering with the arc lead 4 during bonding, thereby preventing poor contact and ensuring the qualified rate of the product.

[0029] The vertical leads 5 on the same chip particle 2 are arranged at intervals, and the vertical leads 5 on adjacent chip particles 2 are arranged in a staggered manner.

[0030] In this embodiment, in the same chip particle 2, the directions of the arc leads 4 on adjacent pads 3 are the same.

[0031] The carrier 1 is provided with a plurality of pads 3, and the pads 3 on the carrier 1 are connected to the bottom layer of chip particles 2 through arc leads 4, and are interconnected with the substrate through vertical leads 5. Since the vertical bonding of the pads 3 of adjacent chip particles 2 is staggered, the smooth connection of this embodiment requires an additional row of pads on the carrier to receive the vertical bonding portion of the pads 3 of the bottom layer of chip particles 2.

[0032] In this embodiment, the number of chip particles 2 is an odd number or an even number.

[0033] The staggered distance between adjacent chip particles 2 is 200±100 um; the spacing between pads 3 is 50-100 um; the diameters of arc leads 4 and vertical leads 5 are 15-25 um.

[0034] like Figure 3 As shown, the hybrid wire bonding method in this embodiment includes the following steps: S1, stacking a plurality of chip particles 2 alternately on a carrier board 1, exposing a pad 3 of each chip particle 2; S2, bonding the pads 3 at the same position of adjacent chip particles 2 together through arc wires 4; S3 , among the two pads 3 interconnected by the arc lead 4 , one of the pads 3 is bonded to the substrate by the vertical lead 5 .

[0035] Adjacent chip particles 2 and chip particles 2 and carrier board 1 are bonded together by bonding materials. In this embodiment, the bonding material is DAF film.

[0036] The pads 3 of several chip particles 2 have the same arrangement structure. Example

[0037] This embodiment only describes the differences from the first embodiment, and the similarities are not described again.

[0038] The difference between this embodiment and the first embodiment is that Figures 4 to 5 As shown, this embodiment is a forward and reverse connection, and in the same chip particle 2, the directions of the arc leads 4 on adjacent pads 3 are opposite.

[0039] In this embodiment, the number of chip particles 2 is an even number. Example

[0040] This embodiment only describes the differences from the first embodiment, and the similarities are not described again.

[0041] The difference between this embodiment and the first embodiment is that Figure 6 As shown, this embodiment is a forward and reverse connection, and in the same chip particle 2, the directions of the arc leads 4 on adjacent pads 3 are opposite.

[0042] In this embodiment, the number of chip particles 2 is an odd number. At this time, a row of pads needs to be added on the carrier 1 to receive the remaining pads. The pads 3 on the carrier 1 are connected to the bottom layer of chip particles 2 through arc leads 4, and are interconnected with the substrate through vertical leads 5.

Claims

1. A hybrid wire bonding structure, comprising a carrier, characterized in that: A plurality of staggered and stacked chip particles (2) are provided on one side of the carrier (1), a substrate is provided above the chip particles (2), the pads (3) at the same position of two adjacent chip particles (2) are connected via an arc lead (4), and one of the pads (3) is connected to one end of a vertical lead (5), and the other end of the vertical lead (5) is connected to the substrate.

2. A hybrid wire bonding structure according to claim 1, characterized in that: The pad (3) connected to the vertical lead (5) is away from the side where the arc lead (4) is bent.

3. The hybrid wire bonding structure according to claim 1, characterized in that: The vertical leads (5) on the same chip particle (2) are arranged at intervals, and the vertical leads (5) on adjacent chip particles (2) are arranged in a staggered manner.

4. The hybrid wire bonding structure according to claim 1, characterized in that: In the same chip particle (2), the arc leads (4) on adjacent pads (3) have the same direction.

5. A hybrid wire bonding structure according to claim 4, characterized in that: The carrier (1) is provided with a plurality of pads (3). The pads (3) on the carrier (1) are connected to the chip particles (2) at the bottom layer via arc leads (4) and are interconnected with the substrate via vertical leads (5).

6. The hybrid wire bonding structure according to claim 1, characterized in that: In the same chip particle (2), the arc leads (4) on adjacent pads (3) are in opposite directions.

7. A hybrid wire bonding structure according to claim 6, characterized in that: The number of the chip particles (2) is an even number.

8. The hybrid wire bonding structure according to claim 6, characterized in that: The number of the chip particles (2) is an odd number, and the pads (3) on the carrier board (1) are connected to the chip particles (2) on the bottom layer via arc leads (4), and are interconnected with the substrate via vertical leads (5).

9. The hybrid wire bonding structure according to claim 1, characterized in that: The distance between adjacent chip particles (2) is 200±100 um; the distance between pads (3) is 50-100 um; and the diameters of arc leads (4) and vertical leads (5) are 15-25 um.

10. A hybrid wire bonding process, characterized in that: The steps include: S1, stacking a plurality of chip particles (2) alternately on a carrier board (1) to expose a pad (3) of each chip particle (2); S2, bonding pads (3) at the same position of adjacent chip particles (2) together through arc wires (4); S3, among the two pads (3) interconnected by the arc wire (4), one of the pads (3) is bonded to the substrate by the vertical wire (5).

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