Method for manufacturing dual damascene structure with a trench formed first
a damascene structure and trench technology, applied in semiconductor/solid-state device manufacturing, basic electric elements, electric apparatus, etc., can solve the problems of no effective dry etching process for copper, and hidden problems, etc., to reduce the q-time, reduce the cost, and reduce the cost
Inactive Publication Date: 2006-08-31
TRENCHANT BLADE TECH LLC
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Benefits of technology
This approach reduces copper oxidation risk, eliminates micro trenches and fences, and enhances photolithography control windows, resulting in improved semiconductor device quality and yield.
Problems solved by technology
However, copper itself is inclined to oxidize and tends to react with other materials at low temperatures.
Further, no effective dry etching process exists for copper.
This method, however, conceals some problems.
Using copper as the metal layer dramatically affects the quality of the devices, since copper is inclined to oxidize.
For example, fences cause poor coverage capability of barrier layers and electrochemical plating (ECP) deposition.
Fences, for instance, further result in unsteady electrical properties, as well as poor reliability of devices.
Therefore the photoresist is not developed and patterned well, which also leads to a decrease in the production yield.
Method used
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[0023] A method for manufacturing a dual damascene structure with a trench formed first is disclosed in the invention, in order to reduce Q-time when copper is exposed to the air to shorten the process, to increase development ability of the photoresist to increase the control windows of the photolithography process, and also to eliminate the problems of micro trenches and fences. As a result, the productivity and the yield of semiconductor devices are effectively improved in accordance with the invention. The making and using of the preferred embodiment of the present invention are discussed in detail below with reference to drawings. It should be appreciated, however, those skilled in the art would make and use in a wide variety ways of the present invention without departing from the spirit and the scope of the invention.
[0024]FIGS. 3A-3H illustrate a preferred embodiment of manufacturing a dual damascene structure with a trench formed first in accordance with the present invent...
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A method for manufacturing a dual damascene structure, which forms a trench first, is described. The manufacturing method has following steps. First, a substrate with a plurality of semiconductor devices is provided. A first metal layer, a first etching stop layer, a dielectric layer, and a second etching stop layer are subsequently formed thereon. A trench is formed in the dielectric layer at a predetermined depth thereafter, and a sacrificial layer is filled therein and is next planarized. Then a photoresist layer is formed thereon for etching a via. Afterward the photoresist layer and the sacrificial layer are both removed. Following that, the first etching stop layer is etched through to expose the first metal layer. Finally, the via and the trench are filled with a second metal layer.
Description
FIELD OF THE INVENTION [0001] This application is a division of U.S. patent application Ser. No. 10 / 919,328, filed Aug. 17, 2004. [0002] The present invention relates to a method of manufacturing a dual damascene structure, and more particularly, to a method of manufacturing a dual damascene structure with a trench formed first. BACKGROUND OF THE INVENTION [0003] The manufacture of integrated circuits (ICs) usually adopts multilevel interconnects to build up 3-D interconnection structures in highly dense devices, as IC device performance extends to higher levels. In devices, the metal lines of the first layer are generally electrically coupled to the drains / sources of devices through vias, and the interconnects between the devices are coupled by the metal lines of other layers. On the other hand, the multilevel interconnects between the metal lines are separated by inter-metal dielectric (IMD) layers, while the respective metal layers are connected by via plugs. The dual damascene p...
Claims
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IPC IPC(8): H01L21/4763H01L21/768
CPCH01L21/76808H01L21/76811
InventorYANG, CHIN-TIENJOU, JUAN-JANNLEE, YU-HUALAI, CHIA-HUNG
OwnerTRENCHANT BLADE TECH LLC