Method for fabricating semiconductor packages
a technology of semiconductor packages and fabrication methods, which is applied in the direction of semiconductor devices, semiconductor/solid-state device details, electrical apparatus, etc., can solve the problems of increasing the overall fabrication cost of the package, and wasting the substrate, so as to avoid material waste, improve the adhesion, and avoid the effect of material was
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first preferred embodiment
[0032]FIGS. 1A to 1K show a method for fabricating semiconductor packages according to a first preferred embodiment of the present invention. First referring to FIG. 1A, a plurality of build-up substrates 10 (only one is shown) each carrying a chip 20 thereon are prepared. The length and width of each of the substrates 10 are approximately equal to predetermined length and width of the final semiconductor package 1 (shown in FIG. 1K) respectively. In this embodiment, the predetermined dimensions of the semiconductor package 1 after singulation are 31 mm×31 mm in length and width, such that the length and width of the substrate 10 are also sized as 31 mm×31 mm, and a diagonal of the substrate 10 is 43.84 mm long as shown in FIG. 1B. Referring to FIG. 1C, a substrate carrier 15 having a plurality of rectangular openings 16 (only one is shown) is prepared. As shown in FIG. 1D, a protruded portion 12 is provided at each corner position of each of the openings 16, and a distance between ...
second preferred embodiment
[0041] Apart from the carrier 15 being made of the organic insulating material such as FR4, FR5 or BT, a metal carrier having a metal layer plated on a surface thereof can also be used in the present invention. The metal layer is made of a material that is poorly adhesive to the encapsulant 32. FIGS. 4A to 4J show a method for fabricating semiconductor packages by using the metal carrier. In this embodiment, the predetermined dimensions of the semiconductor package 1, the dimensions of the substrate 10 and the size of openings 46 of the metal carrier 45 are all consistent with those in the foregoing first embodiment. Only the material used for the carrier 45 and some of the fabrication processes in this embodiment differ from those of the first embodiment.
[0042] First referring to FIG. 4A, a plurality of build-up substrates 10 (only one is shown) each carrying a chip 20 thereon are prepared. The length and width of each of the substrates 10 are made equal to the predetermined lengt...
third preferred embodiment
[0046] In the foregoing embodiments, the molding process is performed to allow the encapsulant 32 to encapsulate the chip 20 (flip chip) and solder bumps for electrically connecting the flip chip 20 to the substrate 10. However, in this third embodiment, referring to FIG. 5, an underfilling process is carried out to use an underfill material 51 such as epoxy resin to encapsulate the solder bumps 50 and fill a gap between the flip chip 20 and the substrate 10 prior to the molding process. This can further enhance the mechanical strength of the solder bumps 50 and electrical performances of the semiconductor package 1.
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