Programmable Processor Architecture
a processor and processor technology, applied in the field of processors, can solve the problems of consuming moderate to high amounts of power, requiring enormous development effort, and using different standards to dictate communication between different gadgets, and achieve the effect of fast operations
Inactive Publication Date: 2007-12-20
ICELERO
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AI Technical Summary
Benefits of technology
The processor achieves low power consumption and cost-effectiveness by optimizing data path, control, and memory granularity, enabling simultaneous execution of multiple applications with reduced die size and manufacturing costs.
Problems solved by technology
However, an emerging problem is the use of different standards dictating communications of and between different gadgets requiring tremendous development effort.
Due to the wide utilization of processors in consumer products, the processor must be inexpensive to manufacture, otherwise, its use in most common consumer electronics is not pragmatic.
Cons: The general purpose nature of the architecture does not leverage common / specific characteristics of a set or sub-set of applications for better price, power and performance.
They consume moderate to high amounts of power with respect to the amount of computation provided.
Performance increase is mostly achieved at the expense of pipeline latency which adversely affects several multimedia and communication algorithms.
Complicated hardware scheduler, sophisticated control mechanisms and significantly reduced restrictions for more efficient automatic code generation for general algorithms have made this category of solutions less area efficient.
Control is both expensive and power consuming especially for primitive control code in many multimedia and communication applications.
Several power and area inefficient techniques were used to make automatic code generation easy.
VLIW architectures are not well suited for processing serial code.
Many have challenged existing and matured laws and design paradigms with little industry success.
Cons: Several designs in this space did not provide an efficient and easy programming solution and therefore was not widely accepted by a community adept in programming DSPs.
Automatic code generation from higher level languages like C was either virtually impossible or highly inefficient for many of the designs.
In many cases, the external interface was complicated because the proprietary reconfigurable fabric did not match industry standard system design methodologies.
Cons: Although performance requirements may be adequately answered, power and price inefficiencies are too high.
This makes the job of the application developer much harder.
Uniform scaling of multiple processors is a very expensive and power consuming resource.
This has shown to display some non-determinism that may be detrimental to the performance of the entire system.
The programming model at the system level suffers from complexity of communicating data, code and control information without any shared memory resources—since shared memory is not uniformly scalable.
Extensive and repetitive glue logic required to connect different types of processors to a homogeneous network adds to the area inefficiencies, increases power and adds to the latency.
Method used
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[0082] Referring now to FIG. 1, an application 10 is shown with reference to a digital product 12 including an embodiment of the present invention. FIG. 1 is intended to provide the reader with a perspective regarding some, but not necessarily all, of the advantages of a product, which includes an embodiment of the present invention relative to those available in the marketplace.
[0083] Accordingly, the product 12 is a converging product in that it incorporates all of the applications that need to be executed by today's mobile phone device 14, digital camera device 16, digital recording or music device 18 and PDA device 20. The product 12 is capable of executing one or more of the functions of the devices 14-20 simultaneously yet utilizing less power.
[0084] The product 12 is typically battery-operated and therefore consumes little power even when executing multiple applications of the applications executed by the devices 14-20. It is also capable of execute code to effectuate opera...
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One embodiment of the present includes a heterogenous, high-performance, scalable processor having at least one W-type sub-processor capable of processing W bits in parallel, W being an integer value, at least one N-type sub-processor capable of processing N bits in parallel, N being an integer value wherein and smaller than W by a factor of two. The processor further includes a shared bus coupling the at least one W-type sub-processor and at least one N-type sub-processor and memory shared coupled to the at least one W-type sub-processor and the at least one N-type sub-processor, wherein the W-type sub-processor rearranges memory to accommodate execution of applications allowing for fast operations.
Description
CROSS REFERENCE TO RELATED APPLICATION [0001] This application is a continuation of U.S. patent application Ser. No. 11 / 180,068, entitled “PROGRAMMABLE PROCESSOR ARCHITECTURE”, filed on Jul. 12, 2005 by Amit Ramchandran and John Reid Hauser, Jr., which claims the benefit of U.S. Provisional Patent Application No. 60 / 598,691, entitled “Quasi-Adiabatic Programmable or COOL Processors Architecture” and filed on Jul. 13, 2004 and the benefit of U.S. Provisional Patent Application No. 60 / 598,417, entitled “Quasi-Adiabatic Programmable Processor Architecture” and filed on Aug. 2, 2004.BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] This invention relates generally to the field of processors and more particularly, to processors having low power consumption, high performance, low die area, and flexibly and scalably employed in multimedia and communications applications. [0004] 2. Description of the Prior Art [0005] With the advent of the popularity of consumer gadgets, s...
Claims
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IPC IPC(8): G06F15/00
CPCG06F1/3203G06F9/30014G06F9/30032G06F9/30036G06F9/3824G06F9/3877G06F9/3885G06F9/3895G06F15/7842G06F15/7867G06F15/8053G06F9/3828G06F15/781G06F9/30038
InventorRAMCHANDRAN, AMITHAUSER, JOHN REID JR.
OwnerICELERO