Oscillator Circuit

Abstract

The present application relates to an oscillator circuit. A small area oscillator circuit is provided. The oscillator circuit includes a first constant current source and a second constant current source, a comparator, a first capacitor element and a second capacitor element, and a resistor element. In a first state, the first capacitor element is connected to the first constant current source and a fixed voltage node, the second capacitor element is connected to the second constant current source and the first current source, and the resistor element is connected to the second constant current source. In a second state, the first capacitor element is connected to the second constant current source and the first constant current source, the second capacitor element is connected to the second constant current source and the fixed voltage node, and the resistor element is connected to the first constant current source.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The entire disclosure of Japanese Patent Application No. 2019-081990 filed on April 23, 2019 including the specification, drawings and abstract is incorporated herein by reference. Technical Field

[0003] The present invention relates to oscillator circuits. Background Art

[0004] A clock oscillator circuit is built into a semiconductor device such as a general-purpose microcomputer. The clock oscillator circuit is a circuit for generating a clock signal for defining the operation of internal modules such as a CPU (Central Processing Unit) and peripheral function blocks.

[0005] In order to reduce the size and cost of the device, a so-called on-chip oscillator (configured without an external component such as a crystal oscillator) may be used for a clock oscillator circuit. Generally, the frequency accuracy of an on-chip oscillator is lower than that of a clock oscillator circuit using an external oscillator. Therefore, the application of an on-chip oscillator is limited.

[0006] The disclosed technologies are listed below.

[0007] <Patent Document 1> U.S. Patent No. 9680413

[0008] Patent document 1 discloses a clock oscillator circuit requiring low power consumption. Specifically, it shows an RC oscillator circuit in which the oscillation frequency is determined by the resistance value and the capacitance value. The oscillation frequency is determined by the resistance value and the capacitance value.

[0009] The clock oscillator circuit of patent document 1 is composed of two constant currents, a resistor capacitor and a comparator. The clock oscillator circuit generates a reference voltage by a constant current flowing through a resistor, and charges the capacitor by another constant current. Here, the voltage of the capacitor rises proportionally with time. The comparator compares the voltage of the capacitor with the reference voltage and generates a clock signal based on the comparison result. The oscillator performs by repeating these operations. The time required for the capacitor to reach the reference voltage is equivalent to half the time of the oscillation period. Therefore, when the oscillation period is T, the resistance value of the resistor element is R, and the capacitance value of the capacitor element is C, the oscillation period T is twice the product of the resistance value R and the capacitance value C, and is defined as the following formula (1).

[0010] T=2RC (1)

[0011] Prior art literature Summary of the invention

[0012] However, the oscillator circuit disclosed in Patent Document 1 has a problem that a resistance element and a capacitance element become large, particularly when a low oscillation frequency is required as a desired oscillation frequency, such as in a real-time clock.

[0013] The present disclosure is to solve the above problems, and the present disclosure provides an oscillator circuit with a small area. Other objects and novel features will become apparent from the description of the specification and the accompanying drawings.

[0014] Means of solving the problem

[0015] According to one embodiment, the oscillator circuit includes: a first constant current source; a second constant current source; a comparator, one input terminal of which is connected to the first constant current source and the other input terminal of which is connected to the second constant current source; a first capacitor; a second capacitor; a resistor, one terminal of which is connected to one of the first constant current source and the second constant current source, and the other terminal is connected to a fixed voltage node; and a switch control circuit for controlling the connection relationship between the first constant current source and the second constant current source, the fixed voltage node, the first capacitor and the second capacitor, and the resistor. The switch control circuit switches between a first state and a second state, wherein in the first state, one of the first capacitors is connected to the first constant current source and the other is connected to the fixed voltage node, one of the second capacitors is connected to the second constant current source and the other is connected to the first constant current source, and one side of the resistor element is connected to the second constant current source; in the second state, according to the output of the comparator, one of the first capacitors is connected to the second constant current source and the other is connected to the second constant current source, one of the second capacitors is connected to the second constant current source and the other is connected to the fixed voltage node, and one side of the resistor element is connected to the first constant current source.

[0016] Effects of the Invention

[0017] According to one embodiment, the RC time constant of the oscillator circuit for achieving the same frequency can be made smaller than that of the comparative example. The area of ​​at least one of the resistance element and the capacitance element can be reduced to reduce the area of ​​the oscillator circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a diagram showing a configuration of an oscillator circuit 100 according to the first embodiment.

[0019] Figure 2 1 is a diagram for explaining an equivalent circuit when the positive phase clock signal CLK of the oscillator circuit 100 according to the first embodiment is at a high level.

[0020] Figure 3 1 is a diagram for explaining an equivalent circuit when the inverted clock signal CLKB of the oscillator circuit 100 according to the first embodiment is at a high level.

[0021] Figure 4 is a diagram showing changes in the potentials of the nodes NX and NY of the oscillator circuit 100 according to the first embodiment.

[0022] Figure 5 is a diagram showing voltage conversion between terminals of the capacitance elements C1 and C2 of the oscillator circuit 100 according to the first embodiment.

[0023] Figure 6 is a diagram showing a configuration of an oscillator circuit 200 according to the second embodiment.

[0024] Figure 7 is a circuit diagram for explaining the circuit configuration of a decoder DC according to the second embodiment.

[0025] Figure 8 is a diagram for explaining switch control signals S0 to S11 output from a decoder DC according to the second embodiment.

[0026] Fig. 9 is a diagram showing an equivalent circuit of a first connection state of the oscillator circuit 200 according to the second embodiment.

[0027] Fig.10 2 is a diagram showing an equivalent circuit of the second connection state of the oscillator circuit 200 according to the second embodiment.

[0028] Fig.11 is a diagram showing an equivalent circuit of the third connection state of the oscillator circuit 200 according to the second embodiment.

[0029] Fig.12 is a diagram showing an equivalent circuit of a fourth connection state of the oscillator circuit 200 according to the second embodiment.

[0030] Fig.13 is a diagram showing changes in the potentials of the nodes NX and NY of the oscillator circuit 200 according to the second embodiment.

[0031] Fig.14 is a diagram showing transition of the voltage between the terminals of the capacitance elements C1 and C2 of the oscillator circuit 200 according to the second embodiment.

[0032] Fig.15 1 is a diagram for explaining a state when the oscillator circuit 200 according to the second embodiment is switched from the first connection state to the second connection state.

[0033] Fig.16 1 is a diagram for explaining a state when the second connection state of the oscillator circuit 200 is switched according to the second embodiment. DETAILED DESCRIPTION

[0034] In the drawings, the same or corresponding components are denoted by the same reference numerals, and description thereof will not be repeated.

[0035] <First Embodiment>

[0036] Figure 1 is a diagram showing a configuration of an oscillation circuit 100 according to the first embodiment.

[0037] Reference Figure 1 The oscillator circuit 100 includes current sources CS1 and CS2, a resistor element R1, capacitor elements C1 and C2, switches SW1 to SW6, and a comparison unit CMP. The switches SW1 to SW6 receive input of a positive phase clock signal CLK or a negative phase clock signal CLKB to perform a switching operation.

[0038] The comparison unit CMP includes a comparator CP and inverters IV0 and IV1. The inverter IV0 inverts the output of the comparator CP to output a positive-phase clock signal CLK.

[0039] Inverter IV1 inverts the input of inverter IV0 and outputs an inverted clock signal CLKB.

[0040] In the capacitance element C1, one is the node NA0 and the other is the node NA1. In the capacitance element C2, one is the node NB0 and the other is the node NB1.

[0041] For example, the current sources CS1 , CS2 are configured by a current mirror circuit using MOS transistors.

[0042] The switches SW1 to SW6 are composed of, for example, MOS transistors. The current source CS1 is connected between a power supply node (power supply voltage VDD) and a node NX, and supplies a constant current Ic.

[0043] The current source CS2 is connected between the power supply node (power supply voltage VDD) and the node NY, and provides a constant current Ic.

[0044] One input terminal of the comparator CP is connected to the node NX, and the other input terminal is connected to the node NY. The comparator CP compares the potential of the node NX with the potential of the node NY, and outputs a signal corresponding to the comparison result.

[0045] The node NA0 of the capacitive element C1 is connected to the node NX. The node NA1 of the capacitive element C1 is connected to the fixed voltage VSS (fixed voltage node) via the switch SW3. The switch SW3 receives the positive phase clock signal CLK.

[0046] The node NB0 of the capacitance element C2 is connected to the node NY. The node NB1 of the capacitance element C2 is connected to the fixed voltage VSS (fixed voltage node) via the switch SW4. The switch SW4 receives the inverted clock signal CLKB.

[0047] The switch SW1 is connected between the node NX and the node NC, and receives an input of the inverted clock signal CLKB.

[0048] The switch SW2 is connected between the node NY and the node NC, and receives an input of the positive phase clock signal CLK.

[0049] The switch SW5 is connected between the node NA1 and the node NB0 , and receives an input of the inverted clock signal CLKB.

[0050] The switch SW6 is connected between the node NA0 and the node NB1 , and receives input of the positive phase clock signal CLK.

[0051] The switches SW1 to SW6 constitute a switch control circuit for controlling the connection relationship between the current sources CS1, CS2 and the fixed voltage node (fixed voltage VSS), the capacitance elements C1, C2 and the resistance element R1.

[0052] The resistor element R1 is connected between the node NC and the fixed voltage node (fixed voltage VSS). The resistor element R1 is a variable resistor element with an adjustable resistance value. The oscillation frequency can be adjusted by adjusting the resistance value. The oscillation frequency can be adjusted not only by adjusting the resistance value, but also by adjusting the capacitance value of the capacitor elements C1 and C2. Specifically, the capacitance value of the capacitor elements C1 and C2 can be adjusted by adding an adjustment mechanism to the capacitor elements C1 and C2, or the oscillation frequency can be adjusted by adjusting the capacitance value of the capacitor elements C1 and C2 and the resistance value of the resistor element R1.

[0053] (Operation of Oscillator Circuit) Next, the operation of the oscillator circuit will be described.

[0054] The switches SW1 , SW4 , and SW5 are controlled by the inverted clock signal CLKB, and are controlled to be turned on when, for example, the inverted clock signal CLKB is at a high level.

[0055] The switches SW2 , SW3 , and SW6 are controlled by the positive-phase clock signal CLK, and are controlled to be turned on when, for example, the positive-phase clock signal CLK is at a high level.

[0056] When the positive phase clock signal CLK is at a high level, switches SW2, SW3 and SW6 are turned on, and switches SW1, SW4 and SW5 are turned off. When the negative phase clock signal CLK is at a high level, switches SW2, SW3 and SW6 are turned off, and switches SW1, SW4 and SW5 are turned on.

[0057] Figure 2 1 is a diagram for explaining an equivalent circuit when the positive phase clock signal CLK of the oscillator circuit 100 according to the first embodiment is at a high level.

[0058] like Figure 2 As shown, the capacitance element C1 is charged by a current of 0.5Ic of the constant current Ic provided by the current source CS1. Therefore, the potential of the node NA0 rises in proportion to time.

[0059] The remaining 0.5Ic of the constant current I provided by the current source CS1 discharges the charge stored in the capacitive element C2.

[0060] A current of 1.5Ic (a sum of a current of 0.5Ic discharged from the capacitance element C2 and a current Ic supplied from the current source CS2) flows to the resistance element R1.

[0061] As a result, the potential of the node NY becomes a constant voltage determined by the resistance value of the node resistance element R1 and the value of the current flowing to the node resistance element R1 .

[0062] When the potential of the node NX rising with time reaches the potential of the node NY, the output of the comparator CP is inverted. The positive clock signal CLK output from the inverter IV0 changes from high level to low level. The negative clock signal CLKB output from the inverter IV1 changes from low level to high level.

[0063] Figure 3 1 is a diagram for explaining an equivalent circuit when the inverted clock signal CLKB of the oscillator circuit 100 according to the first embodiment is at a high level.

[0064] like Figure 3 As shown, in the constant current Ic provided by the current source CS2, the capacitance element C2 is charged by a current of 0.5Ic. As a result, the potential of the node NB0 rises proportionally with time.

[0065] The remaining current 0.5Ic of the constant current Ic provided by the current source CS2 discharges the charge stored in the capacitance element C1.

[0066] A current 1.5Ic, which is the sum of a current 0.5I discharged from the capacitance element C1 and a current Ic supplied from the current source CS1, flows to the resistance element R1.

[0067] As a result, the potential of the node NX becomes a constant voltage determined by the resistance value of the resistance element R1 and the value of the current flowing through the resistance element R1 .

[0068] When the potential of the node NY rising with time reaches the potential of the node NX, the output of the comparator CP is inverted. The positive clock signal CLK output from the inverter IV0 changes from low level to high level. The negative clock signal CLKB output from the inverter IV1 changes from high level to low level.

[0069] In this way, the positive phase clock signal CLK repeats the transition from the high level to the low level and from the low level to the high level. Therefore, the oscillator circuit 100 performs the oscillation operation through this process.

[0070] Figure 4 is a diagram for explaining changes in the potentials of the nodes NX and NY of the oscillator circuit 100 according to the first embodiment.

[0071] like Figure 4 As shown, the period until the potential of the node NX reaches the constant voltage (reference voltage) of the node NY corresponds to a period of 1 / 2 of the oscillation period. The capacitance element C1 is charged by a current of 0.5Ic, and the potential of the node NX rises.

[0072] Therefore, when the oscillation period is defined as T, the capacitance value of the capacitance elements C1 and C2 is defined as C, the resistance value of the resistance element R1 is defined as R, and the current value of the current sources CS1 and CS2 is defined as Ic, the relationship of the following formula (2) is established.

[0073] 0.5Ic(T / 2) / C=1.5Ic·R (2)

[0074] Therefore, the oscillation period T is determined as shown in the formula (3), and is 6 times the product of the resistance value R and the capacitance C.

[0075] T=6RC (3)

[0076] like Figure 4 As shown, in an actual circuit, the comparator CP has a delay time from the time when the input signal changes until the output signal changes. As a result, overshoot occurs in the nodes NX and NY.

[0077] Figure 5 is a diagram for explaining transition of the voltage between the terminals of the capacitance elements C1 and C2 of the oscillator circuit 100 according to the first embodiment.

[0078] like Figure 5 As shown, the terminal voltage of the capacitor elements C1 and C2 is ideally a triangular wave that reciprocates between 0 and the reference voltage. On the other hand, as shown in the figure, since two undershoots and two overshoots occur, the cycle is delayed by this amount.

[0079] Taking this into consideration, when the delay time of the comparator CP is Td, the oscillation period Ta of the oscillator circuit 100 is determined by the following equation (4).

[0080] Ta=6RC+4Td (4)

[0081] (Influence of Oscillation Frequency Accuracy) The delay time Td of the comparator CP is changed by noise components such as transistor elements constituting the comparator CP. The main item of power noise is the fluctuation of the delay time Td due to low-frequency noise. In order to improve the frequency accuracy, it is necessary to reduce the ratio of Td in the oscillation period Ta.

[0082] As a comparative example, in the conventional method, the oscillation period considering the delay time of the comparator is determined by the following equation (5).

[0083] Ta=2RC+2Td (5)

[0084] Therefore, compared with the comparator according to the comparative example, the product of RC when the same frequency is set can be 1 / 3, and the circuit area can be significantly reduced.

[0085] In addition, according to the oscillator circuit 100 according to the first embodiment, the contribution rate of the delay time Td of the comparator CP in the oscillation period is smaller than the contribution rate of the delay time Td of the comparator according to the comparative example. Therefore, the deterioration of the accuracy of the oscillation frequency caused by the change of the delay time of the comparator CP can be suppressed.

[0086] <Second Embodiment>

[0087] Figure 6 is a diagram for explaining the configuration of an oscillation circuit 200 according to the second embodiment.

[0088] refer to Figure 6 The oscillator circuit 200 includes current sources CS1 and CS2, a resistor element R1, capacitor elements C1 and C2, switches SW1 to SW2, three output switches (SP3TSW) ST1-ST4, a comparison unit CMP, and a decoder DC. The switches SW1 to SW6 receive input of a positive phase clock signal CLK or a negative phase clock signal CLKB to perform a switching operation.

[0089] The comparison unit CMP includes a comparator CP and inverters IV0 and IV1. The inverter IV0 inverts the output of the comparator CP to output a positive-phase clock signal CLK.

[0090] Inverter IV1 inverts the input of inverter IV0 and outputs an inverted clock signal CLKB.

[0091] In the capacitor element C1, one side is the node NA0, and the other side is the node NA1. In the capacitor element C2, one side is the node NB0, and the other side is the node NB1.

[0092] For example, the current sources CS1 , CS2 are configured by a current mirror circuit using MOS transistors.

[0093] The switches SW1 and SW2 are formed of, for example, MOS transistors. The current source CS1 is connected between a power supply node (power supply voltage VDD) and a node NX, and supplies a constant current Ic.

[0094] The current source CS2 is connected between the power supply node (power supply voltage VDD) and the node NY, and provides a constant current Ic.

[0095] One input terminal of the comparator CP is connected to the node NX, and the other input terminal is connected to the node NY. The comparator CP compares the potential of the node NX with the potential of the node NY, and outputs a signal corresponding to the comparison result.

[0096] Node NA0 of capacitance element C1 is connected to three-output switch ST1. Three-output switch ST1 connects node NA0 to any one of a fixed voltage node (fixed voltage VSS), node NX and node NY according to switch control signals S0, S2 and S4 output from decoder DC.

[0097] Node NA1 of capacitance element C1 is connected to three-output switch ST2. Three-output switch ST2 connects node NA1 to any one of a fixed voltage node (fixed voltage VSS), node NX and node NY according to switch control signals S1, S3 and S5 output from decoder DC.

[0098] The node NB0 of the capacitance element C2 is connected to the three-output switch ST3. The three-output switch ST3 connects the node NB0 to any one of the fixed voltage node (fixed voltage VSS), the node NX and the node NY according to the switch control signals S6, S8 and S10 output from the decoder DC.

[0099] The node NB1 of the capacitance element C2 is connected to the three-output switch ST4. The three-output switch ST4 connects the node NB1 to any one of the fixed voltage node (fixed voltage VSS), the node NX and the node NY according to the switch control signals S7, S9 and S11 output from the decoder DC.

[0100] The resistor element R1 is connected between the node NC and the fixed voltage node (fixed voltage VSS). The resistor element R1 is a variable resistor element with an adjustable resistance value. The oscillation frequency can be adjusted by adjusting the resistance value.

[0101] The switch SW1 is connected between the node NX and the node NC, and receives an input of the inverted clock signal CLKB.

[0102] The switch SW2 is connected between the node NY and the node NC, and receives an input of the positive phase clock signal CLK.

[0103] Switches SW1 and SW2, three output switches ST1 to ST4 and a decoder DC constitute a switch control circuit for controlling the connection relationship between current sources CS1 and CS2, a fixed voltage node (fixed voltage VSS), capacitor elements C1, C2 and resistor element R1.

[0104] Figure 7 2 is a circuit diagram for explaining the circuit configuration of a decoder DC according to the second embodiment. Figure 7 The decoder DC includes frequency dividers 40 and 42, inverters IV2 and IV3, and AND circuits AD0 to AD11.

[0105] The frequency divider 40 divides the frequency of the positive phase clock signal CLK by 1 / 2, and outputs the divided frequency as the switch control signal S0. The switch control signal S0 (high level) connects the node NA0 and the node NX.

[0106] The inverter IV2 inverts the output of the frequency divider 40 and outputs the inverted output as the switch control signal S1. The switch control signal S1 (high level) connects the node NA1 and the node NX.

[0107] AND circuit AD0 outputs the result of AND logic operation of the output of inverter IV2 and inverted clock signal CLKB as switch control signal S2. Switch control signal S2 (high level) connects node NA0 and node NY.

[0108] AND circuit AD1 outputs the result of AND logic operation of the output of frequency divider 40 and inverted clock signal CLKB as switch control signal S3. Switch control signal S3 (high level) connects node NA1 and node NY.

[0109] AND circuit AD2 outputs the AND logic operation result of the output of inverter IV2 and positive phase clock signal CLK as switch control signal S4. Switch control signal S4 (high level) connects node NA0 and fixed voltage node (fixed voltage VSS).

[0110] AND circuit AD3 outputs the result of AND logic operation of the output of frequency divider 40 and positive phase clock signal CLK as switch control signal S5. Switch control signal S5 (high level) connects node NA1 and fixed voltage node (fixed voltage VSS).

[0111] The frequency divider 42 divides the frequency of the inverted clock signal CLKB by 1 / 2, and outputs the divided frequency as the switch control signal S6. The switch control signal S6 (high level) connects the node NB0 and the node NY.

[0112] The inverter IV3 inverts the output of the frequency divider 42 and outputs the inverted output as the switch control signal S7. The switch control signal S7 (high level) connects the node NB1 and the node NY.

[0113] AND circuit AD4 outputs the result of AND logic operation of the output of inverter IV3 and positive phase clock signal CLK as switch control signal S8. Switch control signal S8 (high level) connects node NB0 and node NX.

[0114] AND circuit AD5 outputs the result of AND logic operation of the output of frequency divider 42 and positive phase clock signal CLK as switch control signal S9. Switch control signal S9 (high level) connects node NB1 and node NX.

[0115] AND circuit AD6 outputs the AND logic result of the output of inverter IV3 and inverted clock signal CLKB as switch control signal S10. Switch control signal S10 (high level) connects node NB0 and fixed voltage node (fixed voltage VSS).

[0116] AND circuit AD7 outputs the result of AND logic operation of the output of frequency divider 42 and inverted clock signal CLKB as switch control signal S11. Switch control signal S11 (high level) connects node NB1 and fixed voltage node (fixed voltage VSS).

[0117] Figure 8 is a diagram for explaining switch control signals S0 to S11 output from a decoder DC according to the second embodiment.

[0118] Reference Figure 8 , in time T0, the positive phase clock signal CLK is set to a high level, and the negative phase clock signal BCLK is set to a low level.

[0119] Accordingly, the switch control signal S0 is set to a high level. The switch control signal S2 is set to a low level. The switch control signal S4 remains at a low level. The three-output switch ST1 connects the node NA0 and the node NX.

[0120] The switch control signal S1 is set to a low level. The switch control signal S3 is kept at a low level. The switch control signal S5 is set to a high level. The three-output switch ST2 connects the node NA1 and a fixed voltage node (fixed voltage VSS).

[0121] The switch control signal S8 is kept at a low level. The switch control signal S6 is kept at a high level. The switch control signal S10 is kept at a low level. The switch ST3 connects the node NB0 and the node NY.

[0122] The switch control signal S9 is set high. The switch control signal S7 is kept low. The switch control signal S11 is set low. The switch ST4 connects the node NB1 and the node NX.

[0123] This sets the first connection state. Next, in time T1, the positive phase clock signal CLK is set to a low level, and the negative phase clock signal BCLK is set to a high level.

[0124] Accordingly, the switch control signal S0 maintains a high level. The switch control signal S2 maintains a low level. The switch control signal S4 maintains a low level. The three-output switch ST1 connects the node NA0 and the node NX.

[0125] The switch control signal S1 is kept at a low level. The switch control signal S3 is set to a high level. The switch control signal S5 is kept at a low level. The three-output switch ST2 connects the node NA1 and the node NY.

[0126] The switch control signal S8 is maintained at a low level. The switch control signal S6 is set to a low level. The switch control signal S10 is set to a high level. The switch ST3 connects the node NB0 and the fixed voltage node (fixed voltage VSS).

[0127] The switch control signal S9 is set to low. The switch control signal S7 is set to high. The switch control signal S11 is kept at a low level. The switch ST4 connects the node NB1 and the node NY.

[0128] This sets the second connection state. In time T2, the positive phase clock signal CLK is set to a high level, and the negative phase clock signal BCLK is set to a low level.

[0129] Accordingly, the switch control signal S0 is set to a low level. The switch control signal S2 remains at a low level. The switch control signal S4 is set to a high level. The three-output switch ST1 connects the node NA0 and the fixed voltage node (fixed voltage VSS).

[0130] The switch control signal S1 is set to a high level. The switch control signal S3 is set to a low level. The switch control signal S5 remains at a low level. The three-output switch ST2 connects the node NA1 and the node NX.

[0131] The switch control signal S8 is set to a high level. The switch control signal S6 is kept at a low level. The switch control signal S10 is set to a low level. The switch ST3 connects the node NB0 and the node NX.

[0132] The switch control signal S9 is kept at a low level. The switch control signal S7 is set to a high level. The switch control signal S11 is kept at a low level. The switch ST4 connects the node NB1 and the node NY.

[0133] This sets the third connection state. In time T3, the positive phase clock signal CLK is set to a low level, and the negative phase clock signal BCLK is set to a high level.

[0134] Accordingly, the switch control signal S0 is kept at a low level. The switch control signal S2 is set to a high level. The switch control signal S4 is set to a low level. The three-output switch ST1 connects the node NA0 and the node NY.

[0135] The switch control signal S1 maintains a high level. The switch control signal S3 maintains a low level. The switch control signal S5 maintains a low level. The three-output switch ST2 connects the node NA1 and the node NX.

[0136] The switch control signal S8 is set to a low level. The switch control signal S6 is set to a high level. The switch control signal S10 is kept at a low level. The switch ST3 connects the node NB0 and the node NY.

[0137] The switch control signal S9 is maintained at a low level. The switch control signal S7 is set to a low level. The switch control signal S1 is set to a high level. The switch ST4 connects the node NB1 and the fixed voltage node (fixed voltage VSS).

[0138] This sets the fourth connection state. The connection state at time T4 is set to the first connection state, similar to the connection state at time T0. The connection state at time T5 is set to the second connection state, similar to the connection state at time T1. The connection state at time T6 is set to the third connection state, similar to the connection state at time T2. The connection state at time T7 is set to the fourth connection state, similar to the connection state at time T3. The same applies to the time after time T8.

[0139] Next, the operation of the oscillator circuit 200 of the second embodiment will be described. Figures 9 to 12 The equivalent circuit for each connection state is shown.

[0140] Fig. 9 is a diagram showing an equivalent circuit of a first connection state of the oscillator circuit 200 according to the second embodiment.

[0141] In the first connection state, the three-output switch ST1 connects the node NA0 and the node NX. The three-output switch ST2 connects the node NA1 and the fixed voltage node (fixed voltage VSS). The switch ST3 connects the node NB0 and the node NY. The switch ST4 connects the node NB1 and the node NX.

[0142] like Fig. 9 As shown, the capacitor C1 is charged by 0.5Ic of the constant current Ic provided by the current source CS1. Therefore, the potential of the node NA0 rises proportionally with time.

[0143] The remaining current 0.5Ic of the constant current Ic provided by the current source CS1 discharges the charge stored in the capacitance element C2.

[0144] A current 1.5Ic, which is the sum of a current 0.5Ic discharged from the capacitance element C2 and a current Ic supplied from the current source CS2, flows to the resistance element R1.

[0145] As a result, the potential of the node NY becomes a constant voltage determined by the resistance value of the resistance element R1 and the value of the current flowing through the resistance element R1 .

[0146] When the potential of the node NX rising with time reaches the potential of the node NY, the output of the comparator CP is inverted. The positive clock signal CLK output from the inverter IV0 changes from high level to low level. The negative clock signal CLKB output from the inverter IV1 changes from low level to high level.

[0147] Fig.10 2 is a diagram for explaining an equivalent circuit of the second connection state of the oscillator circuit 200 according to the second embodiment.

[0148] In the second connection state, the three-output switch ST1 connects the node NA0 and the node NX. The three-output switch ST2 connects the node NA1 and the node NY. The switch ST3 connects the node NB0 and the fixed voltage node (fixed voltage VSS). The switch ST4 connects the node NB1 and the node NY.

[0149] like Fig.10 As shown, the capacitance element C2 is charged by a current of 0.5Ic of the constant current Ic supplied from the current source CS2. As a result, the potential of the node NB1 rises in proportion to time.

[0150] The remaining current 0.5Ic of the constant current Ic provided by the current source CS2 discharges the charge stored in the capacitance element C1.

[0151] A current 1.5Ic, which is the sum of a current 0.5I discharged from the capacitance element C1 and a current Ic supplied from the current source CS1, flows to the resistance element R1.

[0152] As a result, the potential of the node NX becomes a constant voltage determined by the resistance value of the resistance element R1 and the value of the current flowing through the resistance element R1 .

[0153] When the potential of node NX, which rises with time, reaches the potential of node NY, the output of comparator CP is inverted. The positive clock signal CLK output from inverter IV0 changes from low level to high level. The negative clock signal CLKB output from inverter IV1 changes from high level to low level.

[0154] Fig.11 is a diagram for explaining an equivalent circuit of the third connection state of the oscillator circuit 200 according to the second embodiment.

[0155] In the third connection state, the three-output switch ST1 connects the node NA0 and the node NX. The three-output switch ST2 connects the node NA1 and the fixed voltage node (fixed voltage VSS). The switch ST3 connects the node NB0 and the node NY. The switch ST4 connects the node NB1 and the node NX.

[0156] like Fig.11 As shown, the capacitance element C1 is charged by a current of 0.5Ic of the constant current Ic supplied from the current source CS1. Therefore, the potential of the node NA0 rises in proportion to time.

[0157] The remaining current 0.5Ic of the constant current Ic provided by the current source CS1 discharges the charge stored in the capacitance element C2.

[0158] A current 1.5Ic, which is the sum of a current 0.5Ic discharged from the capacitance element C2 and a current Ic supplied from the current source CS2, flows to the resistance element R1.

[0159] As a result, the potential of the node NY becomes a constant voltage determined by the resistance value of the node resistance element R1 and the value of the current flowing to the node resistance element R1 .

[0160] When the potential of the node NX rising with time reaches the potential of the node NY, the output of the comparator CP is inverted. The positive clock signal CLK output from the inverter IV0 changes from high level to low level. The negative clock signal CLKB output from the inverter IV1 changes from low level to high level.

[0161] Fig.12 is a diagram for explaining an equivalent circuit of the fourth connection state of the oscillator circuit 200 according to the second embodiment.

[0162] In the fourth connection state, the three-output switch ST1 connects the node NA0 and the node NX. The three-output switch ST2 connects the node NA1 and the node NY. The switch ST3 connects the node NB0 and the fixed voltage node (fixed voltage VSS). The switch ST4 connects the node NB1 and the node NY.

[0163] like Fig.12As shown, the capacitance element C2 is charged by the current 0.5Ic of the constant current Ic supplied from the current source CS2. As a result, the potential of the node NB1 rises in proportion to time.

[0164] The remaining current 0.5Ic of the constant current Ic provided by the current source CS2 discharges the charge stored in the capacitance element C1.

[0165] A current 1.5Ic, which is the sum of a current 0.5I discharged from the capacitance element C1 and a current Ic supplied from the current source CS1, flows to the resistance element R1.

[0166] As a result, the potential of the node NX becomes a constant voltage determined by the resistance value of the node resistance element R1 and the value of the current flowing to the node resistance element R1.

[0167] When the potential of node NX, which rises with time, reaches the potential of node NY, the output of comparator CP is inverted. The positive clock signal CLK output from inverter IV0 changes from low level to high level. The negative clock signal CLKB output from inverter IV1 changes from high level to low level.

[0168] In this way, the positive phase clock signal CLK repeats the transition from the high level to the low level and from the low level to the high level. Therefore, the oscillator circuit 200 performs the oscillation operation through this process.

[0169] Fig.13 is a diagram for explaining changes in the potentials of the nodes NX and NY of the oscillator circuit 200 according to the second embodiment.

[0170] like Fig.13 As shown, the period until the potential of the node NX reaches the constant voltage (reference voltage) of the node NY corresponds to a period of 1 / 2 of the oscillation period. The capacitance element C1 is charged by a current of 0.5Ic, and the potential of the node NX rises.

[0171] Therefore, when the oscillation period is T, the capacitance value of the capacitance elements C1, C2 is C, the resistance value of the resistance element R1 is R, and the current value of the current sources CS1, CS2 is Ic, the ideal oscillation period T is 6RC, similar to the first embodiment.

[0172] On the other hand, in the actual circuit, similarly to the first embodiment, the comparator CP has a delay time from when the input signal changes to when the output signal changes. As a result, overshoot occurs in the nodes NX and NY.

[0173] Fig.14 is a diagram for explaining transition of the voltage between the terminals of the capacitance elements C1 and C2 of the oscillator circuit 200 according to the second embodiment.

[0174] like Fig.14 As shown, the terminal voltages of the capacitor elements C1 and C2 ideally have a triangular wave that reciprocates between 0 and the reference voltage.

[0175] In the oscillator circuit 200 according to the second embodiment, the delay of the delay time Td occurs within a half period. Taking this into consideration, when the delay time of the comparator CP is Td, the oscillation period Ta of the oscillator circuit 100 is determined by the following equation (6).

[0176] Ta=6RC+2Td (6)

[0177] Therefore, the oscillator circuit 200 according to the second embodiment has less influence of delay time than the configuration of the oscillator circuit 100 according to the first embodiment.

[0178] The oscillator circuit 200 according to the second embodiment uses a method in which the connection polarity of the capacitance element that makes the voltage between the terminals close to zero is reversed when the output of the comparator CP is inverted. This makes it possible to eliminate the extra charge.

[0179] Fig.15 1 is a diagram for explaining a state when the oscillator circuit 200 according to the second embodiment is switched from the first connection state to the second connection state.

[0180] like Fig.15 As shown, the voltage between the terminals of the node NA0 and the node NA1 of the capacitance element C1 is set to the reference voltage VREF + the overshoot voltage ΔV by the influence of the delay of the comparator CP. At this time, the terminal voltage between the node NB1 and the node NB0 of the capacitance element C2 is set to the voltage ΔV.

[0181] Fig.16 2 is a diagram for explaining a state when the second connection state of the oscillator circuit 200 is switched according to the second embodiment.

[0182] like Fig.16 As shown, according to the switching of the second connection state, the potential of the node NY is set to the voltage ΔV of the terminal voltage between the node NB1 and the node NB0 of the capacitance element C2.

[0183] The potential of the node NX is set to the reference voltage VREF+2ΔV. Since the potential of the node NX converges to the reference voltage VREF, the component of the voltage ΔV originally present at the node NY also disappears due to the capacitive voltage division in the process. That is, the overshoot voltage ΔV is eliminated.

[0184] Similarly, when referring to Fig.11 The third connection state described is changed to reference Fig.12 The same phenomenon also occurs in the fourth connection state described.

[0185] Therefore, compared with the oscillation circuit 100 according to the first embodiment, the output noise caused by the delay time variation of the comparator CP is halved, and thus the oscillator circuit 200 according to the second embodiment can further suppress the deterioration of the oscillation frequency accuracy.

[0186] Although the present disclosure has been specifically described based on the above-mentioned embodiments, the present disclosure is not limited to these embodiments, and it goes without saying that various modifications can be made without departing from the gist thereof.

Claims

1. An oscillator circuit comprising: First constant current source; The second constant current source; a comparator having a first input terminal connected to the first constant current source and a second input terminal connected to the second constant current source; a first capacitive element having a first terminal and a second terminal; a second capacitive element having a third terminal and a fourth terminal; a resistance element having a fifth terminal connected to one of the first constant current source and the second constant current source and a sixth terminal connected to a fixed voltage node; as well as wherein, in a first state, the first terminal is connected to the first constant current source, the second terminal is connected to the fixed voltage node, the third terminal is connected to the second constant current source, the fourth terminal is connected to the first constant current source, the fifth terminal is connected to the second constant current source, and In the second state, the first terminal is connected to the second constant current source, the second terminal is connected to the first constant current source, the third terminal is connected to the second constant current source, the fourth terminal is connected to the fixed voltage node, and the fifth terminal is connected to the first constant current source.

2. The oscillator circuit according to claim 1 further includes a switch control circuit, which controls the connection relationship between the first constant current source, the second constant current source, the fixed voltage node, the first capacitor element, the second capacitor element and the resistor element based on the output signal of the comparator.

3. An oscillator circuit comprising: First constant current source; The second constant current source; a comparator having one input terminal connected to the first constant current source and another input terminal connected to the second constant current source; a first capacitive element; a second capacitive element; a resistance element having one side connected to one of the first constant current source and the second constant current source and the other terminal connected to a fixed voltage node; as well as a switch control circuit, which controls the connection relationship between the first constant current source, the second constant current source, the fixed voltage node, the first capacitor, the second capacitor and the resistor based on the output signal of the comparator; The switch control circuit switches between a first state and a second state. wherein, in the first state, one side of the first capacitive element is connected to the first constant current source, the other side of the first capacitive element is connected to the fixed voltage node, one side of the second capacitive element is connected to the second constant current source, the other side of the second capacitive element is connected to the first constant current source, and the one side of the resistive element is connected to the second constant current source, and Wherein, in the second state, the one side of the first capacitor element is connected to the second constant current source, the other side of the first capacitor element is connected to the first constant current source, the one side of the second capacitor element is connected to the second constant current source, the other side of the second capacitor element is connected to the fixed voltage node, and the one side of the resistor element is connected to the first constant current source.

4. The oscillator circuit according to claim 3, in, The polarities of the current flowing through the first capacitive element are opposite to each other in the first state and in the second state, and The polarities of the current flowing through the second capacitive element are opposite to each other in the first state and in the second state.

5. The oscillator circuit according to claim 3, in, When transitioning from the first state to the second state, the polarity of the current flowing through the first capacitive element is reversed, and When the second state is changed to the first state, the polarity of the current flowing through the second capacitor element is reversed.

6. The oscillator circuit according to any one of claims 3 to 5, in, The resistance element is a variable resistance element with adjustable resistance value.

7. An oscillator circuit comprising: The first constant current source, The second constant current source, Comparators, including: an input terminal connected to the first constant current source; and another input terminal connected to the second constant current source; a first capacitive element; a second capacitive element; Resistor elements, including: a side connected to one side of the first constant current source and the second constant current source; The other side connected to the fixed voltage node, a switch control circuit, controlling the connection between the first capacitor element, the second capacitor element and the resistor element; The switch control circuit switches the first to fourth states according to the output of the comparator. wherein, in a first state, one side of the first capacitive element is connected to the first constant current source, the other side of the first capacitive element is connected to the fixed voltage node, one side of the second capacitive element is connected to the second constant current source, the other side of the second capacitive element is connected to the first constant current source, and the one side of the resistive element is connected to the second constant current source, wherein, in a second state, one side of the first capacitive element is connected to the first constant current source, the other side of the first capacitive element is connected to the second constant current source, one side of the second capacitive element is connected to the fixed voltage node, the other side of the second capacitive element is connected to the second constant current source, and the one side of the resistive element is connected to the first constant current source, wherein, in a third state, one side of the first capacitive element is connected to the fixed voltage node, the other side of the first capacitive element is connected to the first constant current source, one side of the second capacitive element is connected to the first constant current source, the other side of the second capacitive element is connected to the second constant current source, and the one side of the resistive element is connected to the second constant current source, and In which, in a fourth state, one side of the first capacitor element is connected to the second constant current source, the other side of the first capacitor element is connected to the first constant current source, one side of the second capacitor element is connected to the second constant current source, the other side of the second capacitor element is connected to the fixed voltage node, and the one side of the resistor element is connected to the first constant current source.

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