Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, comprising: providing a substrate, wherein the substrate has a first conductive structure; forming a first dielectric layer on the substrate; forming a first opening in the first dielectric layer and extending into the first conductive structure, wherein the bottom surface of the first opening is lower than the top surface of the first conductive structure; and forming a plug structure in the first opening. In the semiconductor structure of the technical solution of the present invention, the first opening is located in the first dielectric layer and extends into the first conductive structure, wherein the bottom surface of the first opening is lower than the top surface of the first conductive structure; and a plug structure is located in the first opening. The first opening extending into the first conductive structure increases the contact area between the first conductive structure and the plug structure, thereby reducing the contact resistance between the first conductive structure and the plug structure, thereby improving the electrical performance of the semiconductor structure finally formed.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] With the continuous advancement of semiconductor technology, the characteristic size of semiconductor devices has gradually become smaller. The reduction of critical size means that more transistors can be arranged on the chip, while putting higher requirements on semiconductor technology.

[0003] Since metal has good electrical conductivity, in semiconductor technology, metal plugs are often used to electrically connect semiconductor connectors (e.g., gate and source / drain doped regions) to external circuits. However, due to the large difference in Fermi levels between metal and semiconductor, the potential barrier between the metal plug and the semiconductor connector is high, resulting in a large contact resistance between the metal plug and the semiconductor connector. The prior art reduces the contact resistance and improves the performance of the semiconductor structure by forming a metal silicide between the metal plug and the semiconductor connector.

[0004] However, the semiconductor structure formed by the prior art still has the problem of large contact resistance between the metal plug and the semiconductor connector. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, which can reduce the contact resistance between the first conductive structure and the plug structure and improve the electrical performance of the formed semiconductor structure.

[0006] To solve the above problems, the present invention provides a semiconductor structure, comprising: a substrate, wherein the substrate has a first conductive structure, and the first conductive structure is exposed on the surface of the substrate; a first dielectric layer located on the substrate; a first opening located in the first dielectric layer and extending into the first conductive structure, and the bottom surface of the first opening is lower than the top surface of the first conductive structure; and a plug structure located in the first opening.

[0007] Optionally, the first conductive structure includes: a first barrier layer and a first conductive layer located on the first barrier layer.

[0008] Optionally, the thickness of the first barrier layer is 5 angstroms to 40 angstroms.

[0009] Optionally, the plug structure includes: a second barrier layer located on the sidewalls and bottom surface of the first opening, and a conductive plug located on the surface of the second barrier layer and filling the first opening.

[0010] Optionally, the second barrier layer has a thickness of 5 angstroms to 40 angstroms.

[0011] Optionally, the method further includes: a second opening located in the first dielectric layer, the first opening is located at the bottom of the second opening, and the second opening is connected to the first opening.

[0012] Optionally, it also includes: a second conductive structure located in the second opening.

[0013] Optionally, the second conductive structure includes: a third barrier layer located on the sidewalls and bottom surface of the second opening, and a second conductive layer located on the surface of the third barrier layer and filling the second opening.

[0014] Optionally, the third barrier layer has a thickness of 5 angstroms to 40 angstroms.

[0015] Optionally, the first barrier layer is a single-layer or multi-layer structure.

[0016] Optionally, the second barrier layer is a single-layer or multi-layer structure.

[0017] Optionally, the third barrier layer is a single-layer or multi-layer structure.

[0018] Optionally, a ratio of a distance from the bottom of the first opening to the top surface of the first conductive structure to a distance from the bottom of the first conductive structure to the top surface of the first conductive structure is 1:4 to 1.5:1.

[0019] Correspondingly, the present invention also provides a method for forming any of the above-mentioned semiconductor structures, comprising: providing a substrate, wherein the substrate has a first conductive structure, and the first conductive structure is exposed on the surface of the substrate; forming a first dielectric layer on the substrate; forming a first opening in the first dielectric layer and extending into the first conductive structure, and the bottom surface of the first opening is lower than the top surface of the first conductive structure; and forming a plug structure in the first opening.

[0020] Optionally, before forming the first opening, the method further includes: forming a second opening in the first dielectric layer; the first opening is located at the bottom of the second opening, and the second opening is connected to the first opening.

[0021] Optionally, the method for forming the first opening includes: forming a first mask layer on the first dielectric layer and in the second opening; forming a first patterned layer on the first mask layer, the first patterned layer exposing a portion of the top surface of the first mask layer in the second opening; etching the first mask layer and the first dielectric layer using the first patterned layer as a mask until a portion of the top surface of the first conductive structure is exposed, thereby forming an initial first opening in the first dielectric layer; etching the top surface of the first conductive structure exposed by the initial first opening, thereby forming the first opening in the first dielectric layer and in the first conductive structure; after forming the first opening, removing the first patterned layer and the first mask layer.

[0022] Optionally, a wet etching process is used to etch the top surface of the first conductive structure exposed by the initial first opening.

[0023] Optionally, while forming the plug structure, the method further includes: forming a second conductive structure in the second opening.

[0024] Optionally, the plug structure includes: a second barrier layer located on the side walls and bottom surface of the first opening, and a conductive plug located on the surface of the second barrier layer and filling the first opening; the second conductive structure includes: a third barrier layer located on the side walls and bottom surface of the second opening, and a second conductive layer located on the surface of the third barrier layer and filling the second opening.

[0025] Optionally, the method for forming the plug structure and the second conductive structure includes: forming an initial barrier layer on the bottom and side wall surfaces of the first opening and the second opening, and the top surface of the first dielectric layer; forming an initial conductive structure on the initial barrier layer; and planarizing the initial barrier layer and the initial conductive structure until the top surface of the first dielectric layer is exposed, thereby forming the plug structure and the second conductive structure.

[0026] Optionally, the first conductive structure includes: a first barrier layer and a first conductive layer located on the first barrier layer.

[0027] Optionally, the thickness of the first barrier layer is 5 angstroms to 40 angstroms.

[0028] Optionally, the second barrier layer has a thickness of 5 angstroms to 40 angstroms.

[0029] Optionally, the thickness of the third barrier layer is 5 angstroms to 40 angstroms.

[0030] Optionally, the first barrier layer is a single-layer or multi-layer structure.

[0031] Optionally, the second barrier layer is a single-layer or multi-layer structure.

[0032] Optionally, the third barrier layer is a single-layer or multi-layer structure.

[0033] Optionally, a ratio of a distance from the bottom of the first opening to the top surface of the first conductive structure to a distance from the bottom of the first conductive structure to the top surface of the first conductive structure is 1:4 to 1.5:1.

[0034] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0035] In the semiconductor structure of the technical solution of the present invention, a first opening is located in the first dielectric layer and extends into the first conductive structure, and the bottom surface of the first opening is lower than the top surface of the first conductive structure; a plug structure is located in the first opening. The first opening extending into the first conductive structure increases the contact area between the first conductive structure and the plug structure, thereby reducing the contact resistance between the first conductive structure and the plug structure, thereby improving the electrical performance of the semiconductor structure finally formed.

[0036] In the method for forming a semiconductor structure of the technical solution of the present invention, while forming the plug structure, it also includes: forming a second conductive structure in the second opening. By forming the plug structure and the second conductive structure at the same time, the process steps can be reduced and the production efficiency can be effectively improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figures 1 to 3 It is a schematic diagram of the structure of a semiconductor structure;

[0038] Figures 4 to 9 It is a schematic structural diagram of each step of an embodiment of a semiconductor structure and a method for forming the same according to the present invention. DETAILED DESCRIPTION

[0039] As described in the background art, the semiconductor structure formed by the prior art still has the problem of large contact resistance between the metal plug and the semiconductor connector.

[0040] Figures 1 to 3 It is a schematic diagram of the structures of various steps in the formation process of a semiconductor structure.

[0041] Please refer to Figure 1 , providing a substrate 100 , wherein the substrate 100 has a first conductive structure 101 therein, and the first conductive structure 101 is exposed on the surface of the substrate 100 .

[0042] Please refer to Figure 2, forming a first dielectric layer 102 on the substrate 100 ; forming a first opening 103 in the first dielectric layer 102 , wherein the first opening 103 exposes a top surface of the first conductive structure 101 .

[0043] Please refer to Figure 3 , a first barrier layer 104 is formed in the first opening 103 ; and a plug structure 106 is formed on the first barrier layer 104 .

[0044] In the above embodiment, although the material of the first barrier layer 104 includes one or more combinations of titanium, titanium nitride, tantalum, tantalum nitride, nickel, magnesium, cobalt, manganese oxide, aluminum oxide and aluminum nitride, the function of the first barrier layer is to reduce the potential barrier between the first conductive structure 101 and the plug structure 105, thereby reducing the contact resistance between the first conductive structure 101 and the plug structure 105, but as the characteristic size of the semiconductor device gradually decreases, the contact area between the first conductive structure 101 and the plug structure 105 will also decrease accordingly. When the contact area between the first conductive structure 101 and the plug structure 105 decreases, the corresponding contact resistance between the first conductive structure 101 and the plug structure 105 will increase, thereby affecting the electrical properties of the semiconductor structure finally formed.

[0045] On this basis, the present invention provides a semiconductor structure and a method for forming the same, wherein a first dielectric layer is formed on the substrate; a first opening is formed in the first dielectric layer and extends into the first conductive structure, wherein the bottom surface of the first opening is lower than the top surface of the first conductive structure; and a plug structure is formed in the first opening. The first opening extending into the first conductive structure increases the contact area between the first conductive structure and the plug structure, thereby reducing the contact resistance between the first conductive structure and the plug structure, thereby improving the electrical performance of the semiconductor structure finally formed.

[0046] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0047] Figures 4 to 9 It is a structural schematic diagram of a formation process of a semiconductor structure according to an embodiment of the present invention.

[0048] Please refer to Figure 4 , providing a substrate 200, wherein the substrate 200 has a first conductive structure 201, and the first conductive structure 201 is exposed on the surface of the substrate 200.

[0049] In this embodiment, the substrate 200 includes a base and a dielectric layer (not shown) located on the base, and the first conductive structure 201 is specifically located in the dielectric layer.

[0050] In this embodiment, the substrate is a single-layer substrate.

[0051] In other embodiments, the substrate may also be an SOI substrate, and the SOI substrate may be a double layer of an insulating substrate and a top single crystal silicon layer, or a sandwich structure with an insulating thin layer as an intermediate layer. When manufacturing a device, only the top thin silicon layer is used as a device manufacturing layer, that is, to form structures such as source, drain, and channel regions. The substrate only plays a supporting role, and the buried device manufacturing layer in the sandwich structure is electrically isolated from the substrate, thereby reducing the influence of the substrate on the device performance.

[0052] In other embodiments, the substrate may also be a fin-type substrate, which includes a semiconductor substrate and a plurality of mutually discrete fins located on the semiconductor substrate. The fin-type field effect transistor formed by the fin-type substrate is a common multi-gate device, which exhibits good gate control capability for channel charge and extends the size of CMOS devices to a smaller range. The structure of the fin-type field effect transistor includes: fins and a dielectric layer located on the surface of the semiconductor substrate, the dielectric layer filling the gaps between the fins and exposing the upper part of the fins; a gate structure located on the surface of the dielectric layer and the top and sidewall surfaces of the fins; and a source region and a drain region in the fins located on both sides of the gate structure.

[0053] The material of the substrate includes silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); it may also include silicon on insulator (SOI), germanium on insulator (GOI); or it may also be other materials, such as III-V group compounds such as gallium arsenide. In this embodiment, the material of the substrate is silicon.

[0054] In this embodiment, the first conductive structure 201 includes: a first barrier layer 202 and a first conductive layer 203 located on the first barrier layer 202 .

[0055] In this embodiment, the method for forming the first conductive structure 201 includes: forming a substrate opening (not shown) in the substrate 200; forming an initial first barrier layer (not shown) on the surface of the substrate opening and the top surface of the substrate 200; forming an initial first conductive layer (not shown) on the initial first barrier layer; and planarizing the initial first barrier layer and the initial first conductive layer until the top surface of the substrate 200 is exposed to form the first conductive structure 201.

[0056] The first barrier layer 202 is annealed to form a metal silicide with the semiconductor material. The contact resistance of the first conductive layer 203 is reduced by the formed metal silicide, thereby improving the electrical properties of the semiconductor structure finally formed. In this embodiment, the first barrier layer 202 is a single-layer structure, and the thickness of the first barrier layer 202 is 5 angstroms to 40 angstroms; in other embodiments, the first barrier layer can also be a multi-layer structure.

[0057] The material of the first barrier layer 202 includes: one or more combinations of titanium, titanium nitride, tantalum, tantalum nitride, nickel, magnesium, cobalt, manganese oxide, aluminum oxide and aluminum nitride. In this embodiment, the material of the first barrier layer 202 is tantalum.

[0058] The material of the first conductive layer 203 includes metal, and the metal includes one or more combinations of copper, cobalt, ruthenium, manganese and aluminum. In this embodiment, the material of the first conductive layer 203 is copper.

[0059] Please refer to Figure 5 , a first dielectric layer 204 is formed on the substrate 200 .

[0060] In this embodiment, the first dielectric layer 204 is a multi-layer structure, including an etch stop layer (not shown) for stopping etching, and an interlayer dielectric layer (not shown) between different conductive layers, and the material of the interlayer dielectric layer includes silicon oxide; in other embodiments, the material of the interlayer dielectric layer may also include one or more combinations of low-k dielectric materials (referring to dielectric materials with a relative dielectric constant lower than 3.9) or ultra-low-k dielectric materials (referring to dielectric materials with a relative dielectric constant lower than 2.5).

[0061] In this embodiment, a first opening is subsequently formed in the first dielectric layer 204 and extends into the first conductive structure, and the bottom surface of the first opening is lower than the top surface of the first conductive structure 201. Before forming the first opening, a second opening is further formed in the first dielectric layer 204. Figure 5 shown.

[0062] Please continue to refer to Figure 5 , a second opening 205 is formed in the first dielectric layer 204 .

[0063] In this embodiment, the method for forming the second opening 205 includes: forming a second mask layer (not shown) on the first dielectric layer 204; forming a second patterned layer (not shown) on the second mask layer, wherein the second patterned layer exposes a portion of the top surface of the second mask layer; etching the second mask layer and the first dielectric layer 204 using the second patterned layer as a mask to form the second opening 205 in the first dielectric layer; after forming the second opening 205, removing the second patterned layer and the second mask layer.

[0064] The material of the second mask layer includes silicon nitride, silicon carbide nitride, silicon boron nitride, silicon carbon nitride oxide or silicon nitride oxide. In this embodiment, the material of the second mask layer is silicon nitride.

[0065] In this embodiment, the material of the second patterned layer includes photoresist, and the process of removing the second patterned layer includes an ashing process.

[0066] After forming the second opening, a first opening is formed in the first dielectric layer 204 and extends into the first conductive structure 201. The bottom surface of the first opening is lower than the top surface of the first conductive structure 201. For the specific formation process of the first opening, please refer to Figures 6 to 8 .

[0067] In this embodiment, the first opening is specifically located at the bottom of the second opening 205 , and the second opening 205 is communicated with the first opening.

[0068] Please refer to Figure 6 , forming a first mask layer 206 on the first dielectric layer 204 and in the second opening 205; forming a first patterned layer 207 on the first mask layer 206, wherein the first patterned layer 207 exposes a portion of the top surface of the first mask layer 206 in the second opening 205; etching the first mask layer 206 and the first dielectric layer 204 using the first patterned layer 207 as a mask until a portion of the top surface of the first conductive structure 201 is exposed, thereby forming an initial first opening 208 in the first dielectric layer 204.

[0069] The material of the first mask layer 206 includes silicon nitride, silicon carbide nitride, silicon boron nitride, silicon carbon nitride oxide or silicon nitride oxide. In this embodiment, the material of the first mask layer 206 is silicon nitride.

[0070] In this embodiment, the material of the first patterned layer 207 is photoresist.

[0071] The process of etching the first mask layer 206 and the first dielectric layer 204 includes a dry etching process or a wet etching process. In the present embodiment, the process of etching the first mask layer 206 and the first dielectric layer 204 adopts a wet etching process.

[0072] Please refer to Figure 7 , etching the top surface of the first conductive structure 201 exposed by the initial first opening 208 to form the first opening 209 in the first dielectric layer 204 and in the first conductive structure 201 .

[0073] In this embodiment, a wet etching process is used to etch the top surface of the first conductive structure 201 exposed by the initial first opening 208 . The etching solution used in the wet etching process includes an acidic solution.

[0074] In this embodiment, the ratio of the distance from the bottom of the first opening 209 to the top surface of the first conductive structure 201 to the distance from the bottom of the first conductive structure 201 to the top surface of the first conductive structure 201 is 1:4-1.5:1.

[0075] The ratio within this range can effectively increase the contact area between the subsequently formed plug structure and the first conductive structure 201 and reduce the contact resistance between the first conductive structure 201 and the plug structure, thereby improving the electrical performance of the finally formed semiconductor structure.

[0076] Please refer to Figure 8 After forming the first opening 209 , the first patterning layer 207 and the first mask layer 206 are removed.

[0077] In this embodiment, the process of removing the first patterned layer 207 includes an ashing process.

[0078] Please refer to Fig. 9 , a plug structure 210 is formed in the first opening 209 .

[0079] The first opening 209 is formed in the first dielectric layer 204 and extends into the first conductive structure 201. The bottom surface of the first opening 209 is lower than the top surface of the first conductive structure 201, and a plug structure 210 is formed in the first opening 209. The first opening 209 extending into the first conductive structure 201 increases the contact area between the first conductive structure 201 and the plug structure 210, thereby reducing the contact resistance between the first conductive structure 201 and the plug structure 210, thereby improving the electrical performance of the finally formed semiconductor structure.

[0080] In this embodiment, while forming the plug structure 210 , the process further includes: forming a second conductive structure 211 in the second opening 205 .

[0081] By forming the plug structure 210 and the second conductive structure 211 simultaneously, the number of process steps can be reduced and the production efficiency can be effectively improved.

[0082] The plug structure 210 includes: a second barrier layer 212 located on the side walls and bottom surface of the first opening 209, and a conductive plug 213 located on the surface of the second barrier layer 212 and filling the first opening 209; the second conductive structure 211 includes: a third barrier layer 214 located on the side walls and bottom surface of the second opening 205, and a second conductive layer 215 located on the surface of the third barrier layer 214 and filling the second opening 205.

[0083] In this embodiment, the method for forming the plug structure 210 and the second conductive structure 211 includes: forming an initial barrier layer (not shown) on the bottom and side wall surfaces of the first opening 209 and the second opening 205, and the top surface of the first dielectric layer 204; forming an initial conductive structure (not shown) on the initial barrier layer; and planarizing the initial barrier layer and the initial conductive structure until the top surface of the first dielectric layer 204 is exposed, thereby forming the plug structure 210 and the second conductive structure 211.

[0084] The planarization process includes a chemical mechanical polishing process, a wet etching process or a dry etching process. In the present embodiment, the planarization process adopts a chemical mechanical polishing process.

[0085] The second barrier layer 212 and the third barrier layer 214 are annealed to form metal silicide with the semiconductor material. The formed metal silicide reduces the contact resistance of the second conductive layer 215 and the conductive plug 213, thereby improving the electrical performance of the final semiconductor structure. In this embodiment, the thickness of the second barrier layer 212 is 5 angstroms to 40 angstroms; the thickness of the third barrier layer 214 is 5 angstroms to 40 angstroms.

[0086] In this embodiment, the second barrier layer and the third barrier layer are single-layer structures; in other embodiments, the second barrier layer and the third barrier layer can also be multi-layer structures.

[0087] In this embodiment, the material of the second barrier layer 212 and the third barrier layer 214 includes: one or more combinations of titanium, titanium nitride, tantalum, tantalum nitride, nickel, magnesium, cobalt, manganese oxide, aluminum oxide and aluminum nitride. In this embodiment, the material of the second barrier layer 212 and the third barrier layer 214 is tantalum.

[0088] In this embodiment, the material of the conductive plug 213 and the second conductive layer 215 includes: one or more combinations of copper, cobalt, ruthenium, manganese and aluminum. In this embodiment, the material of the second conductive layer 215 and the conductive plug 213 is copper.

[0089] Accordingly, an embodiment of the present invention further provides a semiconductor structure, please continue to refer to Fig. 9 , including: a substrate 200, wherein the substrate 200 has a first conductive structure 201, wherein the first conductive structure 201 is exposed on the surface of the substrate 200; a first dielectric layer 204 located on the substrate 200; a first opening (not shown) located in the first dielectric layer 204 and extending into the first conductive structure 201, wherein the bottom surface of the first opening is lower than the top surface of the first conductive structure 201; and a plug structure 210 located in the first opening.

[0090] The following is a detailed description with reference to the accompanying drawings.

[0091] In this embodiment, the first conductive structure 201 includes: a first barrier layer 202 and a first conductive layer 203 located on the first barrier layer 202 .

[0092] The first barrier layer 202 is annealed to form metal silicide with the semiconductor material. The formed metal silicide reduces the contact resistance of the first conductive layer 203, thereby improving the electrical properties of the final semiconductor structure. In this embodiment, the thickness of the first barrier layer 202 is 5 angstroms to 40 angstroms.

[0093] In this embodiment, the first barrier layer 202 is a single-layer structure; in other embodiments, the first barrier layer may also be a multi-layer structure.

[0094] The material of the first barrier layer 202 includes: one or more combinations of titanium, titanium nitride, tantalum, tantalum nitride, nickel, magnesium, cobalt, manganese oxide, aluminum oxide and aluminum nitride. In this embodiment, the material of the first barrier layer 202 is tantalum.

[0095] The material of the first conductive layer 203 includes metal, and the metal includes one or more combinations of copper, cobalt, ruthenium, manganese and aluminum. In this embodiment, the material of the first conductive layer 203 is copper.

[0096] In this embodiment, the ratio of the distance from the bottom of the first opening 209 to the top surface of the first conductive structure 201 to the distance from the bottom of the first conductive structure 201 to the top surface of the first conductive structure 201 is 1:4-1.5:1.

[0097] The ratio within this range can effectively increase the contact area between the subsequently formed plug structure and the first conductive structure 201 and reduce the contact resistance between the first conductive structure 201 and the plug structure, thereby improving the electrical performance of the finally formed semiconductor structure.

[0098] In this embodiment, the plug structure 210 includes: a second barrier layer 212 located on the sidewall and bottom surface of the first opening, and a conductive plug 213 located on the surface of the second barrier layer 212 and filling the first opening.

[0099] In this embodiment, it further includes: a second opening (not labeled) located in the first dielectric layer 204 , the first opening is located at the bottom of the second opening, and the second opening is connected to the first opening.

[0100] In this embodiment, the present invention further includes: a second conductive structure 211 located in the second opening.

[0101] In this embodiment, the plug structure 210 and the second conductive structure 211 are formed simultaneously.

[0102] By forming the second conductive structure and the plug structure at the same time, the number of process steps can be effectively reduced and the production efficiency can be improved.

[0103] In this embodiment, the second conductive structure 211 includes: a third barrier layer 214 located on the sidewalls and bottom surface of the second opening, and a second conductive layer 215 located on the surface of the third barrier layer 214 and filling the second opening.

[0104] The second barrier layer 212 and the third barrier layer 214 are annealed to form metal silicide with the semiconductor material. The formed metal silicide reduces the contact resistance of the second conductive layer 215 and the conductive plug 213, thereby improving the electrical performance of the final semiconductor structure. In this embodiment, the thickness of the second barrier layer 212 is 5 angstroms to 40 angstroms; the thickness of the third barrier layer 214 is 5 angstroms to 40 angstroms.

[0105] In this embodiment, the second barrier layer 212 and the third barrier layer 214 are single-layer structures; in other embodiments, the second barrier layer and the third barrier layer can also be multi-layer structures.

[0106] In this embodiment, the material of the second barrier layer 212 and the third barrier layer 214 includes: one or more combinations of titanium, titanium nitride, tantalum, tantalum nitride, nickel, magnesium, cobalt, manganese oxide, aluminum oxide and aluminum nitride. In this embodiment, the material of the second barrier layer 212 and the third barrier layer 214 is tantalum.

[0107] In this embodiment, the material of the conductive plug 213 and the second conductive layer 215 includes: one or more combinations of copper, cobalt, ruthenium, manganese and aluminum. In this embodiment, the material of the second conductive layer 215 and the conductive plug 213 is copper.

[0108] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, wherein the substrate has a first conductive structure therein, and the first conductive structure is exposed on a surface of the substrate; a first dielectric layer located on the substrate; a first opening located in the first dielectric layer and extending into the first conductive structure, wherein a bottom surface of the first opening is lower than a top surface of the first conductive structure, and the first opening penetrates the first conductive structure; A plug structure is located in the first opening.

2. The semiconductor structure according to claim 1, wherein: The first conductive structure includes a first barrier layer and a first conductive layer located on the first barrier layer.

3. The semiconductor structure according to claim 2, wherein: The thickness of the first barrier layer is 5 angstroms to 40 angstroms.

4. The semiconductor structure according to claim 1, wherein: The plug structure includes: a second barrier layer located on the sidewall and bottom surface of the first opening, and a conductive plug located on the surface of the second barrier layer and filling the first opening.

5. The semiconductor structure according to claim 4, characterized in that The thickness of the second barrier layer is 5 angstroms to 40 angstroms.

6. The semiconductor structure according to claim 1, wherein: Also includes: A second opening is located in the first dielectric layer, the first opening is located at the bottom of the second opening, and the second opening is connected to the first opening.

7. The semiconductor structure according to claim 6, wherein: Also includes: A second conductive structure is located in the second opening.

8. The semiconductor structure according to claim 7, wherein: The second conductive structure includes: a third barrier layer located on the sidewall and bottom surface of the second opening, and a second conductive layer located on the surface of the third barrier layer and filling the second opening.

9. The semiconductor structure according to claim 8, characterized in that The thickness of the third barrier layer is 5 angstroms to 40 angstroms.

10. The semiconductor structure according to claim 2, wherein: The first barrier layer is a single-layer or multi-layer structure.

11. The semiconductor structure according to claim 4, wherein: The second barrier layer is a single-layer or multi-layer structure.

12. The semiconductor structure according to claim 8, wherein: The third barrier layer is a single layer or multi-layer structure.

13. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, wherein the substrate has a first conductive structure therein, and the first conductive structure is exposed on a surface of the substrate; forming a first dielectric layer on the substrate; forming a first opening in the first dielectric layer and extending into the first conductive structure, wherein a bottom surface of the first opening is lower than a top surface of the first conductive structure, and the first opening penetrates the first conductive structure; A plug structure is formed in the first opening.

14. The method for forming a semiconductor structure according to claim 13, wherein: Before forming the first opening, the method further includes: forming a second opening in the first dielectric layer; the first opening is located at the bottom of the second opening, and the second opening is connected to the first opening.

15. The method for forming a semiconductor structure according to claim 14, wherein: The method for forming the first opening includes: forming a first mask layer on the first dielectric layer and in the second opening; forming a first patterned layer on the first mask layer, the first patterned layer exposing a portion of the top surface of the first mask layer in the second opening; etching the first mask layer and the first dielectric layer using the first patterned layer as a mask until a portion of the top surface of the first conductive structure is exposed, thereby forming an initial first opening in the first dielectric layer; etching the top surface of the first conductive structure exposed by the initial first opening, thereby forming the first opening in the first dielectric layer and in the first conductive structure; after forming the first opening, removing the first patterned layer and the first mask layer.

16. The method for forming a semiconductor structure according to claim 15, wherein: A wet etching process is used to etch the top surface of the first conductive structure exposed by the initial first opening.

17. The method for forming a semiconductor structure according to claim 14, wherein: While forming the plug structure, the method further includes: forming a second conductive structure in the second opening.

18. The method for forming a semiconductor structure according to claim 17, wherein: The plug structure includes: a second barrier layer located on the side wall and bottom surface of the first opening, and a conductive plug located on the surface of the second barrier layer and filling the first opening; the second conductive structure includes: a third barrier layer located on the side wall and bottom surface of the second opening, and a second conductive layer located on the surface of the third barrier layer and filling the second opening.

19. The method for forming a semiconductor structure according to claim 18, wherein: The method for forming the plug structure and the second conductive structure includes: forming an initial barrier layer on the bottom and side wall surfaces of the first opening and the second opening, and the top surface of the first dielectric layer; forming an initial conductive structure on the initial barrier layer; and planarizing the initial barrier layer and the initial conductive structure until the top surface of the first dielectric layer is exposed, thereby forming the plug structure and the second conductive structure.

20. The method for forming a semiconductor structure according to claim 13, wherein: The first conductive structure includes a first barrier layer and a first conductive layer located on the first barrier layer.

21. The method for forming a semiconductor structure according to claim 20, wherein: The thickness of the first barrier layer is 5 angstroms to 40 angstroms.

22. The method for forming a semiconductor structure according to claim 18, wherein: The thickness of the second barrier layer is 5 angstroms to 40 angstroms.

23. The method for forming a semiconductor structure according to claim 18, wherein: The thickness of the third barrier layer is 5 angstroms to 40 angstroms.

24. The method for forming a semiconductor structure according to claim 20, wherein: The first barrier layer is a single-layer or multi-layer structure.

25. The method for forming a semiconductor structure according to claim 18, wherein: The second barrier layer is a single-layer or multi-layer structure.

26. The method for forming a semiconductor structure according to claim 18, wherein: The third barrier layer is a single layer or multi-layer structure.

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