Flexible graphene field effect transistor and preparation method thereof

Abstract

The present invention relates to the field of transistor processing technology, and specifically to a graphene field effect transistor integrated device and a preparation method, comprising the following steps: providing a substrate, the substrate being fixed on a substrate; forming a gate on the substrate by thermal evaporation; forming a Ti nucleation layer and a HfO2 gate dielectric layer on the gate in sequence by an ALD atomic layer deposition coating method; transferring graphene on the HfO2 gate dielectric layer by a stamp method to obtain a graphene layer; preparing a source and a drain on the graphene layer by mask plate photolithography; forming a coating layer on the graphene layer by an ALD atomic layer deposition coating method, with the source and the drain exposing the coating layer; peeling the substrate from the substrate to obtain a graphene field effect transistor; and connecting at least two graphene field effect transistors in series and / or in parallel by mask plate photolithography through a metal layer. The present invention overcomes the problem of non-uniform performance of existing graphene field effect transistor devices.

Description

Technical Field

[0001] The present invention relates to the technical field of transistor manufacturing, and in particular to a flexible graphene field effect transistor and a preparation method thereof. Background Art

[0002] As the earliest discovered two-dimensional semiconductor nanomaterial, graphene has attracted a lot of research due to its special electronic properties. With the progress of high-quality synthesis of graphene nanosheets, graphene field-effect transistor electronic devices based on flexible materials have been widely studied.

[0003] Here, the pursuit of high-performance transconductance amplification of flexible graphene field-effect transistor devices has become a research hotspot in the field of super-silicon nanoelectronics. Although the missing bandgap of graphene limits its switching current ratio performance and application in digital integrated circuit systems, graphene field-effect transistor devices still have great potential in analog signal processing. The current saturation phenomenon in graphene field-effect transistor devices is similar to the current saturation phenomenon in traditional silicon MOSFETs to some extent. It would be a logical path to realize the integration of multiple flexible graphene field-effect transistor devices according to the roadmap of silicon-based analog ICs. However, so far, related research is still rare and mostly limited to integrating a single flexible graphene field-effect transistor device with several auxiliary components, such as resistors, inductors or antennas.

[0004] In the actual research process, after a large amount of data research, it was found that the performance non-uniformity of graphene field effect transistor devices caused the above-mentioned problems. Since the atomic form of graphene exposes all carbon atoms, the air, moisture and other impurities in the environment will contaminate the carbon atoms in the graphene. These pollutants can easily cause unpredictable degradation of the graphene surface or even the entire graphene layer, which in turn leads to unevenness in the graphene layer, which greatly affects the conductive effect of the graphene layer. Therefore, even for batch-produced flexible graphene field effect transistor devices, the non-uniformity between the integrated graphene field effect transistor devices also causes the integration results of multiple flexible graphene field effect transistor devices to be inconsistent with the original design. Summary of the invention

[0005] In order to overcome one of the deficiencies of the prior art, the object of the present invention is to provide a flexible graphene field effect transistor and a preparation method. The flexible graphene field effect transistor and the preparation method overcome the problem of uniformity of performance of graphene field effect transistor devices, and facilitate the batch preparation of graphene field effect transistors with high uniformity and long-term stability.

[0006] To solve the above problems, the technical solution adopted by the present invention is as follows:

[0007] A method for preparing a graphene field effect transistor integrated device, comprising:

[0008] A step of providing a substrate, providing a flexible substrate, wherein the substrate is fixed on a substrate;

[0009] A gate preparation step, forming a gate on the substrate by thermal evaporation;

[0010] The gate dielectric layer preparation step comprises forming a Ti nucleation layer and a HfO2 gate dielectric layer on the gate in sequence by using an ALD atomic layer deposition coating method;

[0011] A graphene layer preparation step, wherein graphene is transferred onto the HfO2 gate dielectric layer by a stamp method to obtain a graphene layer;

[0012] The source and drain preparation step is to prepare the source and drain on the graphene layer by mask lithography;

[0013] A coating layer preparation step, forming a coating layer on the graphene layer by using an ALD atomic layer deposition coating method, wherein the source electrode and the drain electrode are exposed from the coating layer;

[0014] The step of preparing a graphene integrated device comprises peeling off the substrate obtained in the step of preparing the coating layer from the substrate to obtain a graphene field effect transistor; using a mask plate photolithography method to respectively connect at least two of the graphene field effect transistors in series and / or in parallel through a metal layer, wherein the gate on the same graphene field effect transistor is connected to the source, and the gate on one graphene field effect transistor is connected to the drain on another graphene field effect transistor.

[0015] In some embodiments, the graphene layer preparation step comprises the following steps:

[0016] Graphene is grown on copper foil by CVD method, and PMMA solution is spin-coated on the graphene layer to obtain a combination of PMMA layer / graphene layer / copper foil in the order of PMMA layer / graphene layer;

[0017] The assembly 1 is adhered and pressed on a glass slide by PDMS glue on one side of the PMMA layer, and the copper foil is removed to obtain an assembly 2 of glass slide / PDMS layer / PMMA layer / graphene layer in the order;

[0018] Rolling the second assembly located on one side of the graphene onto the HfO2 gate dielectric layer, so that the second assembly covers the drain, the gate and the source; the rolling temperature is 160-180° C., and the rolling time is 0.5-4 min; removing the glass slide and the PDMS layer on the second assembly;

[0019] Use acetone to remove the PMMA layer, then clean it with isopropyl alcohol, and then rinse it with deionized water;

[0020] The graphene layer is coated with glue and photolithography is performed to obtain graphene patterned channels, which are then developed and then plasma is used to knock off excess graphene to obtain a graphene device.

[0021] In some embodiments, the second preparation step of the assembly more specifically includes the following steps:

[0022] Coating PDMS glue on one side of the assembly located on the PMMA layer;

[0023] Adhere the glass slide to the PDMS glue and press it firmly;

[0024] The above-obtained assembly was placed in APS100 etching solution to etch away the copper foil, and then washed with deionized water and blown dry to obtain an assembly II having the sequence of glass slide / PDMS layer / PMMA layer / graphene layer.

[0025] In some embodiments, the gate preparation step includes the following steps:

[0026] Spin-coat LOR5A glue on the substrate, then spin-coat AZ5214 glue, then perform photolithography exposure and development to obtain a desired first pattern;

[0027] A Au / Cr metal layer is formed on the substrate by thermal evaporation, and the photoresist is removed to form the gate.

[0028] In some embodiments, the gate dielectric layer preparation step comprises the following steps:

[0029] Forming a Ti nucleation layer on the product obtained in the gate preparation step by using an ALD atomic layer deposition coating method;

[0030] A Hf layer is formed on the Ti nucleation layer by using an ALD atomic layer deposition coating method, and then the Hf layer is oxidized to obtain a HfO2 gate dielectric layer.

[0031] In some embodiments, the source and drain preparation steps include the following steps:

[0032] Coating a photoresist on the graphene layer, then performing photolithography exposure and development to obtain a desired second pattern;

[0033] Performing evaporation by a thermal evaporation method to form an Au / Cr metal layer on the graphene layer;

[0034] The portion with the photoresist is removed by using NMP solution at a temperature of 80-90° C. for 8-12 minutes to obtain the source electrode and the drain electrode.

[0035] In some embodiments, the coating layer is prepared in the following steps:

[0036] Coating a photoresist on the graphene layer, exposing and developing the photoresist layer on the graphene layer, and etching the photoresist layer to obtain a third pattern;

[0037] A HfO2 layer is formed on the graphene layer by using an ALD atomic layer deposition coating method, and the photoresist on the graphene layer is removed by using an NMP solution to obtain a coating layer coated on the graphene layer.

[0038] In some embodiments, the graphene integrated device step comprises the following steps:

[0039] The base sheet obtained in the coating layer preparation step is peeled off from the substrate to obtain a graphene field effect transistor;

[0040] Placing at least two graphene field effect transistors independently on a substrate structure, coating a photoresist on the substrate structure, exposing and developing the photoresist layer on the substrate structure, and etching the photoresist layer to obtain a fourth pattern;

[0041] An Au layer is formed on the photoresist layer by thermal evaporation, and the Au layer respectively connects at least two of the graphene field effect transistors in series and / or in parallel, and the connection mode is that the gate on the same graphene field effect transistor is connected to the source electrode, and the gate on one graphene field effect transistor is connected to the drain electrode on another graphene field effect transistor;

[0042] The photoresist on the substrate structure is removed by using an NMP solution, and the substrate structure is separated from the graphene field effect transistor to obtain a graphene integrated device.

[0043] In some embodiments, the substrate is a PI film, and the thickness of the film is 10-25 μm.

[0044] A graphene field effect transistor integrated device is prepared by adopting the preparation method of the graphene field effect transistor integrated device.

[0045] Compared with the prior art, the present invention has the following beneficial effects:

[0046] The preparation method of the graphene field effect transistor integrated device of the present invention uses PI film as a substrate material, which can greatly improve the flexibility, so that the transistor formed later has greater flexibility. The PI film can greatly improve the working ability of the entire device under high temperature conditions and ensure the stability of the work. Using Ti as a nucleation layer and then forming an HfO2 layer on Ti, the dielectric layer can be used to obtain a larger dielectric constant, so that the gate and the source and drain are insulated and isolated. Using the stamp method to transfer the graphene layer, the graphene layer can be accurately prepared on a large scale to the greatest extent, improving the efficiency and quality of batch production of graphene layers; the HfO2 layer is completely encapsulated on the graphene layer, which can effectively isolate the surrounding pollutants and well maintain the excellent electrical properties and long-term stability of graphene. Finally, the above-mentioned metal layer is used to connect different graphene field effect transistors, so that the integration of multiple graphene field effect transistors can be realized, and the graphene field effect transistor integrated device has high uniformity and long-term stability.

[0047] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 is a schematic diagram of a flow chart of an embodiment of the present invention;

[0049] Figure 2 is a process flow chart of an embodiment of the present invention;

[0050] Figure 3 is a flow chart of the principle of transferring graphene to a substrate in an embodiment of the present invention;

[0051] Figure 4 It is a schematic diagram of the connection structure of the graphene field effect transistor integrated device in an embodiment of the present invention. DETAILED DESCRIPTION

[0052] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0053] See also Figures 1 to 4 , a method for preparing a graphene field effect transistor integrated device, comprising

[0054] S100: providing a substrate, providing a flexible substrate, wherein the substrate is fixed on a substrate;

[0055] S200: a gate preparation step, forming a gate on the substrate by thermal evaporation;

[0056] S300: a gate dielectric layer preparation step, using an ALD atomic layer deposition coating method to sequentially form a Ti nucleation layer and a HfO2 gate dielectric layer on the gate;

[0057] S400: a graphene layer preparation step, transferring graphene on the HfO2 gate dielectric layer by a stamp method to obtain a graphene layer;

[0058] S500: a source electrode and a drain electrode preparation step, wherein the source electrode and the drain electrode are prepared on the graphene layer by using a mask plate photolithography method;

[0059] S600: a coating layer preparation step, forming a coating layer on the graphene layer by using an ALD atomic layer deposition coating method, wherein the source electrode and the drain electrode are exposed from the coating layer;

[0060] S700: a step of preparing a graphene integrated device, wherein the base sheet obtained in the step of preparing the coating layer is peeled off from the substrate to obtain a graphene field effect transistor; at least two of the graphene field effect transistors are respectively connected in series and / or in parallel through a metal layer by means of mask lithography, wherein the gate electrode on the same graphene field effect transistor is connected to the source electrode, and the gate electrode on one graphene field effect transistor is connected to the drain electrode on another graphene field effect transistor.

[0061] In the above step S100, the substrate serves as the base of the entire structure. In order to make it flexible, in one embodiment of the present application, the substrate is a PI film, and the thickness of the film is 10-25 μm. Such a design can effectively reduce the thickness of the transistor matrix, and then multiple devices can be integrated in the Z direction, and the high density of transistors is achieved under the condition of unit thickness. In addition, the PI film can withstand a high temperature of 400°C, and such performance gives the entire transistor the possibility of stable operation at high temperatures. In addition, the PI film has a certain flexibility, and such performance makes the entire transistor also flexible, which is convenient for different usage scenarios. In this application, silicon is used as a substrate, which is convenient for the molding of the PI film and provides corresponding performance, such as rigidity.

[0062] The preparation method of the graphene field effect transistor integrated device uses PI film as the substrate material, which can greatly improve the flexibility, so that the transistor formed later has greater flexibility. The PI film can greatly improve the working ability of the entire device under high temperature conditions and ensure the stability of the work. Using Ti as the nucleation layer and then forming the HfO2 layer on Ti, the dielectric layer can be used to obtain a larger dielectric constant, so that the gate and the source and drain are insulated and isolated. Using the stamp method to transfer the graphene layer, the graphene layer can be accurately prepared on a large scale to the greatest extent, improving the efficiency and quality of batch production of graphene layers; the HfO2 layer is completely encapsulated on the graphene layer, which can effectively isolate the surrounding pollutants and well maintain the excellent electrical properties and long-term stability of graphene. Finally, using the above-mentioned situation, the metal layer connects different graphene field effect transistors, and the integration of multiple graphene field effect transistors can be realized, so that the graphene field effect transistor integrated device has high uniformity and long-term stability.

[0063] It should be noted that, in the above step S200, the gate preparation step includes the following steps:

[0064] S210: Spin-coat LOR5A glue on the substrate, then spin-coat AZ5214 glue, and then perform photolithography exposure and development to obtain a desired first pattern;

[0065] S220: forming an Au / Cr metal layer on the substrate by thermal evaporation, removing the photoresist, and forming the gate.

[0066] Wherein, the Au / Cr metal layer is divided into a gold layer and a chromium layer, and the thickness ratio of the gold layer to the chromium layer is 1:30-50; the gold layer has relatively better conductivity. It should be supplemented that the above-mentioned gate is actually the first electrode. The first pattern is the pattern of the gate. In this application, there are two gates designed to facilitate connection with other devices later. LOR5A glue and AZ5214 glue are both conventional photoresists. At the same time, the coating, exposure and development operations of the photoresist are all conventional technical means, which will not be described in detail in this application.

[0067] It should be noted that, in the above step S220, the photoresist is removed using NMP solution, which is also a conventional technical means, and the present application will not describe the removal principle in detail.

[0068] For further information, see Figure 3 In the above step S300, the gate dielectric layer preparation step includes the following steps:

[0069] S310: forming a Ti nucleation layer on the product obtained in the gate preparation step by using an ALD atomic layer deposition coating method;

[0070] S320: forming a Hf layer on the Ti nucleation layer by using an ALD atomic layer deposition coating method, and then oxidizing the Hf layer to obtain a HfO2 gate dielectric layer.

[0071] Among them, in the above step S310, the Ti nucleation layer completely covers the Au / Cr metal layer formed in step S220, and the setting of the HfO2 gate dielectric layer can maximize the gate dielectric layer to obtain a larger dielectric constant, so that the first electrode and the source and drain formed in step S500 are insulated and isolated. In the above embodiment, in order to obtain the maximum effect, the thickness of the HfO2 gate dielectric layer is 10-20nm. In addition, the Ti nucleation layer is actually obtained by the method of metal titanium ALD atomic layer deposition coating, and its thickness is 0.6-5nm.

[0072] See also Figure 3 More specifically, in step S400 of the present application, the graphene layer preparation step includes the following steps:

[0073] S410: growing graphene on copper foil by CVD method to obtain copper foil / graphene layer, and spin coating PMMA solution on the graphene layer to obtain a combination of PMMA layer / graphene layer / copper foil in the order of one;

[0074] S420: Adhere and press the assembly 1 on a glass slide by PDMS glue on one side of the PMMA layer, and remove the copper foil to obtain an assembly 2 in the order of glass slide / PDMS layer / PMMA layer / graphene layer;

[0075] S430: rolling the second assembly located on the graphene side onto the HfO2 gate dielectric layer, so that the second assembly covers the drain, the gate and the source; the rolling temperature is 160-180° C., and the rolling time is 0.5-4 min; removing the glass slide and the PDMS layer on the second assembly;

[0076] S440: Remove the PMMA layer with acetone, then wash with isopropyl alcohol, and then rinse with deionized water;

[0077] S450: applying glue on the graphene layer and performing photolithography to obtain graphene patterned channels, developing the layers, and then using plasma to knock off excess graphene to obtain a graphene device.

[0078] It should be noted that the PMMA layer is coated on the graphene layer, and the coating method and coating thickness thereof are not limited, but in actual operation, such a PMMA layer is relatively thicker than the PDMS layer, and it can achieve the maximum buffering of the rolling force in the above-mentioned rolling operation, and avoid the rolling force from damaging the graphene layer. In addition, after the copper foil / graphene layer is generated, it is also necessary to cut as required, so that the graphene layer is rolled on the substrate in the later stage, and the substrate here is the substrate obtained by the above-mentioned step S300. Wherein, PMMA is a conventional material, and this application is not described in detail here. In addition, the thickness of the PMMA layer is not required in this application, and its main purpose is to adhere to the PDMS glue and fix the slide glass in the later stage. In addition, PMMA can also play a role in fixing the graphene layer in actual operation, so that step S430 is convenient for rolling and avoiding the graphene layer from being damaged.

[0079] In some embodiments, in the above step S420, the second assembly preparation step more specifically includes the following steps:

[0080] S421: coating PDMS glue on one side of the assembly located on the PMMA layer;

[0081] S422: Adhere the glass slide to the PDMS glue and press it;

[0082] S423: The above-obtained assembly is placed in APS100 etching solution to etch away the copper foil, and then washed with deionized water and blown dry to obtain an assembly 2 having the sequence of glass slide / PDMS layer / PMMA layer / graphene layer.

[0083] Among them, the design of the above-mentioned combination 2 uses a glass slide as a substrate, which is convenient for the rolling process in the later step S430. The glass slide can, to a certain extent, ensure that the graphene can provide uniform rolling pressure to the greatest extent during the rolling process, thereby ensuring the adhesion between the graphene layer and the HfO2 gate dielectric layer.

[0084] More specifically, in step S430, the heating temperature of the substrate is preferably 170°C, and the rolling time is 2 minutes. Among them, at about 170°C, the adhesion between the PDMS layer and the PMMA layer is reduced, and at this time the glass slide is easier to separate from the PMMA layer, reducing the difficulty of separating the glass slide. In addition, the main purpose of the glass slide in this application is to facilitate the external roller press to roll the PMMA layer / graphene layer onto the above-mentioned substrate; the glass slide provides a stable rigid structure, thereby ensuring the quality of rolling. As an important step in transferring the graphene layer by the stamp method, glass slide rolling is directly related to the subsequent rolling quality, the adhesion effect of the graphene layer and the PI film, and the coverage effect of the graphene layer on the first electrode.

[0085] In addition, in the present application, the graphene layer is coated with glue and photolithography is performed to obtain a graphene layer patterned channel, which is actually the pattern of the first electrode. The photoresist layer on the first electrode, that is, the channel graphene layer, is not washed off and intentionally retained by the photolithography, and is retained to protect the graphene layer. It should be supplemented that, in order to remove the PMMA layer using acetone, the entire carrier needs to be placed in an acetone solution for two hours to remove it. The PMMA remaining on the graphene layer can be effectively cleaned by washing with isopropanol. The main purpose of rinsing with deionized water is to eliminate isopropanol and ensure the purity of the graphene layer and the substrate. In addition, after rinsing with deionized water, air drying is required.

[0086] In some embodiments, in order to better illustrate the formation of the source and the drain, which is actually the formation of the second electrode, step S500 specifically includes the following steps:

[0087] S510: coating a photoresist on the graphene layer, then performing photolithography exposure and development to obtain a desired second pattern;

[0088] S520: performing evaporation by a thermal evaporation method to form an Au / Cr metal layer on the graphene layer;

[0089] S530: using NMP solution to remove the portion with the photoresist, the temperature during removal is 80-90° C., and the removal time is 8-12 minutes, to obtain the source electrode and the drain electrode.

[0090] Among them, the formation method of the source and drain is the same as the formation method of the gate, and this application will not be described in detail here. It should be supplemented that the material used for the source and drain is also the Au / Cr metal layer divided into a gold layer and a chromium layer, and the thickness ratio of the gold layer and the chromium layer is 1:10-12, which is different from the thickness of the gate, and it is selected according to actual needs. It should be noted that at least one source and drain are respectively provided, so that it is convenient to integrate and connect with different graphene field effect transistors in the later stage, which is set according to actual usage requirements.

[0091] In some embodiments, in the above embodiments, since the second electrode and the first electrode are located at different positions, in order to better ensure the sealing of the graphene layer between the second electrode and the first electrode, in the above step S600, the coating layer preparation step is:

[0092] S610: coating a photoresist on the graphene layer, exposing and developing the photoresist layer on the graphene layer, and etching the photoresist layer to obtain a third pattern;

[0093] S620: forming a HfO2 layer on the graphene layer by using an ALD atomic layer deposition coating method, and removing the photoresist on the graphene layer by using an NMP solution to obtain a coating layer coated on the graphene layer.

[0094] Among them, the HfO2 layer is selected as the coating layer to a certain extent, thanks to its larger dielectric constant, which reduces the external pollution sources from entering the graphene layer or other signal sources from causing electromagnetic interference to the graphene layer.

[0095] In some embodiments, in step S700 of the present application, the graphene integrated device step includes the following steps:

[0096] S710: peeling the base sheet obtained in step S600 from the substrate to obtain a graphene field effect transistor;

[0097] S720: placing at least two graphene field effect transistors independently on a substrate structure, coating a photoresist on the substrate structure, exposing and developing the photoresist layer on the substrate structure, and etching the photoresist layer to obtain a fourth pattern;

[0098] S730: forming an Au layer on the photoresist layer by thermal evaporation, wherein the Au layer respectively connects at least two of the graphene field effect transistors in series and / or in parallel, and the connection mode is that the gate electrode on the same graphene field effect transistor is connected to the source electrode, and the gate electrode on one graphene field effect transistor is connected to the drain electrode on another graphene field effect transistor;

[0099] S740: removing the photoresist on the substrate structure with an NMP solution, and separating the substrate structure from the graphene field effect transistor to obtain a graphene integrated device.

[0100] The substrate structure can also be made of flexible materials, such as polyimide film. It should be noted that the fourth pattern is actually the layout pattern of the Au layer, which has no fixed method. It is mainly to facilitate the connection of the two adjacent graphene field effect transistors mentioned above. At the same time, the Au layer has sufficient flexibility to facilitate folding at a certain angle in the later stage; at the same time, based on the thin thickness of the entire device substrate, a high transistor density per unit volume can be achieved.

[0101] It should be noted that since each graphene integrated device is only integrated by multiple graphene field effect transistors, a new technical field is opened, especially a new packaging circuit. At the same time, graphene field effect transistors have consistency, uniformity and long-term stability. Therefore, after multiple integrations, graphene field effect transistors can still maintain uniformity, which makes it easier for the analog signal inside the entire graphene integrated device to not easily have nonlinear distortion, thus achieving signal fidelity.

[0102] In addition, the present invention also provides a graphene field effect transistor integrated device, which is prepared by using the preparation method of the graphene field effect transistor integrated device. Figure 4 It should be noted that the graphene field effect transistor integrated device of the present application is preferably used as an analog amplifier integrated circuit. For the sake of convenience, the present invention takes two graphene field effect transistors as an example for integration of the technical solution, wherein Figure 4 The reference numerals 1, 2, 5 and 6 in the figure represent the second electrode, wherein 1 and 5 are the source electrode, 2 and 6 are the drain electrode, and the material is a gold-chromium layer; 3, 4, 7, 8, 9 and 13 represent the first electrode (gate), 17 and 18 are Au layers, 10 and 14 are hafnium dioxide gate dielectric layers / Ti nucleation layers; 12 and 16 represent cladding layers, and 11 and 15 are graphene layers. Through the above design, the good linearity of the wire signal can be used for the fidelity amplification, which is very suitable for the high-fidelity pre-amplification of the small baseband signal of the analog information source, overcomes the inherent nonlinear distortion problem in the existing silicon MOSFET amplifier, and may provide a promising solution for the accurate pre-amplification of weak analog signals.

[0103] The above-mentioned embodiments are only preferred embodiments of the present invention and cannot be used to limit the scope of protection of the present invention. Any non-substantial changes and substitutions made by technicians in this field on the basis of the present invention shall fall within the scope of protection required by the present invention.

Claims

1. A method for preparing a graphene field effect transistor integrated device, characterized in that: include A step of providing a substrate, providing a flexible substrate, wherein the substrate is fixed on a substrate; A gate preparation step, forming a gate on the substrate by thermal evaporation; The gate dielectric layer preparation step comprises forming a Ti nucleation layer and a HfO2 gate dielectric layer on the gate in sequence by using an ALD atomic layer deposition coating method; A graphene layer preparation step, wherein graphene is transferred onto the HfO2 gate dielectric layer by a stamp method to obtain a graphene layer; The source and drain preparation step is to prepare the source and drain on the graphene layer by mask lithography; A coating layer preparation step, forming a coating layer on the graphene layer by using an ALD atomic layer deposition coating method, wherein the source electrode and the drain electrode are exposed from the coating layer; The preparation of graphene integrated device includes the following steps: The base sheet obtained in the coating layer preparation step is peeled off from the substrate to obtain a graphene field effect transistor; Placing at least two graphene field effect transistors independently on a substrate structure, coating a photoresist on the substrate structure, exposing and developing the photoresist layer on the substrate structure, and etching the photoresist layer to obtain a fourth pattern; An Au layer is formed on the photoresist layer by thermal evaporation, and the Au layer respectively connects at least two of the graphene field effect transistors in series and / or in parallel, and the connection mode is that the gate on the same graphene field effect transistor is connected to the source electrode, and the gate on one graphene field effect transistor is connected to the drain electrode on another graphene field effect transistor; The photoresist on the substrate structure is removed by using an NMP solution, and the substrate structure is separated from the graphene field effect transistor to obtain a graphene integrated device.

2. The method for preparing a graphene field effect transistor integrated device according to claim 1, characterized in that: The graphene layer preparation step comprises the following steps: Graphene is grown on copper foil by CVD method, and PMMA solution is spin-coated on the graphene layer to obtain a combination of PMMA layer / graphene layer / copper foil in the order of PMMA layer / graphene layer; The assembly 1 is adhered and pressed on a glass slide by PDMS glue on one side of the PMMA layer, and the copper foil is removed to obtain an assembly 2 of glass slide / PDMS layer / PMMA layer / graphene layer in the order; Rolling the second assembly located on one side of the graphene onto the HfO2 gate dielectric layer, so that the second assembly covers the drain, the gate and the source; the rolling temperature is 160-180° C., and the rolling time is 0.5-4 min; removing the glass slide and the PDMS layer on the second assembly; Use acetone to remove the PMMA layer, then clean it with isopropyl alcohol, and then rinse it with deionized water; The graphene layer is coated with glue and photolithography is performed to obtain graphene patterned channels, which are then developed and then plasma is used to knock off excess graphene to obtain a graphene device.

3. The method for preparing a graphene field effect transistor integrated device according to claim 2, characterized in that: The second preparation step of the assembly more specifically includes the following steps: Coating PDMS glue on one side of the assembly located on the PMMA layer; Adhere the glass slide to the PDMS glue and press it firmly; The above-obtained assembly was placed in APS100 etching solution to etch away the copper foil, and then washed with deionized water and blown dry to obtain an assembly II having the sequence of glass slide / PDMS layer / PMMA layer / graphene layer.

4. The method for preparing a graphene field effect transistor integrated device according to claim 1, characterized in that: The gate preparation step comprises the following steps: Spin-coat LOR5A glue on the substrate, then spin-coat AZ5214 glue, then perform photolithography exposure and development to obtain a desired first pattern; A Au / Cr metal layer is formed on the substrate by thermal evaporation, and the photoresist is removed to form the gate.

5. The method for preparing a graphene field effect transistor integrated device according to claim 1 or 4, characterized in that: The gate dielectric layer preparation step comprises the following steps: Forming a Ti nucleation layer on the product obtained in the gate preparation step by using an ALD atomic layer deposition coating method; A Hf layer is formed on the Ti nucleation layer by using an ALD atomic layer deposition coating method, and then the Hf layer is oxidized to obtain a HfO2 gate dielectric layer.

6. The method for preparing a graphene field effect transistor integrated device according to claim 1 or 2, characterized in that: The source and drain preparation steps include the following steps: Coating a photoresist on the graphene layer, then performing photolithography exposure and development to obtain a desired second pattern; Performing evaporation by a thermal evaporation method to form an Au / Cr metal layer on the graphene layer; The portion with the photoresist is removed by using NMP solution at a temperature of 80-90° C. for 8-12 minutes to obtain the source electrode and the drain electrode.

7. The method for preparing a graphene field effect transistor integrated device according to claim 1, characterized in that: The coating layer preparation steps: Coating a photoresist on the graphene layer, exposing and developing the photoresist layer on the graphene layer, and etching the photoresist layer to obtain a third pattern; A HfO2 layer is formed on the graphene layer by using an ALD atomic layer deposition coating method, and the photoresist on the graphene layer is removed by using an NMP solution to obtain a coating layer coated on the graphene layer.

8. The method for preparing a graphene field effect transistor integrated device according to claim 1, characterized in that: The substrate is a PI film, and the thickness of the film is 10-25 μm.

9. A graphene field effect transistor integrated device, characterized in that: It is prepared by the method for preparing a graphene field effect transistor integrated device as described in any one of claims 1 to 8.

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