SGT device and preparation method thereof
By designing the structure of single-gate and double-gate trench in SGT devices and adopting specific oxide layer and polysilicon layer deposition processes, the cell density of the device is improved, and the high source-drain series resistance in the prior art is solved. The problem of Rsp reduction and Qgd optimization are achieved.
Patent Information
- Application Number
- CN202410186179.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-02-20
- Publication Date
- 2024-12-17
- Estimated Expiration
- 2044-02-20
AI Technical Summary
The trench depth and width of existing SGT devices are relatively large, resulting in limited cell size, which cannot effectively reduce the source-drain series resistance (Rsp), and cannot meet the growing application needs.
Design an SGT device, including a single gate trench and a double gate trench on a semiconductor substrate, the gate group consists of a single gate structure and a double gate structure, and the contact hole structure is symmetrically connected to the side of the single gate. The well/body region is located on both sides of the double gate structure, the source region is arranged on the upper surface of the well/body region, and the device cell density is increased by a specific oxide layer and polysilicon layer deposition process.
By increasing the cell density, the Rsp of the device is effectively reduced, and the Qgd and overall performance index of the device are optimized, meeting the need to reduce the source-drain series resistance.
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Figure CN117747672B_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to an SGT device and a method for preparing the same. Background Art
[0002] In the semiconductor manufacturing process, SGT (Shield Gate Trench) MOSFET is a new type of power semiconductor device. It has the advantages of low conduction loss of traditional deep trench MOSFET in the medium and low voltage fields, and has lower switching loss. As a switching device, SGT MOSFET is used in motor drive systems, inverter systems and power management systems in the fields of new energy electric vehicles, new photovoltaic power generation, energy-saving home appliances, etc., and is a core power control component.
[0003] The SGT structure in the related technology usually has a large trench depth-to-width ratio. Due to the process technology limitations of the trench, contact hole and terrace spacing (the spacing between the trench and the contact hole), the cell size is relatively limited. This is obviously not in line with the existing industry's continuous demand to reduce Rsp (source-drain series resistance) application requirements. This situation needs to be changed. Summary of the invention
[0004] In view of this, the present application provides an SGT device and a preparation method thereof, which improves the device cell density and reduces the device Rsp.
[0005] To achieve the above objectives, according to the first aspect, the technical solution adopted is:
[0006] An SGT device, comprising:
[0007] A semiconductor substrate, wherein a single-gate trench and a double-gate trench are formed on the semiconductor substrate, and the double-gate trenches are arranged at intervals on both sides of the single-gate trench;
[0008] a gate group, the gate group comprising a single gate structure disposed in the single gate trench and a double gate structure disposed in the double gate trench;
[0009] A contact hole structure, wherein the contact hole structure is opened on the semiconductor substrate and symmetrically connected to the side of the single gate structure, and a metal lead-out layer is deposited on the contact hole structure;
[0010] A well / body region, wherein the well / body region is disposed on the semiconductor substrate and is located on both sides of the dual-gate structure, and the well / body region located on one side of the dual-gate structure extends to the contact hole structure;
[0011] A source region is disposed on the semiconductor substrate and is arranged correspondingly on the upper surface of the well / body region.
[0012] The present application is further configured as follows: the single gate structure includes a first oxide layer and a first polysilicon layer, the first oxide layer is grown on the groove wall of the single gate trench, and the first polysilicon layer is deposited on the first oxide layer.
[0013] The present application is further configured as follows: the dual-gate structure includes the first oxide layer, the first polysilicon layer, and a second oxide layer and a second polysilicon layer, the first oxide layer is grown on the groove wall of the dual-gate trench, the first polysilicon layer is deposited on the first oxide layer, the second oxide layer is grown on the groove wall of the dual-gate trench and covers the first polysilicon layer, and the second polysilicon layer is deposited on the second oxide layer.
[0014] The present application is further configured as follows: an interlayer dielectric layer is deposited on the first polysilicon layer of the single gate structure and the second polysilicon layer of the double gate structure, the interlayer dielectric layer is flush with the top surface of the semiconductor substrate, and the first oxide layer of the single gate structure and the second oxide layer of the double gate structure are flush with the top surface of the semiconductor substrate.
[0015] The present application is further configured as follows: it also includes a front metal layer and a back metal layer, the front metal layer is arranged on the top surface of the semiconductor substrate and is respectively connected to the interlayer dielectric layer, the contact hole structure and the source region, and the back metal layer is arranged on the side of the semiconductor substrate away from the front metal layer.
[0016] The present application is further configured that: the material forming the interlayer dielectric layer includes TEOS and BPSG materials.
[0017] The present application is further configured as follows: the well / body region has a first conductivity type, the source region has a second conductivity type, the first conductivity type includes a P type, and the second conductivity type includes an N type.
[0018] According to the second aspect, the technical solution adopted is:
[0019] A method for preparing an SGT device, comprising:
[0020] Providing a semiconductor substrate, etching a single-gate trench and a double-gate trench on the semiconductor substrate, wherein the double-gate trenches are arranged at intervals on both sides of the single-gate trench;
[0021] Forming a first oxide layer on the single-gate trench and the double-gate trench by a diffusion growth process and a thin film deposition process, and forming a sacrificial oxide layer on the semiconductor substrate;
[0022] Depositing a first polysilicon layer in the single-gate trench and the double-gate trench by a thin film deposition process and etching back once to obtain a single-gate structure in the single-gate trench;
[0023] Photolithography and exposure of the dual-gate trench, etching the first polysilicon layer in the dual-gate trench to a first set depth, and wet removal of the sacrificial oxide layer;
[0024] Forming a second oxide layer on the dual-gate trench by a furnace tube thermal growth process, wherein the second oxide layer covers the first polysilicon layer in the dual-gate trench, depositing a second polysilicon layer on the second oxide layer and etching back for a second time, thereby obtaining a dual-gate structure in the dual-gate trench;
[0025] Self-aligning the single-gate trench and the double-gate trench, and sequentially forming a well / body region and a source region through ion implantation and annealing processes;
[0026] After etching back the first polysilicon layer of the single-gate trench and the second polysilicon layer of the double-gate trench to a second set depth three times, depositing and reflowing at high temperature for planarization to form an interlayer dielectric layer;
[0027] Photolithographically exposing a contact hole pattern on the semiconductor substrate, self-aligning the single-gate trench, and ion implanting the contact hole pattern to form the contact hole structure;
[0028] A metal material is deposited in the contact hole structure to form a metal lead-out layer, and a metal is deposited on the semiconductor substrate to form a front metal layer and a back metal layer.
[0029] The present application is further configured as follows: the etching to obtain a single-gate trench and a double-gate trench specifically includes:
[0030] Depositing a silicon dioxide thin film layer on the semiconductor substrate;
[0031] Using the silicon dioxide film layer as a hard mask, photolithography and exposure of a groove pattern;
[0032] The single-gate trench and the double-gate trench are obtained by dry etching the trench pattern on the semiconductor substrate;
[0033] The silicon dioxide thin film layer is removed.
[0034] The present application is further configured as follows: the ion implantation type for forming the contact hole structure is the same as the ion implantation type for forming the well / body region, and the junction depth of the well / body region is greater than the second set depth.
[0035] In summary, compared with the prior art, the present application discloses an SGT device and a preparation method thereof, wherein a single gate trench and a double gate trench are provided on a semiconductor substrate, a single gate structure of a gate group is provided in the single gate trench, a double gate structure is provided in the double gate trench, and a contact hole structure is provided on the semiconductor substrate and symmetrically connected to the side of the single gate structure, a well / body region is provided on the semiconductor substrate and located on both sides of the double gate structure, and a source region is provided on the semiconductor substrate and arranged correspondingly on the upper surface of the well / body region. That is, through the above-mentioned arrangement, the formed double-single-double gate SGT device improves the device cell density, achieves the purpose of reducing the device Rsp, and effectively reduces the device Qgd. BRIEF DESCRIPTION OF THE DRAWINGS
[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.
[0037] Figure 1 is a schematic structural diagram of the first SGT device of this embodiment;
[0038] Figure 2 is a schematic structural diagram of a second SGT device of this embodiment;
[0039] Figure 3 is a schematic structural diagram of a third SGT device of this embodiment;
[0040] Figure 4 is a schematic structural diagram of a fourth SGT device of this embodiment;
[0041] Figure 5 is a schematic structural diagram of the fifth SGT device of this embodiment;
[0042] Figure 6 is a schematic structural diagram of a sixth SGT device of this embodiment;
[0043] Figure 7 is a schematic structural diagram of the seventh SGT device of this embodiment;
[0044] Figure 8 is a schematic diagram of the planar structure of the SGT device of this embodiment;
[0045] Fig. 9 4 is a flow chart of the method for preparing the SGT device of this embodiment. DETAILED DESCRIPTION
[0046] Here, exemplary embodiments will be described in detail, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are only examples of devices and methods consistent with some aspects of the present application as detailed in the attached claims.
[0047] It should be noted that, in this article, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element. In addition, components, features, and elements with the same name in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined by their explanation in the specific embodiment or further combined with the context of the specific embodiment.
[0048] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.
[0049] In the subsequent description, the suffixes such as "module", "component" or "unit" used to represent elements are only used to facilitate the description of the present application, and have no specific meanings. Therefore, "module", "component" or "unit" can be used in a mixed manner.
[0050] In the description of the present application, it should be noted that the terms "upper", "lower", "left", "right", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.
[0051] The technical solutions shown in this application will be described in detail below through specific embodiments. It should be noted that the description order of the following embodiments is not intended to limit the priority order of the embodiments.
[0052] As described in the background technology, the SGT device in the related art usually has a large trench depth-to-width ratio. Due to the process technology limitations of the trench, contact hole and terrace spacing (the spacing between the trench and the contact hole), the cell size is relatively limited, which does not meet the application requirements of continuously reducing Rsp (source-drain series resistance). Therefore, this embodiment discloses an SGT device and a preparation method thereof.
[0053] refer to Figure 7 and Figure 8 The SGT device includes a semiconductor substrate 1, a gate group 2, a contact hole structure 5, a well / body region 6 and a source region 7, wherein a single gate trench 11 and a double gate trench 12 are provided on the semiconductor substrate 1, and the double gate trenches 12 are arranged at intervals on both sides of the single gate trench 11, and the gate group 2 includes a single gate structure 3 provided in the single gate trench 11, and a double gate structure 4 provided in the double gate trench 12, further, the contact hole structure 5 is provided on the semiconductor substrate 1, and is symmetrically connected to the side of the single gate structure 3, a metal lead-out layer 51 is deposited on the contact hole structure 5, the well / body region 6 is provided on the semiconductor substrate 1, and is located on both sides of the double gate structure 4, the well / body region 6 located on one side of the double gate structure 4 extends to the contact hole structure 5, and the source region 7 is provided on the semiconductor substrate 1, and is correspondingly arranged on the upper surface of the well / body region 6.
[0054] The semiconductor substrate 1 of the present embodiment may be formed of materials such as single crystal silicon, polycrystalline silicon, amorphous silicon or doped silicon. The material of the semiconductor substrate 1 may also be a SiGe substrate, a III-V group element compound substrate, a silicon carbide substrate or a stacked structure thereof, or a silicon-on-insulator structure. It may also be a diamond substrate or other semiconductor material substrates known to those skilled in the art. For example, P atoms may be implanted into single crystal silicon to form an N-type conductive semiconductor substrate, and B atoms may be implanted into single crystal silicon to form a P-type conductive semiconductor substrate, so as to improve the selectivity of the material and its adaptability to the actual production environment.
[0055] In some embodiments, a buried layer and an epitaxial layer stacked in sequence may be formed on the semiconductor substrate 1 , and in this case, the functional layers of the semiconductor device may all be formed on the epitaxial layer.
[0056] In the specific implementation process, based on the structural design of the single gate structure 3 and the double gate structure 4, the polysilicon gate of the SGT device is completely buried in the trench, and the formed double-single-double gate structure layout increases the cell density of the SGT device and achieves the purpose of reducing Rsp.
[0057] Furthermore, the single gate structure 3 may include a first oxide layer 31 and a first polysilicon layer 32 , wherein the first oxide layer 31 is grown on the wall of the single gate trench 11 , and the first polysilicon layer 32 is deposited on the first oxide layer 31 .
[0058] The dual-gate structure 4 may include a first oxide layer 31, a first polysilicon layer 32, and a second oxide layer 41 and a second polysilicon layer 42, wherein the first oxide layer 31 is grown on the wall of the dual-gate trench 12, the first polysilicon layer 32 is deposited on the first oxide layer 31, the second oxide layer 41 is grown on the wall of the dual-gate trench 12 and covers the first polysilicon layer 32, and the second polysilicon layer 42 is deposited on the second oxide layer 41.
[0059] That is, compared with the single gate structure 3, the dual gate structure 4 has a double-layer polysilicon structure. In this embodiment, the trench depths of the single gate trench 11 and the dual gate trench 12 can be set to be the same. The deposition height of the first polysilicon layer 32 separated by the second oxide layer 41 of the dual gate structure 4 is smaller than the first oxide layer 31 of the single gate structure 3.
[0060] Furthermore, an interlayer dielectric layer 8 is deposited on the first polysilicon layer 32 of the single gate structure 3 and the second polysilicon layer 42 of the double gate structure 4, and the interlayer dielectric layer 8 is flush with the top surface of the semiconductor substrate 1, and the first oxide layer 31 of the single gate structure 3 and the second oxide layer 41 of the double gate structure 4 are flush with the top surface of the semiconductor substrate 1, thereby ensuring that the polysilicon gate of the SGT device is completely buried in the trench, and the planarization of the interlayer dielectric layer 8 relative to the semiconductor substrate 1 can eliminate the space occupied by the surface gate-source dielectric isolation between the source / body contact and the polysilicon gate of the SGT device, thereby improving the cell density, reducing the crosstalk effect between the gate and the source, and ultimately reducing the device Rsp.
[0061] In the specific implementation process, the SGT device also includes a front metal layer 9 and a back metal layer 13. The front metal layer 9 is arranged on the top surface of the semiconductor substrate 1, and is respectively connected to the interlayer dielectric layer 8, the contact hole structure 5 and the source region 7, which are used for surface protection and passivation of the SGT device and for providing PAD for the metal lead-out layer 51, thereby providing electrical connection and signal transmission. The back metal layer 13 is arranged on the side of the semiconductor substrate 1 away from the front metal layer 9 to play a drain role.
[0062] It should be noted that the materials used to form the interlayer dielectric layer 8 include TEOS and BPSG materials. TEOS (Tetraethylorthosilicate) has good thermal stability and chemical inertness. During the preparation of the interlayer dielectric layer 8, TEOS can be deposited by chemical vapor deposition (CVD) or physical vapor deposition (PVD) to form a dense silicon dioxide (SiO2) layer. BPSG is a boron and phosphorus-doped SiO2 material that can be deposited on the SGT device by a melting method to provide a better planarization effect and has a lower dielectric constant, which is beneficial to reducing capacitance and crosstalk effects.
[0063] The well / body region 6 of the SGT device in this embodiment has a first conductivity type, and the source region 7 has a second conductivity type. The first conductivity type may include a P type, and the second conductivity type may include an N type, thereby forming a PN junction of the SGT device.
[0064] Based on the above SGT device, this embodiment also discloses a method for preparing the SGT device, referring to Fig. 9 , the preparation method specifically comprises:
[0065] S101 , providing a semiconductor substrate 1 , etching the semiconductor substrate 1 to obtain a single-gate trench 11 and a double-gate trench 12 , wherein the double-gate trenches 12 are arranged at two sides of the single-gate trench 11 at intervals.
[0066] In this step, refer to Figure 1 , etching to obtain a single-gate trench 11 and a double-gate trench 12, which may specifically include: depositing a silicon dioxide film layer 1a on a semiconductor substrate 1; using the silicon dioxide film layer 1a as a hard mask, photolithography and exposing a groove pattern; dry etching on the semiconductor substrate 1 through the groove pattern to obtain a single-gate trench 11 and a double-gate trench 12; after obtaining the single-gate trench 11 and the double-gate trench 12, removing the silicon dioxide film layer 1a.
[0067] In some embodiments, a silicon dioxide thin film layer 1a with a thickness of 500-5000Å can be formed on the semiconductor substrate 1 by a thin film deposition process.
[0068] In some embodiments, the trench depths of the single-gate trench 11 and the double-gate trench 12 obtained by etching may be 0.5 um-6 um.
[0069] S102 , forming a first oxide layer 31 on the single-gate trench 11 and the double-gate trench 12 by a diffusion growth process and a thin film deposition process, and forming a sacrificial oxide layer 31 a on the semiconductor substrate 1 .
[0070] In this step, refer to Figure 2 , a first oxide layer 31 may be formed on the inner walls of the single-gate trench 11 and the double-gate trench 12 by a diffusion growth process, and the thickness of the first oxide layer 31 may be 200-3000Å.
[0071] Furthermore, a sacrificial oxide layer 31a is formed on the surface of the semiconductor substrate 1 through a thin film deposition process. The thickness of the sacrificial oxide layer 31a can be 500-5000Å, and the first oxide layer 31 in the groove and the sacrificial oxide layer 31a on the surface of the semiconductor substrate 1 are connected as a whole.
[0072] S103 , depositing a first polysilicon layer 32 in the single-gate trench 11 and the double-gate trench 12 by a thin film deposition process and etching back once, thereby obtaining a single-gate structure 3 in the single-gate trench 11 .
[0073] In this step, refer to Figure 3 The thickness of the first polysilicon layer 32 deposited by the thin film deposition process can be 6000-12000Å. After the first polysilicon layer 32 is formed, the excess polysilicon is etched back by etching or CMP (chemical polishing method) so that the first polysilicon layer 32 is flush with the top surface of the semiconductor substrate 1.
[0074] The single gate structure 3 may include a first oxide layer 31 and a first polysilicon layer 32 , wherein the first oxide layer 31 is grown on the wall of the single gate trench 11 , and the first polysilicon layer 32 is deposited on the first oxide layer 31 .
[0075] S104 , photolithography and exposure of the dual-gate trench 12 , etching the first polysilicon layer 32 in the dual-gate trench 12 to a first set depth, and wet-removing the sacrificial oxide layer 31 a .
[0076] In this step, the first set depth is set to H1, and H1 can be 0.05-3um.
[0077] S105, forming a second oxide layer 41 on the dual-gate trench 12 through a furnace tube thermal growth process, the second oxide layer 41 covers the first polysilicon layer 32 in the dual-gate trench 12, depositing a second polysilicon layer 42 on the second oxide layer 41 and etching back a second time to obtain a dual-gate structure 4 in the dual-gate trench 12.
[0078] In this step, refer to Figure 4 The thickness of the second oxide layer 41 formed by the furnace tube thermal growth process can be 200-1000Å, and based on the second oxide layer 41, the thickness of the deposited second polysilicon layer 42 can be 2000-8000Å. After the second polysilicon layer 42 is formed, the excess polysilicon is etched back by etching or CMP (chemical polishing), so that the second polysilicon layer 42 is flush with the top surface of the semiconductor substrate 1.
[0079] The dual-gate structure 4 may include a first oxide layer 31, a first polysilicon layer 32, and a second oxide layer 41 and a second polysilicon layer 42, wherein the first oxide layer 31 is grown on the wall of the dual-gate trench 12, the first polysilicon layer 32 is deposited on the first oxide layer 31, the second oxide layer 41 is grown on the wall of the dual-gate trench 12 and covers the first polysilicon layer 32, and the second polysilicon layer 42 is deposited on the second oxide layer 41.
[0080] It can be understood that after the second oxide layer 41 covers the first polysilicon layer 32 in the dual-gate trench 12, it can extend to cover the surface of the semiconductor substrate 1 to facilitate the deposition of the second polysilicon layer 42. After the second polysilicon layer 42 is etched back, part of the second oxide layer 41 on the surface of the semiconductor substrate 1 can be wet removed.
[0081] S106 , the self-aligned single-gate trench 11 and the double-gate trench 12 are formed in sequence through ion implantation and annealing processes to form the well / body region 6 and the source region 7 .
[0082] In this step, refer to Figure 5 The formation of the well / body region 6 and the source region 7 is based on a self-alignment process for the single-gate trench 11 and the double-gate trench 12. P-type impurities can be used for the formation of the well / body region 6, for example, by implanting boron ions into the substrate, while N-type impurities can be used for the formation of the source region 7, for example, by implanting phosphorus or arsenic ions into the substrate, thereby changing its conductive properties.
[0083] The well / body region 6 is formed on both sides of the double gate structure 4 and between the single gate structure 3 and the double gate structure 4 , and the source region 7 is correspondingly arranged on the upper surface of the well / body region 6 .
[0084] S107 , after etching back the first polysilicon layer 32 of the single-gate trench 11 and the second polysilicon layer 42 of the double-gate trench 12 to a second set depth three times, deposit and reflow at high temperature for planarization to form an interlayer dielectric layer 8 .
[0085] In this step, the second set depth is set to H2, and H2 may be 0.05-2.8 um, wherein the etching back of the first polysilicon layer 32 and the second polysilicon layer 42 is performed synchronously.
[0086] It should be noted that the junction depth of the well / body region 6 is greater than the second set depth H2.
[0087] The interlayer dielectric layer 8 is formed of materials including TEOS and BPSG materials, and is planarized by high-temperature reflow. The interlayer dielectric layer 8 is processed by etching or CMP (chemical polishing) to make the interlayer dielectric layer 8 flush with the top surface of the semiconductor substrate 1 .
[0088] S108 , photolithography is performed on the semiconductor substrate 1 to expose a contact hole pattern, self-align the single gate trench 11 , and ion implantation is performed on the contact hole pattern to form a contact hole structure 5 .
[0089] refer to Figure 6 The contact hole structure 5 is symmetrically connected to the side of the single gate structure 3, and the well / body region 6 and the source region 7 located on one side of the double gate structure 4 extend to the contact hole structure 5, wherein the ion implantation type for forming the contact hole structure 5 is the same as the ion implantation type for forming the well / body region 6.
[0090] S109 , depositing metal material in the contact hole structure 5 to form a metal lead-out layer 51 , and depositing metal on the semiconductor substrate 1 to form a front metal layer 9 and a back metal layer 13 .
[0091] In this step, refer to Figure 7 The metal material forming the metal lead-out layer 51 may include one or more of Ti, TiN or W, and the material forming the front metal layer 9 may include Al.
[0092] In some embodiments, the metal material forming the metal lead-out layer 51 may further include Co.
[0093] After the front metal layer 9 is formed, a hole may be opened on the front metal layer 9 in coordination with the metal lead-out layer 51 .
[0094] It can be understood that in SGT devices, Rsp stands for Source-Drain On-Resistance, which refers to the resistance between the source and drain when the device is on. A smaller Rsp value indicates a lower on-resistance, while Qgd stands for Gate-Source Charge, which refers to the change in gate charge during the switching process. A larger Qgd value may result in slower switching speeds. FOM, as a performance indicator, is the product of Qgd and Rsp, and is used to evaluate the comprehensive performance of the device in terms of switching speed and on-resistance.
[0095] In the SGT device formed by the preparation method of the SGT device, a single gate trench 11 and a double gate trench 12 are opened on the semiconductor substrate 1, a single gate structure 3 of the gate group 2 is arranged in the single gate trench 11, and a double gate structure 4 is arranged in the double gate trench 12, and a contact hole structure 5 formed by ion implantation of the self-aligned single gate trench 11 is opened on the semiconductor substrate 1 and symmetrically connected to the side of the single gate structure 3, a well / body region 6 formed by ion implantation of the self-aligned single gate trench 11 and the double gate trench 12 is arranged on the semiconductor substrate 1 and located on both sides of the double gate structure 4, a source region 7 is arranged on the semiconductor substrate 1 and arranged correspondingly on the upper surface of the well / body region 6, and an interlayer dielectric layer 8 on the single gate structure 3 and the double gate structure 4 is flush with the top surface of the semiconductor substrate 1, so that the double-single-double gate SGT device formed thereby improves the device cell density, thereby achieving the purpose of reducing the device Rsp, and effectively reducing the device Qgd, and further optimizing the FOM (FOM=Qgd*Rsp) of the SGT device.
[0096] The above is a detailed introduction to the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the core idea of the present application. At the same time, for technical personnel in this field, according to the idea of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.
Claims
1. A method for preparing a SGT device, characterized in that: include: A semiconductor substrate is provided, and a single-gate trench and a double-gate trench are etched on the semiconductor substrate, wherein the double-gate trenches are arranged at intervals on both sides of the single-gate trench, and the trench depths of the single-gate trench and the double-gate trench are within a range of 0.5um-6um; The single-gate trench and the double-gate trench are formed by a diffusion growth process and a thin film deposition process. A first oxide layer having a thickness of Thickness of sacrificial oxide layer; Depositing in the single-gate trench and the double-gate trench by a thin film deposition process A first polysilicon layer of thickness is formed and etched back once to obtain a single gate structure in the single gate trench, wherein the single gate structure comprises the first oxide layer and the first polysilicon layer, the first oxide layer is grown on the groove wall of the single gate trench, and the first polysilicon layer is deposited on the first oxide layer; Photolithography and exposure of the dual-gate trench, etching the first polysilicon layer in the dual-gate trench to a first set depth, and wet removal of the sacrificial oxide layer, wherein the first set depth is 0.05-3 um; The double-gate trench is formed by a furnace thermal growth process. A second oxide layer of a thickness of , the second oxide layer covers the first polysilicon layer in the dual-gate trench, and a second oxide layer is deposited on the second oxide layer A second polysilicon layer of thickness is formed and etched back twice to obtain a double-gate structure in the double-gate trench, wherein the double-gate structure includes the first oxide layer, the first polysilicon layer, the second oxide layer and the second polysilicon layer, the first oxide layer is grown on the trench wall of the double-gate trench, the first polysilicon layer is deposited on the first oxide layer, the second oxide layer is grown on the trench wall of the double-gate trench and covers the first polysilicon layer, the second polysilicon layer is deposited on the second oxide layer, and the single-gate structure in the single-gate trench and the double-gate structure in the double-gate trench constitute a gate group of the SGT device; Self-aligning the single-gate trench and the double-gate trench, and sequentially forming a well / body region and a source region through ion implantation and annealing processes; After etching back the first polysilicon layer of the single-gate trench and the second polysilicon layer of the double-gate trench to a second set depth three times, depositing and reflowing at high temperature to flatten an interlayer dielectric layer, wherein the second set depth is 0.05-2.8 um, and the interlayer dielectric layer is flush with the top surface of the semiconductor substrate; A contact hole pattern is exposed on the semiconductor substrate by photolithography, the single-gate trench is self-aligned, and ions are implanted into the contact hole pattern to form the contact hole structure, wherein the contact hole structure is opened on the semiconductor substrate and symmetrically connected to the side of the single-gate structure, the well / body region is located on both sides of the double-gate structure, the well / body region located on one side of the double-gate structure extends to the contact hole structure, and the source region is arranged correspondingly on the upper surface of the well / body region, wherein the ion implantation type for forming the contact hole structure is the same as the ion implantation type for forming the well / body region, and the junction depth of the well / body region is greater than the second set depth; A metal material is deposited in the contact hole structure to form a metal lead-out layer, and a metal is deposited on the semiconductor substrate to form a front metal layer and a back metal layer.
2. The method for preparing the SGT device according to claim 1, characterized in that: The interlayer dielectric layer is deposited on the first polysilicon layer of the single gate structure and the second polysilicon layer of the double gate structure, the interlayer dielectric layer is flush with the top surface of the semiconductor substrate, and the first oxide layer of the single gate structure and the second oxide layer of the double gate structure are flush with the top surface of the semiconductor substrate.
3. The method for preparing the SGT device according to claim 1, characterized in that: The front metal layer is arranged on the top surface of the semiconductor substrate and is respectively connected to the interlayer dielectric layer, the contact hole structure and the source region. The back metal layer is arranged on a side of the semiconductor substrate away from the front metal layer.
4. The method for preparing the SGT device according to claim 1, characterized in that: The interlayer dielectric layer is formed of materials including TEOS and BPSG materials.
5. The method for preparing the SGT device according to claim 1, characterized in that: The well / body region has a first conductivity type, and the source region has a second conductivity type, wherein the first conductivity type includes a P type, and the second conductivity type includes an N type.
6. The method for preparing the SGT device according to claim 1, characterized in that: The etching to obtain the single-gate trench and the double-gate trench specifically includes: depositing a silicon dioxide film layer on the semiconductor substrate; using the silicon dioxide film layer as a hard mask, photolithography and exposing a groove pattern; dry etching on the semiconductor substrate through the groove pattern to obtain the single-gate trench and the double-gate trench; and removing the silicon dioxide film layer.