Wafer retest method, wafer test system, test machine and readable storage medium

Abstract

The present application relates to a wafer retest method, a wafer test system, a test machine and a readable storage medium. The method is applied to a test machine in a wafer test system, comprising: obtaining a first test result of each chip under test in a wafer under test; based on the first test result, calculating the wafer yield and the first test yield of the wafer under test; in the case where the first test yield does not reach a preset yield condition, triggering a wafer retest process, comprising: sending a shift instruction and a test instruction to a probe station to perform a retest on a target chip under test in the wafer under test; updating the wafer yield of the wafer under test based on the retest result of the target chip under test after each retest; in the case where the wafer yield meets a preset retest stop condition or the number of retests reaches a preset number of retests, sending a wafer shift instruction to the probe station to stop the wafer retest process, thereby solving the problem of low wafer retest efficiency caused by manual retest judgment and retest process control.

Description

Technical Field

[0001] The present application relates to the field of chip testing, and in particular to a wafer retesting method, a wafer testing system, a testing machine and a readable storage medium. Background Art

[0002] The equipment for wafer testing is mainly a tester and a probe station, which are connected by communication. The probe station moves the probe to the specified chip and sends the chip coordinates to the tester; the tester completes the chip test and sends the test results to the probe station. After the first wafer test, it is sometimes necessary to retest the chips with failed test results. The purpose of retesting is mainly to analyze the reasons for the test failure and improve the test yield. Currently, after the first test is completed, the test engineer usually determines whether to retest the failed chip based on the first test results. If retesting is required, the test engineer controls the probe station to move the probe to the chip that needs to be retested and sends the chip coordinates to the tester to complete the chip retest. Since manual retesting judgment and retesting process control are required, the efficiency of wafer retesting is low. Summary of the invention

[0003] In this embodiment, a wafer retest method, a wafer testing system, a testing machine and a readable storage medium are provided to solve the problem of low wafer retest efficiency caused by manual retest judgment and retest process control in the related art.

[0004] In a first aspect, a wafer retest method is provided in this embodiment, the method is applied to a tester in a wafer test system, the wafer test system further comprising a probe station communicating with the tester, the method comprising:

[0005] Obtain the first test result of each chip under test in the tested wafer;

[0006] Based on the first test result, the wafer yield and the first test yield of the tested wafer are calculated;

[0007] When the first test yield fails to meet the preset yield condition, a wafer retest process is triggered, and the wafer retest process includes: sending a shift instruction and a test instruction to the probe station, performing at least one retest on the target chip under test in the wafer under test, the target chip under test is the chip under test whose test result in the last test is a failure; after each retest, updating the wafer yield of the wafer under test based on the retest result of the target chip under test; when the wafer yield meets the preset retest stop condition, or the number of retests reaches the preset number of retests, sending a wafer shift instruction to the probe station to stop the wafer retest process, and the retest stop condition includes that the wafer yield is greater than or equal to a first preset threshold, or the difference between the wafer yield and the first test yield is greater than a second preset threshold.

[0008] In some embodiments, obtaining the first test result of each chip under test in the wafer under test includes:

[0009] Execute the test item and obtain the test data of the chip under test, wherein the test data includes the coordinates of the chip under test and the corresponding test result;

[0010] The coordinates of the chip under test are queried in the stored result data record. If the coordinates are not found, the test result is determined to be the first test result of the chip under test, and the coordinates are stored in the result data record.

[0011] In some embodiments, performing at least one retest on the target chip under test in the wafer under test, and updating the wafer yield of the wafer under test based on the retest result of the target chip under test after each retest includes:

[0012] Retesting the target chip under test whose test result was failed in the last test and obtaining corresponding test data, wherein the target chip under test for the first retest is the chip under test whose test result was failed in the first test;

[0013] querying the coordinates in the test data in the result data record, and determining, when the coordinates are found, that the test result corresponding to the coordinates is the retest result of the target chip under test;

[0014] Based on the retest result of the target chip under test, the wafer yield of the wafer under test is updated.

[0015] In some embodiments, after updating the wafer yield of the wafer under test based on the retest result of the target chip under test after each retest, the method further includes:

[0016] When the difference between the wafer yield and the first-measurement yield is greater than a first alarm threshold, or less than a second alarm threshold, a corresponding alarm message is generated, and the re-measurement is stopped.

[0017] In a second aspect, a wafer testing system is provided in this embodiment, including a testing machine and a probe station communicating with the testing machine, wherein the testing machine is used to retest the wafer under test based on the wafer retest method described in the first aspect.

[0018] In some of the embodiments, when retesting a target chip under test whose test result was a failure in the last test, the test machine obtains the coordinates of the target chip under test, and sends the coordinates and a shift instruction to the probe station, so that the probe of the probe station moves to the target chip under test;

[0019] The test machine sends a test instruction to the probe station, receives a loading signal sent by the probe station, and executes a test item on the target chip under test based on the loading signal.

[0020] In some of the embodiments, the tester determines whether to start automatic retesting after completing the first test of the wafer under test and receiving a wafer closure signal sent by the probe station;

[0021] When the automatic retest is started, the test machine automatically retests the wafer under test.

[0022] In some embodiments, when the wafer yield satisfies the retest stop condition or the number of retests reaches a preset number of retests, the test machine sends a wafer shifting instruction to the probe station, and the probe station performs wafer bonding processing on the wafer under test based on the wafer shifting instruction.

[0023] In a third aspect, a testing machine is provided in this embodiment, and the testing machine includes:

[0024] An acquisition module is used to obtain the first test result of each tested chip in the tested wafer;

[0025] A calculation module, used for calculating the wafer yield and the first test yield of the tested wafer based on the first test result;

[0026] A retest module is used to trigger a wafer retest process when the first test yield does not meet the preset yield condition, and the wafer retest process includes: sending a shift instruction and a test instruction to the probe station, performing at least one retest on the target chip under test in the tested wafer, the target chip under test is the chip under test whose test result in the last test is a failure; after each retest, updating the wafer yield of the tested wafer based on the retest result of the target chip under test; when the wafer yield meets the preset retest stop condition, or the number of retests reaches the preset number of retests, sending a wafer shift instruction to the probe station to stop the wafer retest process, and the retest stop condition includes that the wafer yield is greater than or equal to a first preset threshold value, or the difference between the wafer yield and the first test yield is greater than a second preset threshold value.

[0027] In a fourth aspect, a readable storage medium is provided in this embodiment, on which a program is stored, and when the program is executed by a processor, the steps of the wafer retest method described in the first aspect are implemented.

[0028] Compared with the related art, the wafer retest method provided in the present embodiment obtains the first test result of each tested chip in the tested wafer through the test machine, and calculates the wafer yield and the first test yield of the tested wafer based on the first test result, and obtains the test statistical data of the wafer, which can be sent to the factory system software for further analysis; by triggering the wafer retest process when the first test yield does not reach the preset yield condition, the shift instruction and the test instruction are automatically sent to the probe station, and the tested chip with a failed test result in the last test is retested at least once, and the wafer yield is updated according to the retest result until the retest stop condition is met or the preset number of retests is reached, and the retest judgment and retest process control are automatically performed without the intervention of the operator, and the wafer yield is improved through retesting, which solves the problem of low wafer retest efficiency caused by manual retest judgment and retest process control in the related art, thereby improving the wafer retest efficiency.

[0029] Details of one or more embodiments of the present application are set forth in the following drawings and description to make other features, objects, and advantages of the present application more readily apparent. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0031] Figure 1 is a structural block diagram of a wafer testing system in some embodiments of the present application;

[0032] Figure 2 is a flow chart of a wafer retest method according to some embodiments of the present application;

[0033] Figure 3 is a flow chart of obtaining the first test results of each tested chip in the tested wafer in some embodiments of the present application;

[0034] Figure 4 is a flow chart of performing retest on a target chip under test and updating wafer yield in some embodiments of the present application;

[0035] Figure 5 is a communication diagram between a test machine and a probe station in some embodiments of the present application;

[0036] Figure 6 is a flow chart of a wafer retest method according to some preferred embodiments of the present application;

[0037] Figure 7 is a flow chart of automatic wafer retesting of some preferred embodiments of the present application;

[0038] Figure 8It is a structural block diagram of a test machine of some embodiments of the present application. DETAILED DESCRIPTION

[0039] In order to more clearly understand the purpose, technical solutions and advantages of the present application, the present application is described and illustrated below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0040] Unless otherwise defined, the technical terms or scientific terms involved in this application shall have the general meaning understood by people with general skills in the technical field to which this application belongs. The words "one", "a", "the", "these" and the like in this application do not indicate a quantitative limitation, and they may be singular or plural. The terms "include", "comprise", "have" and any variants thereof involved in this application are intended to cover non-exclusive inclusions; for example, a process, method and system, product or device comprising a series of steps or modules (units) is not limited to the listed steps or modules (units), but may include unlisted steps or modules (units), or may include other steps or modules (units) inherent to these processes, methods, products or devices. The words "connect", "connected", "coupled" and the like involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The "multiple" involved in this application refers to two or more. "And / or" describes the association relationship of associated objects, indicating that there may be three relationships, for example, "A and / or B" may mean: A exists alone, A and B exist at the same time, and B exists alone. Generally, the character " / " indicates that the objects associated with each other are in an "or" relationship. The terms "first", "second", "third", etc. in this application are only used to distinguish similar objects and do not represent a specific ordering of the objects.

[0041] The wafer retest method provided in the embodiment of the present application can be executed in a tester in a wafer test system. Figure 1 is a structural block diagram of a wafer testing system in some embodiments of the present application. Figure 1 As shown, the wafer testing system includes a tester 10 and a probe station 12 that communicates with the tester 10. The tester 10 can provide functions such as power supply, instrumentation and signal processing to perform electrical characteristic tests and functional verification on the chip under test. According to different test requirements, the tester can perform a variety of tests such as voltage, current, power, frequency, timing, etc. The probe station 12 provides a platform for fixing and supporting the test probes to ensure that the probes can stably contact the test points on the chip under test. Specifically, the communication method between the tester 10 and the probe station 12 may include but is not limited to the GPIB bus. A person of ordinary skill in the art can understand that Figure 1The structure shown is only for illustration and does not limit the structure of the above-mentioned wafer testing system. Figure 1 More or fewer components as shown, or with Figure 1 Different configurations shown.

[0042] This embodiment provides a wafer retest method. Figure 2 is a flow chart of a wafer retest method according to some embodiments of the present application. Figure 2 As shown, the process includes the following steps:

[0043] Step S201, obtaining the first test result of each chip under test in the wafer under test.

[0044] The wafer includes multiple chips (dies) to be tested, and the physical position of each chip to be tested can be described by coordinates. During the chip testing process, the probe station obtains the coordinates of each chip to be tested, moves the probe to the corresponding chip to be tested, and transmits the test signal sent by the tester to the corresponding pin of the chip to be tested through the contact between the probe and the chip to be tested, and transmits the result signal on the corresponding pin of the chip to the tester. The tester determines the test result based on the result signal, and the test result includes Pass and Fail.

[0045] For batch wafer testing, when the tester receives the communication signal sent by the probe station, it performs corresponding actions according to the type of communication signal. Specifically, the communication signal can be a wafer opening signal, a material loading signal, a wafer closing signal, a batch closing signal, etc. The wafer opening signal is used to prepare for the test of the wafer under test; the material loading signal is used to start the chip testing process for one or more chips under test on the wafer under test, and obtain the corresponding test results and send them to the probe station; the wafer closing signal is used to end the test process of the wafer under test; and the batch closing signal is used to end the wafer test of the entire batch.

[0046] In this embodiment, each chip under test on the wafer under test can be tested in sequence based on the loading signal, and corresponding test results can be obtained. The first test result refers to the test result of the first test of each chip under test.

[0047] Step S202, based on the initial test result, the wafer yield and the initial test yield of the tested wafer are calculated.

[0048] The test machine counts the first test results of all the tested chips on the tested wafer and calculates the wafer yield and first test yield of the tested wafer. Among them, wafer yield = number of chips with a test result of Pass / total number of chips; first test yield = number of chips with a first test result of Pass / total number of chips. When only the first test is performed, the wafer yield is equal to the first test yield.

[0049] Step S203, when the first test yield does not meet the preset yield condition, triggering the wafer retest process, the wafer retest process includes: sending shift instructions and test instructions to the probe station, performing at least one retest on the target chip under test in the tested wafer, the target chip under test is the chip under test whose test result in the last test was a failure; after each retest, updating the wafer yield of the tested wafer based on the retest result of the target chip under test; when the wafer yield meets the preset retest stop condition, or the number of retests reaches the preset number of retests, sending a wafer shift instruction to the probe station to stop the wafer retest process, the retest stop condition includes that the wafer yield is greater than or equal to a first preset threshold, or the difference between the wafer yield and the first test yield is greater than a second preset threshold.

[0050] The preset yield condition may be a preset yield threshold or threshold range. If the first test yield does not meet the preset yield condition, the tester may trigger a wafer retest process. The wafer retest process may include one or more retest processes, and each retest process includes three steps: retest, yield update, and stop determination.

[0051] The retest step includes sending a shift instruction and a test instruction to the probe station, and performing a retest on a target chip under test in the wafer under test, wherein the target chip under test is a chip under test whose test result in the last test is a failure.

[0052] The tester determines that the target chip under test whose first test result failed needs to be retested for the first time based on the first test results and corresponding coordinates of all the chips under test on the wafer under test. The tester sends a shift instruction and the coordinates of the target chip under test to the probe station. The probe station moves the probe to the position of the target chip under test based on the coordinates, performs retesting based on the test instruction sent by the tester, and sends the retesting results to the tester.

[0053] In some embodiments, the number of retests and the retest stop condition are preset. If the number of retests is not reached and the retest stop condition is not met, multiple retests will be performed, and each retest is performed according to the same steps. In each retest, the retest object is the target chip under test whose test result was a failure in the previous test. Therefore, the number of chips in each retest cycle is less than or equal to the number of chips in the previous retest cycle. Specifically, the retest object of the first retest cycle is the target chip under test whose first test result was a failure.

[0054] The yield updating step includes: updating the wafer yield of the tested wafer based on the retest result of the target tested chip after each retest.

[0055] After completing a retest, the wafer yield of the tested wafer is updated according to the retest results of all target tested chips. Specifically, the number of target tested chips with a pass result in this retest is counted, and this number is added to the number of chips with a pass test result, and the wafer yield is recalculated to obtain the updated wafer yield of the tested wafer.

[0056] The stop judgment step includes: when the wafer yield meets the preset re-test stop condition, or the number of re-tests reaches the preset number of re-tests, a wafer move instruction is sent to the probe station to stop the wafer re-test process. The re-test stop condition includes that the wafer yield is greater than or equal to a first preset threshold, or the difference between the wafer yield and the initial test yield is greater than a second preset threshold.

[0057] This embodiment can make a stop judgment based on any one of the two parameters of the retest stop condition and the number of retests. Among them, the retest stop condition can be that the wafer yield is greater than or equal to the first preset threshold, or the difference between the wafer yield and the first test yield is greater than the second preset threshold, wherein the first preset threshold can be equal to the yield threshold in the preset yield condition. That is, if the wafer yield after retest is improved to a certain extent, the retest can be stopped. In other embodiments, if the wafer yield does not reach the first preset threshold in the specified number of retests, or the difference between the wafer yield and the first test yield does not reach the second preset threshold, the retest can be stopped when the number of retests is reached to avoid wasting test resources.

[0058] Through steps S201~S203, the first test result of each tested chip in the tested wafer is obtained by the test machine, and based on the first test result, the wafer yield and the first test yield of the tested wafer are calculated to obtain the test statistical data of the wafer, which can be sent to the factory system software for further analysis; when the first test yield does not reach the preset yield condition, the wafer retest process is triggered, and the shift instruction and the test instruction are automatically sent to the probe station, and the tested chip with a failed test result in the last test is retested at least once, and the wafer yield is updated according to the retest result until the retest stop condition is met or the preset number of retests is reached, and the retest judgment and retest process control are automatically performed without the intervention of the operator, and the wafer yield is improved through retesting, which solves the problem of low wafer retest efficiency caused by manual retest judgment and retest process control in the related technology, thereby improving the wafer retest efficiency.

[0059] In some embodiments, Figure 3 is a flow chart of obtaining the first test results of each tested chip in the tested wafer in some embodiments of the present application, such as Figure 3 As shown, the process includes the following steps:

[0060] Step S301, executing the test items and acquiring the test data of the chip under test, wherein the test data includes the coordinates of the chip under test and the corresponding test results.

[0061] After the test machine obtains the test result of the chip under test, it packages the test result and the coordinates of the corresponding chip under test into test data.

[0062] Step S302, querying the coordinates of the chip under test in the stored result data record, and if the coordinates are not found, determining that the test result is the first test result of the chip under test, and storing the coordinates in the result data record.

[0063] The result data record is used to save the coordinates of each chip under test on the wafer under test and the corresponding test results. The record corresponding to the test result Pass is true, otherwise it is false. The test data of each chip under test is parsed to obtain the corresponding X and Y coordinates. Use the X and Y coordinates to query in the result data record. If the coordinates are not found, it is determined that the test result is the first test result of the chip under test, and the first test result and the X and Y coordinates are stored in the result data record.

[0064] If the first test result of the tested chip is Pass, the number of chips with Pass results can be increased by 1, the number of chips with Pass results can be increased by 1, and the total number of tested chips can be increased by 1, and the result data record saves the X and Y coordinate results as true. If the first test result of the tested chip is Fail, the total number of tested chips can be increased by 1, and the result data record saves the X and Y coordinate results as false.

[0065] When the total number of test chips is equal to the total number of chips on the tested wafer, it can be determined that all tested chips have completed the first test. At this time, the wafer yield and first test yield can be calculated based on the number of chips with Pass results in the first test, the number of chips with Pass results in the test, and the total number of test chips.

[0066] Through steps S301~S302, the test items are executed and the test data of the chip under test is obtained as the basic data for determining whether to retest the chip; the coordinates of the chip under test are queried in the stored result data record. If the coordinates are not found, the test result is determined to be the first test result of the chip under test, and the coordinates are stored in the result data record. A database of the coordinates and test results of each chip under test in the wafer under test is established to facilitate data statistics and refresh, thereby improving chip retest efficiency.

[0067] In some embodiments, Figure 4 is a flowchart of performing retest on a target chip under test and updating wafer yield in some embodiments of the present application, such as Figure 4 As shown, the process includes the following steps:

[0068] Step S401 , retesting a target chip under test whose test result was failed in the last test and acquiring corresponding test data, wherein the target chip under test for the first retest is the chip under test whose test result was failed in the first test.

[0069] During a retest process, the tester can retest each target chip under test in turn and obtain corresponding test data, which includes the coordinates of the target chip under test and the corresponding test results.

[0070] Step S402, querying the coordinates in the test data in the result data record, and when the coordinates are found, determining that the test result corresponding to the coordinates is the retest result of the target chip under test.

[0071] Similar to step S302, the test data of the target chip under test is parsed to obtain the corresponding X and Y coordinates. The X and Y coordinates are used to query the result data record, and if the coordinates are found, the test result in the test data is determined to be the retest result of the target chip under test.

[0072] If the retest result is Pass, the number of chips with Pass test result is increased by 1, and the result data record saves the X and Y coordinate results as true. If the retest result is Fail, the data is not updated.

[0073] Step S403 , updating the wafer yield of the wafer under test based on the retest result of the target chip under test.

[0074] After all target chips under test have been retested, the wafer yield is recalculated based on the number of chips with a Pass test result.

[0075] Through steps S401 to S403, by retesting the target chip under test whose test result was a failure in the last test and obtaining corresponding test data, the test result of the target chip under test is updated, and the chip test failure caused by environmental or other external factors is reduced through retesting, thereby improving the test stability of the chip; by querying the coordinates in the test data in the result data record, when the coordinates are queried, it is determined that the test result corresponding to the coordinates is the retest result of the target chip under test, and based on the retest result of the target chip under test, the wafer yield of the tested wafer is updated, thereby improving the wafer yield through retesting.

[0076] In some embodiments, a specific method for abnormal alarm during retesting is also involved. The method includes:

[0077] When the difference between the wafer yield and the first test yield is greater than the first alarm threshold, or less than the second alarm threshold, a corresponding alarm message is generated and retesting is stopped.

[0078] Specifically, during the chip retesting process, the wafer yield is updated after retesting each target chip under test. If the difference between the updated wafer yield and the initial test yield is greater than the first alarm threshold, it means that the wafer yield has increased too much after the retest, and there may be an abnormality in the initial test process, and the initial test data is incorrect. At this time, the corresponding alarm information is generated and the retesting is stopped. It can be checked whether there is an abnormality in the initial test process, eliminate possible risks, and improve the safety and stability of the wafer test system. In a specific embodiment, the first alarm threshold is 5%.

[0079] If the difference between the updated wafer yield and the first test yield is less than the second alarm threshold, it means that there is little room for improvement in the wafer yield and there is no need to continue retesting. At this time, a corresponding alarm message is generated and retesting is stopped to avoid wasting test resources. In a specific embodiment, the second alarm threshold is 1%.

[0080] In some embodiments, a wafer testing system is further provided, including a testing machine and a probe station communicating with the testing machine, wherein the testing machine is used to retest the wafer under test based on the wafer retest method of the above embodiment.

[0081] Figure 5 is a schematic diagram of communication between a test machine and a probe station in some embodiments of the present application, such as Figure 5 As shown, when retesting the target chip under test 14 whose test result in the last test was failure, the test machine 10 obtains the coordinates of the target chip under test 14, and sends the coordinates and shift instructions to the probe station 12, so that the probe of the probe station 12 moves to the target chip under test 14; the test machine 10 sends a test instruction to the probe station 12, and receives a loading signal sent by the probe station 12, and executes the test item on the target chip under test 14 based on the loading signal.

[0082] Specifically, the tester 10 can perform retest on one or more target chips under test 14. When there are multiple target chips under test 14, the retest can be performed in sequence according to a preset order. During the retest, the coordinates and shift instructions of the target chip under test 14 are sent to the probe station 12, so that the probe of the probe station 12 moves to the target chip under test 14. Then a test instruction is sent to the probe station 12, and the probe station 12 completes the connection with the target chip under test 14 according to the test instruction, and sends a loading signal to the tester 10. The tester 10 executes the test item on the target chip under test 14 based on the loading signal to obtain the corresponding retest result.

[0083] The wafer testing system of the present embodiment sends the coordinates and shift instructions of the target chip to be tested to the probe station through the testing machine, and controls the probe station to correctly connect with the chip pins to be retested; sends test instructions to the probe station through the testing machine, and receives the loading signal sent by the probe station, and retests the target chip to be tested based on the loading signal. The testing machine is used as a control device to perform wafer retesting, and the retesting process control is automatically performed without the intervention of an operator, which solves the problem of low wafer retesting efficiency caused by manual retesting process control in related technologies, and improves the wafer retesting efficiency.

[0084] In some embodiments, after completing the first test of the wafer under test and receiving the wafer closure signal sent by the probe station 12, the test machine 10 determines whether to start automatic retesting; when automatic retesting is started, the test machine 10 automatically retests the wafer under test.

[0085] When all the chips under test on the wafer under test have completed the first test, the probe station 12 sends a wafer completion signal to the tester 10. After receiving the wafer completion signal, the tester 10 determines that all the chips under test have completed the first test. At this time, the tester 10 calculates the wafer yield and the first test yield according to the test data corresponding to each chip under test, and determines whether to start the automatic retest according to the first test yield. When it is determined to start the automatic retest, the tester 10 triggers the wafer retest process, including sending a shift instruction and the coordinates of the target chip under test to the probe station 12.

[0086] The wafer testing system of this embodiment determines that all chips under test have completed the first test through the wafer closure signal sent by the probe station, determines the statistics of the wafer yield through the test machine and determines whether to start the automatic retest. When it is determined to start the automatic retest, the wafer retest process is triggered, and the retest judgment and automatic triggering are automatically performed without the intervention of an operator, thereby improving the efficiency of wafer retest.

[0087] In some embodiments, when the wafer yield meets the retest stop condition or the number of retests reaches a preset number of retests, the test machine 10 sends a wafer shifting instruction to the probe station 12, and the probe station 12 performs wafer bonding processing on the wafer under test based on the wafer shifting instruction.

[0088] The tester 10 determines whether to stop the retest process according to the retest stop conditions and the number of retests. If it is determined to stop the retest process, it sends a wafer moving instruction to the probe station 12. The probe station 12 determines that the retest process is ended according to the wafer moving instruction, performs wafer bonding processing on the wafer under test, and completes the test of the wafer under test.

[0089] The wafer retest method of this embodiment is described and illustrated by a preferred embodiment below. The method is applied to a tester in a wafer test system, and the wafer test system also includes a probe station communicating with the tester. Figure 6is a flow chart of a wafer retest method according to some preferred embodiments of the present application, such as Figure 6 As shown, the process includes the following steps:

[0090] Step S601, receiving a communication signal sent by a probe station;

[0091] Step S602, determining whether the communication signal is a start-up signal, if it is a start-up signal, executing the start-up process and returning to step S601;

[0092] Step S603, if it is not a sheet opening signal, determine whether the communication signal is a material loading signal;

[0093] Step S604, if it is a loading signal, execute the test process of the chip under test;

[0094] Step S605, obtaining the first test data of each chip under test;

[0095] Step S606, calculating the wafer yield and the first test yield according to the first test data;

[0096] Step S607, determining whether the current test is an automatic retest process according to the automatic retest flag; if it is not an automatic retest process, returning to step S601;

[0097] Step S608: If it is an automatic retest process, the automatic retest process is executed. The detailed flowchart of the process is shown in FIG. Figure 7 As shown;

[0098] Step S609, after completing the automatic retest process, execute the film closing process and return to step S601;

[0099] Step S610: if the signal in step S603 is not a material loading signal, determine whether the communication signal is a sheet forming signal;

[0100] Step S611, if it is a wafer-clogging signal, determine whether to start automatic retesting according to the first test yield; if automatic retesting is not started, execute step S609;

[0101] Step S612: if automatic retest is started, the automatic retest flag is marked and executed. Figure 7 The automatic retest process shown;

[0102] Step S613, if the signal of step S610 is not a sheet-closing signal, determine whether the communication signal is a batch-closing signal;

[0103] Step S614: If it is a batch closing signal, execute the batch closing process.

[0104] Through steps S601 to S614, by receiving and identifying the communication signal of the probe station, the corresponding wafer opening, loading, wafer binding, and batch binding processes are executed to ensure that the main process of wafer testing is carried out in an orderly manner; by adding the calculation of wafer yield and first test yield in the loading process, data reference is obtained to determine whether to perform automatic wafer retesting; by adding the judgment process of automatic wafer retesting in the wafer binding process, retesting judgment is automatically performed without the intervention of operators, thereby improving the efficiency of wafer retesting; when it is determined to perform wafer retesting, the retesting process is marked to distinguish the retesting process from other test processes, thereby ensuring the orderly execution of the retesting process.

[0105] The automatic retest process in step S608 is as follows: Figure 7 As shown, Figure 7 This is a flow chart of automatic wafer retesting according to some preferred embodiments of the present application.

[0106] Step S701, obtaining the wafer yield, first test yield, yield target, yield improvement target, and number of wafer retests of the wafer under test;

[0107] Step S702, determining whether the difference between the wafer yield and the first test yield is greater than a first alarm threshold or less than a second alarm threshold;

[0108] Step S703: If yes, stop the retest process;

[0109] Step S704, sending a sheet moving instruction to the probe station;

[0110] Step S705, executing the film bonding process;

[0111] Step S706, if not, determine whether the wafer yield reaches the yield target, if so, proceed to step S703;

[0112] Step S707, if not, determine whether the difference between the wafer yield and the first test yield reaches the yield improvement target, if so, proceed to step S703;

[0113] Step S708, if not, determine whether the preset number of retests has been reached, if so, proceed to step S703;

[0114] Step S709, if not, sending a shift instruction and the coordinates of the target chip to be tested to the probe station;

[0115] Step S710, sending a test instruction to the probe station;

[0116] Step S711, retesting the target chip under test;

[0117] Step S712, determining whether all target chips under test have completed retesting; if so, proceeding to step S701, otherwise, proceeding to step S709.

[0118] Through steps S701~S712, by determining whether the wafer yield meets the yield target or the yield improvement target, the yield improvement is used as the end condition of wafer retest, so as to achieve yield improvement through wafer retest, and improve the wafer yield while realizing automatic retest; by using the number of retries and alarm thresholds as the end conditions of wafer retest, the safety of wafer retest is improved and the waste of test resources is avoided; by controlling the connection between the probe station and the target chip under test to perform chip retest, the retest judgment and retest process control are automatically performed without the intervention of operators, thereby improving the efficiency of wafer retest.

[0119] This embodiment also provides a testing machine, Figure 8 is a structural block diagram of a test machine in some embodiments of the present application, such as Figure 8 As shown, the test machine includes:

[0120] An acquisition module 81 is used to acquire the first test result of each tested chip in the tested wafer;

[0121] A calculation module 82 is used to calculate the wafer yield and the first test yield of the tested wafer based on the first test result;

[0122] The retest module 83 is used to trigger the wafer retest process when the first test yield does not meet the preset yield condition. The wafer retest process includes: sending shift instructions and test instructions to the probe station, performing at least one retest on the target chip under test in the tested wafer, and the target chip under test is the chip under test whose test result in the last test is a failure; after each retest, updating the wafer yield of the tested wafer based on the retest result of the target chip under test; when the wafer yield meets the preset retest stop condition, or the number of retests reaches the preset number of retests, sending a wafer shift instruction to the probe station to stop the wafer retest process, and the retest stop condition includes that the wafer yield is greater than or equal to a first preset threshold, or the difference between the wafer yield and the first test yield is greater than a second preset threshold.

[0123] The test machine of the present embodiment obtains the first test result of each tested chip in the tested wafer through the acquisition module 81, and calculates the wafer yield and the first test yield of the tested wafer based on the first test result through the calculation module 82, and obtains the test statistical data of the wafer, and the test statistical data can be sent to the factory system software for further analysis; through the re-test module 83, when the first test yield does not reach the preset yield condition, the wafer re-test process is triggered, and the shift instruction and the test instruction are automatically sent to the probe station, and the tested chip with a failed test result in the last test is re-tested at least once, and the wafer yield is updated according to the re-test result until the re-test stop condition is met or the preset re-test number is reached, and the re-test judgment and re-test process control are automatically performed without the intervention of the operator, and the wafer yield is improved through re-testing, which solves the problem of low wafer re-testing efficiency caused by manual re-test judgment and re-testing process control in the related art, thereby improving the wafer re-testing efficiency.

[0124] In addition, in combination with the wafer retest method provided in the above embodiments, a readable storage medium may be provided in this embodiment to implement the method. The readable storage medium stores a program; when the program is executed by a processor, any one of the wafer retest methods in the above embodiments is implemented.

[0125] It should be noted that the specific examples in this embodiment can refer to the examples described in the above embodiments and optional implementation modes, and will not be repeated in this embodiment.

[0126] It should be understood that the specific embodiments described herein are only used to explain the application, rather than to limit it. Based on the embodiments provided in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the protection scope of this application.

[0127] Obviously, the drawings are only some examples or embodiments of the present application. For ordinary technicians in the field, the present application can also be applied to other similar situations based on these drawings without creative work. In addition, it is understandable that although the work done in this development process may be complicated and lengthy, for ordinary technicians in the field, certain changes in design, manufacturing or production based on the technical content disclosed in this application are only conventional technical means and should not be regarded as insufficient content disclosed in this application.

[0128] The term "embodiment" in this application refers to a specific feature, structure or characteristic described in conjunction with the embodiment that can be included in at least one embodiment of the present application. The appearance of this phrase in various locations in the specification does not necessarily mean the same embodiment, nor does it mean that it is mutually exclusive with other embodiments and is independent or optional. It is clearly or implicitly understood by those of ordinary skill in the art that the embodiments described in this application can be combined with other embodiments without conflict.

[0129] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of patent protection. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the scope of protection of the present application. Therefore, the scope of protection of the present application shall be subject to the attached claims.

Claims

1. A wafer retest method, characterized in that: The method is applied to a tester in a wafer test system, wherein the wafer test system further comprises a probe station communicating with the tester, and the method comprises: Execute the test items and obtain test data of each chip under test in the wafer under test, wherein the test data includes the coordinates of the chip under test and the corresponding test results; Inquiring the coordinates of the chip under test in the stored result data record, and if the coordinates are not found, determining that the test result is the first test result of the chip under test, and storing the coordinates in the result data record; Based on the first test result, the wafer yield and the first test yield of the tested wafer are calculated, wherein the wafer yield is the ratio of the number of chips with a test result of Pass to the total number of chips in the tested wafer; the first test yield is the ratio of the number of chips with a first test result of Pass to the total number of chips; When the first test yield fails to meet the preset yield condition, a wafer retest process is triggered, and the wafer retest process includes: sending a shift instruction and a test instruction to the probe station, performing at least one retest on the target chip under test in the wafer under test, the target chip under test is the chip under test whose test result in the last test is a failure; after each retest, updating the wafer yield of the wafer under test based on the retest result of the target chip under test; when the wafer yield meets the preset retest stop condition, or the number of retests reaches the preset number of retests, sending a wafer shift instruction to the probe station to stop the wafer retest process, and the retest stop condition includes that the wafer yield is greater than or equal to a first preset threshold, or the difference between the wafer yield and the first test yield is greater than a second preset threshold, and the first preset threshold is equal to the yield threshold in the preset yield condition.

2. The method according to claim 1, characterized in that: The performing at least one retest on the target chip under test in the wafer under test, and updating the wafer yield of the wafer under test based on the retest result of the target chip under test after each retest, comprises: Retesting the target chip under test whose test result was failed in the last test and obtaining corresponding test data, wherein the target chip under test of the first retest is the chip under test whose test result was failed in the first test; querying the coordinates in the test data in the result data record, and determining, when the coordinates are found, that the test result corresponding to the coordinates is the retest result of the target chip under test; Based on the retest result of the target chip under test, the wafer yield of the wafer under test is updated.

3. The method according to claim 1, characterized in that After updating the wafer yield of the wafer under test based on the retest result of the target chip under test after each retest, the method further includes: When the difference between the wafer yield and the first-measurement yield is greater than a first alarm threshold, or less than a second alarm threshold, a corresponding alarm message is generated, and the re-measurement is stopped.

4. A wafer testing system, comprising a testing machine and a probe station communicating with the testing machine, characterized in that: The testing machine is used to retest the wafer under test based on the wafer retest method described in any one of claims 1 to 3.

5. The system according to claim 4, characterized in that When retesting a target chip under test whose test result was a failure in the last test, the test machine obtains the coordinates of the target chip under test, and sends the coordinates and a shift instruction to the probe station, so that the probe of the probe station moves to the target chip under test; The test machine sends a test instruction to the probe station, receives a loading signal sent by the probe station, and executes a test item on the target chip under test based on the loading signal.

6. The system according to claim 4, characterized in that The test machine determines whether to start automatic retesting after completing the first test of the wafer under test and receiving a wafer closure signal sent by the probe station; When the automatic retest is started, the tester automatically retests the wafer under test.

7. The system according to claim 4, characterized in that When the wafer yield meets the retest stop condition, or the number of retests reaches a preset number of retests, the test machine sends a wafer shifting instruction to the probe station, and the probe station performs wafer bonding processing on the wafer under test based on the wafer shifting instruction.

8. A testing machine, characterized in that: The testing machine comprises: An acquisition module is used to execute the test items and acquire the test data of each chip under test in the wafer under test, wherein the test data includes the coordinates of the chip under test and the corresponding test results; query the coordinates of the chip under test in the stored result data record, and if the coordinates are not found, determine that the test result is the first test result of the chip under test, and store the coordinates in the result data record; A calculation module is used to calculate the wafer yield and the first test yield of the tested wafer based on the first test result, wherein the wafer yield is the ratio of the number of chips with a test result of Pass to the total number of chips in the tested wafer; the first test yield is the ratio of the number of chips with a first test result of Pass to the total number of chips; A retest module is used to trigger a wafer retest process when the first test yield does not meet the preset yield condition, and the wafer retest process includes: sending a shift instruction and a test instruction to the probe station, performing at least one retest on the target chip under test in the tested wafer, the target chip under test is the chip under test whose test result in the last test is a failure; after each retest, updating the wafer yield of the tested wafer based on the retest result of the target chip under test; when the wafer yield meets the preset retest stop condition, or the number of retests reaches the preset number of retests, sending a wafer shift instruction to the probe station to stop the wafer retest process, and the retest stop condition includes that the wafer yield is greater than or equal to a first preset threshold, or the difference between the wafer yield and the first test yield is greater than a second preset threshold, and the first preset threshold is equal to the yield threshold in the preset yield condition.

9. A readable storage medium having a program stored thereon, characterized in that: When the program is executed by a processor, the steps of the wafer retest method according to any one of claims 1 to 3 are implemented.

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