Integrated circuit post-simulation layout generation method, device and readable storage medium

Abstract

The present application relates to a method, device and readable storage medium for generating a post-simulation layout of an integrated circuit, wherein the method for generating a post-simulation layout of an integrated circuit comprises: determining a target device in the original layout by acquiring an original layout; acquiring a winding structure of each pin of the target device in the original layout, and generating a first layout file according to the winding structure; acquiring a target area including a front and middle layer of all pins of the target device in the original layout, and generating a second layout file according to the target area; merging the first layout file and the second layout file to obtain a post-simulation layout of the target device. Through the present application, the problems of low post-simulation accuracy due to incomplete metal routing acquired during the post-simulation process and low efficiency in extracting a post-simulation parameter netlist are solved, thereby improving the post-simulation accuracy and the efficiency in extracting a post-simulation parameter netlist.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method, device and readable storage medium for generating a post-simulation layout for an integrated circuit. Background Art

[0002] With the continuous advancement of technology, the impact of parasitic effects such as parasitic capacitance on the performance of integrated circuits can no longer be ignored, and the impact of this factor must be considered especially for deep submicron integrated circuit design. Specifically, an integrated circuit contains multiple electronic components, each of which may generate parasitic capacitance, which was not considered when the circuit was designed before, and therefore will have an impact on the actual circuit. Therefore, a post-simulation test method can be used to test whether the circuit containing parasitic capacitance meets the design requirements.

[0003] "Post-simulation" means that after the layout design is completed, the circuit design of the layout is converted into a simulation circuit for simulation, and the circuit parameter netlist and parasitic parameter netlist of the simulation circuit are obtained. The parasitic parameters in the parasitic parameter netlist, such as parasitic capacitance parameters, are reverse-annotated into the extracted circuit parameter netlist for simulation, and the circuit is analyzed to ensure that the circuit meets the design requirements. In the post-simulation process, the netlist, as a file that describes the circuit structure and connection relationship, is the basis of simulation analysis.

[0004] In the related art, in addition to the transistor to be tested, the layout of the device to be tested is also surrounded by transistors or other devices in other original chips. Since the area involved in the metal routing from the pin to the pin pad is relatively large, the current method for generating the simulation layout file is mainly to directly cut out the front and middle pin area containing only the complete device to be tested from the entire chip. Therefore, after using this method to reverse-label the parameters of the transistor to be tested into the circuit parameter netlist to form a post-simulation netlist, the obtained post-simulation parameter netlist cannot fully reflect the influence of the resistance and capacitance of the routing of the transistor to be tested, resulting in poor post-simulation effect. In addition, the related art also uses a tiling method to form a flat parasitic parameter netlist. The same method is used when extracting the circuit parameter netlist, and the parameters of multiple sub-circuits are listed one by one in the code segment to form a flat circuit parameter netlist. The flat netlist has only one level, and there is no multi-level call function. Therefore, after using this method to back-annotate the parasitic capacitance parameters into the circuit parameter netlist to form a post-simulation parameter netlist, the file of the post-simulation parameter netlist is large, resulting in a long simulation time when the post-simulation parameter netlist is used for simulation, wasting resources and time.

[0005] There is currently no effective solution to the problem in the related art that in the post-simulation process, the post-simulation accuracy is low due to incomplete metal routing, and the efficiency of post-simulation parameter netlist extraction is low. Summary of the invention

[0006] In this embodiment, a method and device for generating a post-simulation layout for an integrated circuit are provided to solve the problems in the related art of low post-simulation accuracy due to incomplete metal routing obtained during the post-simulation process, as well as low efficiency in extracting post-simulation parameter netlists.

[0007] In a first aspect, a method for generating a post-simulation layout of an integrated circuit is provided in this embodiment, comprising:

[0008] Obtain the original layout and determine the target device in the original layout;

[0009] Obtaining a wiring structure of each pin of a target device in an original layout, and generating a first layout file according to the wiring structure;

[0010] Obtain a target area including the front and middle layers of all pins of the target device in the original layout, and generate a second layout file according to the target area;

[0011] The first layout file and the second layout file are merged to obtain a post-simulation layout of the target device.

[0012] In some of the embodiments, obtaining the wiring structure of each pin of the target device in the original layout includes:

[0013] Get the complete metal trace from each pin to the pad and the vias connecting the metal traces for each target device.

[0014] In some embodiments, obtaining a complete metal trace from each pin to a pad of a target device and a through hole connecting the metal traces includes:

[0015] Determine the complete metal routing from each pin to the pad and the vias connecting the metal routing based on the identification on each pin metal layer of the target device.

[0016] In some of the embodiments, obtaining a target area including a front-middle layer of all pins of a target device in an original layout includes:

[0017] Traversing the identification coordinates of each pin in the target device to determine an initial rectangle, wherein the initial rectangle includes all pins in the target device;

[0018] Expand the outer contour of the initial rectangle outward by a preset size to obtain the target area.

[0019] In some of the embodiments, the range of the initial rectangle is the minimum range that includes all pins in the target device.

[0020] In some of the embodiments, before obtaining the wiring structure of each pin of the target device in the original layout and generating the first layout file according to the wiring structure, the method further includes:

[0021] Calculate the device ratio of the target device in a preset determination area, wherein the preset determination area is an area in the original layout including all pins of the target device and a complete wiring structure from each pin to a pad;

[0022] Determine whether the device proportion value is less than a preset proportion threshold value, wherein the device proportion value is the ratio of the number of target devices to the number of all devices in a preset determination area;

[0023] If so, the wiring structure of each pin of the target device in the original layout is obtained, and a first layout file is generated according to the wiring structure.

[0024] In some of the embodiments, the post-simulation netlist is extracted and simulated according to the post-simulation layout of the target device.

[0025] In a second aspect, in this embodiment, a device for generating a post-simulation layout of an integrated circuit is provided, comprising: a determination module, a first acquisition module, a second acquisition module and a merging module, wherein:

[0026] A determination module is used to obtain the original layout and determine the target device in the original layout;

[0027] A first acquisition module is used to acquire the winding structure of each pin of the target device in the original layout, and generate a first layout file according to the winding structure;

[0028] The second acquisition module is used to acquire the target area including the front and middle layers of all pins of the target device in the original layout, and generate a second layout file according to the target area;

[0029] The merging module is used to merge the first layout file and the second layout file to obtain a post-simulation layout of the target device.

[0030] In some of the embodiments, the device further includes: a determination module, a first positioning module and a second positioning module, wherein:

[0031] A judgment module, used to calculate a device ratio of the target device in a preset judgment area, and judge whether the device ratio is less than a preset ratio threshold;

[0032] The first positioning module is used to determine the complete metal routing from each pin to the pad and the through hole connecting the metal routing according to the mark on the metal layer of each pin in the target device;

[0033] The second positioning module is used to traverse the identification coordinates of each pin in the target device to determine an initial rectangle, wherein the initial rectangle includes all pins in the target device; and expand the outer contour of the initial rectangle outward by a preset size to obtain a target area.

[0034] According to a third aspect, a computer-readable storage medium is provided in this embodiment, on which a computer program is stored. When the computer program is executed by a processor, the steps of the integrated circuit post-simulation layout generation method described in the first aspect are implemented.

[0035] Compared with the related art, the integrated circuit post-simulation layout generation method provided in the present embodiment determines the target device in the original layout by acquiring the original layout; acquires the winding structure of each pin of the target device in the original layout, and generates a first layout file according to the winding structure; acquires the target area including the front and middle layers of all pins of the target device in the original layout, and generates a second layout file according to the target area; merges the first layout file and the second layout file to obtain the post-simulation layout of the target device, thereby solving the problems of low post-simulation accuracy due to incomplete metal routing acquired during the post-simulation process and low efficiency in extracting the post-simulation parameter netlist, and improving the post-simulation accuracy and the extraction efficiency of the post-simulation parameter netlist.

[0036] Details of one or more embodiments of the present application are set forth in the following drawings and description to make other features, objects, and advantages of the present application more readily apparent. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0038] Figure 1 It is a hardware structure block diagram of a terminal of the integrated circuit post-simulation layout generation method of this embodiment.

[0039] Figure 2 4 is a flow chart of the integrated circuit post-simulation layout generation method of this embodiment.

[0040] Figure 3 This is a preferred flow chart of the integrated circuit post-simulation layout generation method of this embodiment.

[0041] Figure 4 It is a structural block diagram of the integrated circuit post-simulation layout generation device of this embodiment.

[0042] Figure 5 This is a preferred structural block diagram of the integrated circuit post-simulation layout generation device of this embodiment. DETAILED DESCRIPTION

[0043] In order to more clearly understand the purpose, technical solutions and advantages of the present application, the present application is described and illustrated below in conjunction with the accompanying drawings and embodiments.

[0044] Unless otherwise defined, the technical terms or scientific terms involved in this application shall have the general meaning understood by people with general skills in the technical field to which this application belongs. The words "one", "a", "the", "these" and the like in this application do not indicate a quantitative limitation, and they may be singular or plural. The terms "include", "comprise", "have" and any variants thereof involved in this application are intended to cover non-exclusive inclusions; for example, a process, method and system, product or device comprising a series of steps or modules (units) is not limited to the listed steps or modules (units), but may include unlisted steps or modules (units), or may include other steps or modules (units) inherent to these processes, methods, products or devices. The words "connect", "connected", "coupled" and the like involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The "multiple" involved in this application refers to two or more. "And / or" describes the association relationship of associated objects, indicating that there may be three relationships, for example, "A and / or B" may mean: A exists alone, A and B exist at the same time, and B exists alone. Generally, the character " / " indicates that the objects associated with each other are in an "or" relationship. The terms "first", "second", "third", etc. in this application are only used to distinguish similar objects and do not represent a specific ordering of the objects.

[0045] The method embodiment provided in this embodiment can be executed in a terminal, a computer or a similar computing device. For example, running on a terminal, Figure 1 1 is a hardware structure block diagram of a terminal of the integrated circuit post-simulation layout generation method of this embodiment. Figure 1 As shown, the terminal may include one or more ( Figure 1 Only one is shown in the figure) a processor 102 and a memory 104 for storing data, wherein the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA. The above terminal may also include a transmission device 106 and an input and output device 108 for communication functions. It can be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the above terminal. Figure 1 More or fewer components as shown, or with Figure 1 Different configurations shown.

[0046] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the integrated circuit post-simulation layout generation method in this embodiment. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, to implement the above method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories may be connected to the terminal via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0047] The transmission device 106 is used to receive or send data via a network. The above network includes a wireless network provided by the communication provider of the terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (Radio Frequency, referred to as RF) module, which is used to communicate with the Internet wirelessly.

[0048] In this embodiment, a method for generating a post-simulation layout of an integrated circuit is provided. Figure 2 is a flow chart of the integrated circuit post-simulation layout generation method of this embodiment. Figure 2 As shown, the process includes the following steps:

[0049] Step S201, obtaining an original layout and determining a target device in the original layout.

[0050] Specifically, in the field of electronic design automation (EDA), the original layout of the integrated circuit (IC) design is extracted. The layout is a detailed drawing that describes the physical layout and connection method of each component in the integrated circuit (IC). The target device refers to a specific electronic component or module in the layout. The acquisition of the original layout can be exported from the design database through EDA software in the form of a graphic or data file. The target device is determined from the original layout. The target device is the specified device that needs to be generated by the post-simulation layout of the integrated circuit, such as transistors, capacitors, resistors, triodes, etc.

[0051] Step S202, obtaining the wiring structure of each pin of the target device in the original layout, and generating a first layout file according to the wiring structure.

[0052] Specifically, the pin winding structure refers to the layout and routing of device pins in an integrated circuit. This structure can optimize electrical performance, such as reducing resistance, capacitance, and electromagnetic interference, and obtaining the winding structure of each pin of the target device determined in the original layout, that is, obtaining the complete metal routing of each pin of the target device, and saving all the obtained winding structures as the first layout file.

[0053] Step S203, obtaining a target area including the front and middle layers of all pins of the target device in the original layout, and generating a second layout file according to the target area.

[0054] Specifically, in integrated circuit layout design, the layout file usually contains multiple layers, each layer represents a different manufacturing process step. The front-middle end layers usually refer to the bottom to middle layers in the chip, including electronic components, contact holes and other structures. Since the front-middle end range where the target device is located has a great influence on the accuracy of the results of the post-simulation layout of the integrated circuit, and the size of the front-middle end layer is the main factor affecting the simulation time, the area containing all the pins of the target device is identified in the original layout to generate a second layout file, wherein the EDA tool can be used to generate the second layout file, and this application does not make specific restrictions on this.

[0055] Step S204: merge the first layout file and the second layout file to obtain a post-simulation layout of the target device.

[0056] The first layout file includes the winding structure of each pin of the target device, and the second layout file includes the front and middle layer information of the target device. The first layout file and the second layout file are merged to obtain a complete post-simulation layout of the target device. The merging tool can be implemented using an EDA tool, and this application does not make any specific limitations on this.

[0057] Through the above steps S201 to S204, the original layout is obtained, and the target device in the original layout is determined; the winding structure of each pin of the target device in the original layout is obtained, and a first layout file is generated according to the winding structure; the target area including the front and middle layers of all pins of the target device in the original layout is obtained, and a second layout file is generated according to the target area; the first layout file and the second layout file are merged to obtain the post-simulation layout of the target device. Compared with the current method of directly cutting out only the complete front and middle pin area of ​​the device to be tested from the entire chip, resulting in incomplete metal routing, the present application generates a first layout file by first extracting the winding structure of all pins in the target device; then cutting out the information of the front and middle layers containing all pins of the target device as the second layout file; and obtaining the post-simulation layout of the target device by merging the first layout file and the second layout file into one layout file. Among them, the complete metal routing is extracted through the first layout file, which solves the problem of low post-simulation accuracy due to incomplete metal routing in the post-simulation process, improves the post-simulation accuracy, and when intercepting the front and middle layer range where all pins are located, the interception range is narrowed, which reduces the acquisition time and improves the extraction efficiency of the post-simulation parameter netlist.

[0058] In this embodiment, the target device refers to a transistor, but in some other embodiments, the target device may also be an electronic component such as a resistor, a capacitor or a triode, and this application does not make any specific limitation.

[0059] Specifically, in integrated circuit design, the target device is the basic element that constitutes the circuit function, which can be transistors, resistors, capacitors and triodes, etc., each of which has unique electrical characteristics and functions in the circuit. Transistors are semiconductor devices in integrated circuits, used for amplification, switching, signal modulation, etc. In digital circuits, transistors are usually used as building blocks of logic gates, such as N-type and P-type transistors in CMOS technology. In analog circuits, transistors are used to build amplifiers, oscillators, etc. Resistors are used to limit the flow of current and provide a stable voltage drop. In integrated circuits, resistors can be diffused resistors formed by diffusion layers or thin-film resistors formed by polysilicon or metal layers. Capacitors are used to store charge and energy, as well as filter and couple signals in AC circuits. Capacitors in integrated circuits can be metal-oxide-semiconductor (MOS) capacitors, air gap capacitors or interconnect capacitors. A triode is a current-controlled device consisting of an emitter, a base and a collector, used to amplify or switch current. In integrated circuits, triodes are often used for analog signal processing, such as current mirrors, differential amplifiers, etc. In this embodiment, the target device may be any one or more of the above-mentioned devices, which is not specifically limited in this embodiment. This embodiment uses a transistor as an example for specific description.

[0060] In another embodiment, the wiring structure of each pin of the target device in the original layout is obtained, including: obtaining the complete metal routing from each pin of the target device to the pad and the through-holes connecting the metal routing, and determining the complete metal routing from each pin to the pad and the through-holes connecting the metal routing according to the markings on the metal layer of each pin of the target device.

[0061] Specifically, the winding structure of each pin of the target device in the original artwork includes the complete metal routing from each pin to the pad and the corresponding through-holes connecting the metal routing. Each pin has its own specific identification in the layout, which includes the name, number or functional description of the pin. The integrated circuit layout contains multiple metal layers. According to the identification information of each pin on the metal layer, the exact position of each pin on the metal layer and the complete metal routing from each pin to the pad are determined. Vias are vertical conductive structures connecting different metal layers. They allow signals or power to be transmitted between different levels. According to the identification information of each pin on different metal layers, the position of the through-holes connecting the metal routing is determined. According to the determined positions of the completed metal routing and the through-holes connecting the metal routing, the complete winding structure of each pin of the target device is obtained.

[0062] In one of the embodiments, a target area including the front and middle layers of all pins of the target device in the original layout is obtained, including: traversing the identification coordinates of each pin in the target device to determine an initial rectangle, wherein the range of the initial rectangle includes all pins in the target device, and the range of the initial rectangle is the minimum range that includes all pins in the target device; and expanding each side of the outer contour of the initial rectangle outward by a preset size to obtain the target area.

[0063] Specifically, the target device, such as a transistor, is first traversed in the original layout to find the identification coordinate information of all the pins of the transistor in the original layout. Each pin has its unique identification coordinate in the layout. These coordinates define the exact position of the pin in the layout and record its coordinate position in the layout. According to the coordinate positions of all pins, that is, the minimum and maximum values ​​of the pin coordinates, the coordinates of the lower left corner and the upper right corner of the initial rectangle are calculated, wherein the initial rectangle is the minimum range containing all pins. It has been verified by experiments that the main influence on transistor simulation is the range of 3 microns to 5 microns outward from the area containing all pins. Therefore, after obtaining the initial matrix, the outer contour of the initial matrix is ​​extended outward by a preset size of 3 microns to 5 microns to obtain the target area including the front and middle layers of all pins of the target device. The coordinate position of each pin is determined by the identification information of each pin, and the initial matrix is ​​calculated according to the coordinate position of each pin. Then, the initial matrix is ​​expanded according to the experimental data to obtain the target area. On the basis of ensuring that all pins are obtained, the scope of the extracted layout is narrowed, the time for obtaining the post-simulation layout is reduced, and the extraction efficiency of the post-simulation parameter netlist is improved.

[0064] In some of the embodiments, before obtaining the winding structure of each pin of the target device in the original layout and generating the first layout file based on the winding structure, it also includes: calculating the device proportion value of the target device in a preset determination area, wherein the preset determination area is an area in the original layout including all pins of the target device and the complete winding structure from each pin to the pad; judging whether the device proportion value is less than a preset proportion threshold, wherein the device proportion value is the ratio of the number of target devices to the number of all devices in the preset determination area; if so, obtaining the winding structure of each pin of the target device in the original layout, and generating the first layout file based on the winding structure.

[0065] Specifically, in the test chip layout built into the actual product chip, in addition to the transistor to be tested selected as the target device, the transistor to be tested is surrounded by transistors or other devices in other original product chips. Therefore, using the existing technical methods, the front and middle pin area that needs to be intercepted and contains the target device is very large. In other types of test chip layouts, there are also cases where there are no other devices around the target device. Therefore, before using the integrated circuit post-simulation layout generation method of this application, the proportion of the target device in the preset judgment area is calculated.

[0066] First, a preset judgment area is determined, which is an area including all pins of the target device and the complete winding structure from each pin to the pad. This area is used as a reference area for evaluating the proportion of the target device. Secondly, within the preset judgment area, the number of target devices and the number of all devices are counted, and all devices include the target device and other devices around the target device. Finally, the ratio of the number of target devices to the number of all devices is calculated. A ratio threshold is set as a standard for judging whether it meets the method for generating the post-simulation layout of the integrated circuit of the present application. In this embodiment, the ratio threshold is set to 50%. When the ratio value is greater than 50%, it means that there are few or no irrelevant devices in the area. Therefore, it is not necessary to adopt the aforementioned method of the present application, and all are directly intercepted. When the ratio value is less than 50%, according to the aforementioned method of the present application, the winding structure of each pin of the target device is first obtained, and then the first layout file is generated according to the winding structure, and then the target area including the front and middle layers of each pin is intercepted to generate the second layout file, and the first layout file and the second layout file are merged to obtain the post-simulation layout.

[0067] In another embodiment, the post-simulation netlist is extracted and simulated according to the post-simulation layout of the target device.

[0068] Specifically, use the layout extraction tool to extract geometric data and hierarchical information from the generated post-simulation layout of the target device, including the size, shape and position of each layer. Convert the extracted layout data into circuit connection information to generate a post-simulation netlist. The netlist contains the electrical connections of all devices in the layout. Verify the generated post-simulation netlist to ensure that it accurately reflects the electrical connections of the layout without omissions or errors. Set simulation parameters and conditions according to the performance requirements of the circuit design, including simulation type (DC, AC, transient, etc.), temperature range, power supply voltage, etc. Select appropriate simulation tools and models to configure the simulation environment. The models include process models, device models, and simulation engines. Run the simulation to analyze the performance of the circuit after the layout is implemented, including but not limited to gain, speed, power consumption, noise, signal integrity, and power integrity. Compare and analyze the post-simulation netlist with the schematic netlist to check whether there are any differences and analyze the potential impact of these differences on circuit performance. According to the results of simulation analysis and problem diagnosis, the layout is optimized as necessary to improve circuit performance. Through this process, it can be ensured that the performance of the integrated circuit design at the layout level meets expectations, providing a guarantee for the successful manufacturing and performance realization of the product.

[0069] Figure 3 is a preferred flow chart of the integrated circuit post-simulation layout generation method of this embodiment, such as Figure 3 As shown, the integrated circuit post-simulation layout generation method includes the following steps:

[0070] Step S301, obtaining an original layout and determining a target device in the original layout;

[0071] Step S302, calculating the device ratio of the target device in the preset determination area;

[0072] Step S303, when the device proportion value is less than a preset proportion threshold, determine the complete metal routing from each pin to the pad and the through hole connecting the metal routing according to the mark on the metal layer of each pin of the target device, and obtain the winding structure of each pin of the target device;

[0073] Step S304, generating a first layout file according to the winding structure;

[0074] Step S305, traversing the identification coordinates of each pin in the target device to determine an initial rectangle;

[0075] Step S306, expanding the outer contour of the initial rectangle outward by a preset size to obtain a target area;

[0076] Step S307, generating a second layout file according to the target area;

[0077] Step S308, merging the first layout file and the second layout file to obtain a post-simulation layout of the target device;

[0078] Step S309, extracting and simulating the post-simulation netlist according to the post-simulation layout of the target device.

[0079] Through the above steps S301 to S309, the winding structure of each pin of the target device is obtained by first extracting the metal routing used from each pin to the pin pad of the target device and the necessary through holes for connecting the routing, and the winding structure is generated as a first layout file; then the target area of ​​the front and middle sections containing all pins is intercepted to generate a second layout file; the first layout file and the second layout file are merged to obtain the post-simulation layout of the target device, and finally the post-simulation netlist is extracted and simulated according to the post-simulation layout. Since the complete metal routing is extracted through the first layout, the accuracy of the post-simulation is improved. When intercepting the target area of ​​the front and middle sections where the pins are located, the scope of interception is reduced, the time for obtaining the second layout file is reduced, and the extraction efficiency of the post-simulation parameter netlist is improved.

[0080] In this embodiment, a post-simulation layout generation device for integrated circuits is also provided, which is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. The terms "module", "unit", "subunit", etc. used below can implement a combination of software and / or hardware for a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0081] Figure 4 is a structural block diagram of the integrated circuit post-simulation layout generation device of this embodiment, such as Figure 4 As shown, the device 40 includes: a determination module 41, a first acquisition module 42, a second acquisition module 43 and a merging module 44, wherein:

[0082] A determination module 41 is used to obtain an original layout and determine a target device in the original layout;

[0083] A first acquisition module 42 is used to acquire the wiring structure of each pin of the target device in the original layout, and generate a first layout file according to the wiring structure;

[0084] The second acquisition module 43 is used to acquire a target area including the front and middle layers of all pins of the target device in the original layout, and generate a second layout file according to the target area;

[0085] The merging module 44 is used to merge the first layout file and the second layout file to obtain a post-simulation layout of the target device.

[0086] Figure 5is a preferred structural block diagram of the integrated circuit post-simulation layout generation device of this embodiment, such as Figure 5 As shown, the device 50 includes Figure 4 All modules shown in the figure further include: a judgment module 51, a first positioning module 52 and a second positioning module 53, wherein:

[0087] The judgment module 51 is used to calculate the device proportion of the target device in the preset judgment area, and judge whether the device proportion is less than a preset proportion threshold;

[0088] A first positioning module 52, used to determine the complete metal routing from each pin to the pad and the through hole connecting the metal routing according to the mark on the metal layer of each pin in the target device;

[0089] The second positioning module 53 is used to traverse the identification coordinates of each pin in the target device to determine an initial rectangle, wherein the initial rectangle includes all the pins in the target device; and expand the outer contour of the initial rectangle outward by a preset size to obtain a target area.

[0090] It should be noted that the above modules can be functional modules or program modules, and can be implemented by software or hardware. For modules implemented by hardware, the above modules can be located in the same processor; or the above modules can be located in different processors in any combination.

[0091] In this embodiment, an electronic device is further provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0092] Optionally, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0093] Optionally, in this embodiment, the processor may be configured to perform the following steps through a computer program:

[0094] S1, obtaining the original layout and determining the target device in the original layout;

[0095] S2, obtaining the wiring structure of each pin of the target device in the original layout, and generating a first layout file according to the wiring structure;

[0096] S3, obtaining a target area including the front and middle layers of all pins of the target device in the original layout, and generating a second layout file according to the target area;

[0097] S4, merging the first layout file and the second layout file to obtain a post-simulation layout of the target device.

[0098] It should be noted that the specific examples in this embodiment can refer to the examples described in the above embodiments and optional implementation modes, and will not be repeated in this embodiment.

[0099] In addition, in combination with the integrated circuit post-simulation layout generation method provided in the above embodiments, a storage medium can also be provided in this embodiment to implement the method. The storage medium stores a computer program; when the computer program is executed by a processor, any one of the integrated circuit post-simulation layout generation methods in the above embodiments is implemented.

[0100] It should be understood that the specific embodiments described herein are only used to explain the application, rather than to limit it. Based on the embodiments provided in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the protection scope of this application.

[0101] Obviously, the drawings are only some examples or embodiments of the present application. For ordinary technicians in the field, the present application can also be applied to other similar situations based on these drawings without creative work. In addition, it is understandable that although the work done in this development process may be complicated and lengthy, for ordinary technicians in the field, certain changes in design, manufacturing or production based on the technical content disclosed in this application are only conventional technical means and should not be regarded as insufficient content disclosed in this application.

[0102] The term "embodiment" in this application refers to a specific feature, structure or characteristic described in conjunction with the embodiment that can be included in at least one embodiment of the present application. The appearance of this phrase in various locations in the specification does not necessarily mean the same embodiment, nor does it mean that it is mutually exclusive with other embodiments and is independent or optional. It is clearly or implicitly understood by those of ordinary skill in the art that the embodiments described in this application can be combined with other embodiments without conflict.

[0103] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited to this.

[0104] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of patent protection. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the scope of protection of the present application. Therefore, the scope of protection of the present application shall be subject to the attached claims.

Claims

1. A method for generating a post-simulation layout of an integrated circuit, characterized in that: include: Acquire an original layout and determine a target device in the original layout; wherein the target device is a designated device for which a post-simulation layout of an integrated circuit needs to be generated; Acquire the wiring structure of each pin of the target device in the original layout, and generate a first layout file according to the wiring structure; Acquire a target area including the front and middle layers of all pins of the target device in the original layout, and generate a second layout file according to the target area; Merging the first layout file and the second layout file to obtain a post-simulation layout of the target device; The step of obtaining the target area including the front and middle layers of all pins of the target device in the original layout includes: Traversing the identification coordinates of each pin in the target device to determine an initial rectangle, wherein the initial rectangle includes all the pins in the target device; Each side of the outer contour of the initial rectangle is expanded outward by a preset size to obtain the target area.

2. The method for generating a post-simulation layout of an integrated circuit according to claim 1, characterized in that: The obtaining of the wiring structure of each pin of the target device in the original layout includes: A complete metal trace from each pin of the target device to a pad and a through hole connecting the metal trace are obtained.

3. The method for generating a post-simulation layout of an integrated circuit according to claim 2, characterized in that: The step of obtaining a complete metal trace from each pin of the target device to a pad and a through hole connecting the metal trace comprises: A complete metal routing from each pin to a pad and a through hole connecting the metal routing are determined according to the identification on the metal layer of each pin of the target device.

4. The method for generating a post-simulation layout of an integrated circuit according to claim 1, characterized in that: The range of the initial rectangle is the minimum range that includes all pins in the target device.

5. The method for generating a post-simulation layout of an integrated circuit according to claim 1, characterized in that: Before obtaining the wiring structure of each pin of the target device in the original layout and generating the first layout file according to the wiring structure, the method further includes: Calculating the device ratio of the target device in a preset determination area, wherein the preset determination area is an area in the original layout including all pins of the target device and a complete wiring structure from each pin to a pad; Determine whether the device proportion value is less than a preset proportion threshold value, wherein the device proportion value is the ratio of the number of target devices to the number of all devices in the preset determination area; If so, the wiring structure of each pin of the target device in the original layout is obtained, and a first layout file is generated according to the wiring structure.

6. The method for generating a post-simulation layout of an integrated circuit according to claim 1, characterized in that: The method further comprises: According to the post-simulation layout of the target device, the post-simulation netlist is extracted and simulated.

7. An integrated circuit post-simulation layout generation device, characterized in that: include: A determination module, a first acquisition module, a second acquisition module and a merging module, wherein: The determination module is used to obtain the original layout and determine the target device in the original layout; wherein the target device is a designated device that needs to generate a post-simulation layout of the integrated circuit; The first acquisition module is used to acquire the winding structure of each pin of the target device in the original layout, and generate a first layout file according to the winding structure; The second acquisition module is used to acquire the target area including the front and middle layers of all pins of the target device in the original layout, and generate a second layout file according to the target area; wherein acquiring the target area including the front and middle layers of all pins of the target device in the original layout includes: Traversing the identification coordinates of each pin in the target device to determine an initial rectangle, wherein the initial rectangle includes all the pins in the target device; Expand each side of the outer contour of the initial rectangle outward by a preset size to obtain the target area; The merging module is used to merge the first layout file and the second layout file to obtain a post-simulation layout of the target device.

8. The integrated circuit post-simulation layout generation device according to claim 7, characterized in that: The device further includes: a judgment module, a first positioning module and a second positioning module, wherein: The judgment module is used to calculate the device proportion value of the target device in the preset judgment area, and judge whether the device proportion value is less than a preset proportion threshold value; The first positioning module is used to determine the complete metal routing from each pin to the pad and the through hole connecting the metal routing according to the mark on the metal layer of each pin in the target device; The second positioning module is used to traverse the identification coordinates of each pin in the target device to determine an initial rectangle, wherein the initial rectangle includes all the pins in the target device; and expand each side of the outer contour of the initial rectangle outward by a preset size to obtain the target area.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method for generating a post-simulation layout of an integrated circuit according to any one of claims 1 to 6 are implemented.

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