Lateral double diffused field effect transistor, manufacturing method, chip and circuit

By adding carrier flow channels and multi-layer oxide design in lateral double diffusion field effect transistors, the problems of small operating current and slow driving capacity are solved, and higher output power and lower production costs are achieved.

CN118610265BActive Publication Date: 2024-12-13BEIJING SMARTCHIP MICROELECTRONICS TECHNOLOGY CO LTD
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Patent Information

Application Number
CN202411082426.6
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2024-08-08
Publication Date
2024-12-13
Estimated Expiration
2044-08-08

AI Technical Summary

Technical Problem

The existing lateral double diffusion field effect transistors have small operating currents and slow driving capabilities, resulting in larger device area and high production costs under the same operating current requirements.

Method used

By adding carrier flow paths in the transverse double diffusion field effect transistor, using a step-like substrate structure and multi-layer oxide layer design, the second gate and second field plate are added, and the carrier flow path is increased, thereby improving the Operating current and driving capability.

Benefits of technology

Under the same operating current requirements, the transistor area is reduced, production costs are reduced, and the transistor output power and switching speed are increased, thereby enhancing signal transmission capabilities.

✦ Generated by Eureka AI based on patent content.

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Abstract

The present invention provides a lateral double diffused field effect transistor, a manufacturing method, a chip and a circuit, and relates to the field of semiconductors. The transistor includes: a substrate, which includes, from bottom to top, a first substrate layer, a first oxide layer, a heavily doped silicon layer, and a second substrate layer and a second oxide layer protruding from the heavily doped silicon layer; the second oxide layer includes a gate oxide layer and a field plate oxide layer, and the thickness of the field plate oxide layer is greater than the thickness of the gate oxide layer; the heavily doped polysilicon layer and the third oxide layer are formed on the heavily doped silicon layer not covered by the second oxide layer and the second substrate layer; the heavily doped polysilicon layer, the third oxide layer, the second oxide layer and the heavily doped polysilicon layer formed at the bottom of the body region and part of the drift region, and the heavily doped silicon layer at the bottom of the body region and part of the drift region serve as the second gate, and the remaining heavily doped silicon layer and the second oxide layer serve as the second field plate. The present invention can increase the carrier flow channel and increase the working current of the transistor.
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Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a lateral double diffused field effect transistor, a lateral double diffused field effect transistor, a chip and a circuit. Background Art

[0002] Lateral Double-Diffused MOSFET (LDMOS) is a lateral power device with electrodes located on the device surface. It is easy to achieve monolithic integration with low-voltage signal circuits and other devices through internal connections. It also has the advantages of high voltage resistance, high gain, good linearity, high efficiency, and good broadband matching performance. It has been widely used in power integrated circuits, especially low-power and high-frequency circuits.

[0003] In the prior art, the lateral double diffused field effect transistor has a relatively small operating current and a slow driving capability. Under the requirement of the same operating current, a larger device area is required, and the production cost is high. Summary of the invention

[0004] Aiming at the technical problems in the prior art that the lateral double diffused field effect transistor has a small working current, slow driving capability, requires a larger device area under the same working current requirement, and has a high production cost, the present invention provides a lateral double diffused field effect transistor, a method for manufacturing the lateral double diffused field effect transistor, a chip and a circuit. The lateral double diffused field effect transistor can increase the carrier flow channel, increase the working current of the lateral double diffused field effect transistor, improve the driving capability, thereby better driving the load, improve the output power of the transistor, thereby enhancing the signal transmission capability, improving the switching speed of the transistor, reducing the breaking loss, and can reduce the transistor area and reduce the production cost under the same working current requirement.

[0005] To achieve the above-mentioned purpose, the first aspect of the present invention provides a lateral double diffused field effect transistor, comprising: a body region, a drift region, a source, a drain, a first gate and a first field plate, the lateral double diffused field effect transistor also comprising: a substrate, the substrate comprising, from bottom to top, a first substrate layer, a first oxide layer, a heavily doped silicon layer, a second oxide layer and a second substrate layer, the second substrate layer and the second oxide layer protruding from the upper surface of the heavily doped silicon layer in a stepped manner; the body region, the drift region, the source, the drain, the first gate and the first field plate are formed on the second substrate layer; the first substrate layer and the body region have a first conductivity type, the heavily doped silicon layer and the drift region have a second conductivity type, and the ion doping types of the first conductivity type and the second conductivity type are different; the second oxide layer comprises: a gate oxide layer and a field plate oxide layer, the gate oxide layer extends from the bottom of the body region to the bottom of a portion of the drift region, the field plate oxide layer is formed at the bottom of a portion of the drift region, and the thickness of the field plate oxide layer is greater than the thickness of the gate oxide layer;

[0006] A heavily doped polysilicon layer and a third oxide layer are formed on an upper surface of the heavily doped silicon layer that is not covered by the second oxide layer and the second substrate layer, the third oxide layer is located between the heavily doped polysilicon layer, the second substrate layer protruding from the heavily doped silicon layer, and the second oxide layer, and the third oxide layer is in close contact with a body region formed on the second substrate layer; the heavily doped polysilicon layer has a second conductivity type;

[0007] The heavily doped polysilicon layer, the third oxide layer, the second oxide layer formed at the bottom of the body region and part of the drift region, and the heavily doped silicon layer formed at the bottom of the heavily doped polysilicon layer, the bottom of the body region and part of the drift region together serve as a second gate, and the remaining heavily doped silicon layer and the remaining second oxide layer together serve as a second field plate.

[0008] Further, the thickness of the first field plate oxide layer is greater than the thickness of the field plate oxide layer; wherein the first field plate oxide layer is the oxide layer of the first field plate.

[0009] Furthermore, the heavily doped silicon layer is made of polycrystalline silicon.

[0010] Furthermore, the heavily doped silicon layer is made of single crystal silicon.

[0011] Furthermore, the heavily doped silicon layer, the second oxide layer and the second substrate layer are provided by an SOI substrate.

[0012] Furthermore, the lateral double diffused field effect transistor further includes: metal electrodes respectively formed on the source, the drain, the first gate and the heavily doped silicon layer; and an oxide isolation layer formed between two adjacent metal electrodes.

[0013] A second aspect of the present invention provides a method for manufacturing a lateral double diffused field effect transistor, the method comprising: forming a substrate; wherein the substrate comprises, from bottom to top, a first substrate layer, a first oxide layer, a heavily doped silicon layer, a second oxide layer, and a second substrate layer, the second substrate layer and the second oxide layer protruding from the upper surface of the heavily doped silicon layer in a stepped manner; the first substrate layer has a first conductivity type, the heavily doped silicon layer has a second conductivity type, and the first conductivity type and the second conductivity type have different ion doping types; the second oxide layer comprises: a gate oxide layer and a field plate oxide layer, the gate oxide layer extends from the bottom of the body region to the bottom of a portion of the drift region, the field plate oxide layer is formed at the bottom of the portion of the drift region, and the thickness of the field plate oxide layer is greater than the thickness of the gate oxide layer;

[0014] forming a heavily doped polysilicon layer and a third oxide layer on the upper surface of the heavily doped silicon layer not covered by the second oxide layer and the second substrate layer, wherein the third oxide layer is located between the heavily doped polysilicon layer and the second substrate layer protruding from the heavily doped silicon layer and the second oxide layer, and the third oxide layer is in close contact with a body region to be formed on the second substrate layer; the heavily doped polysilicon layer has a second conductivity type;

[0015] A body region, a drift region, a source, a drain, a first gate and a first field plate are formed on the second substrate layer; the body region has a first conductivity type, and the drift region has a second conductivity type; wherein the heavily doped polysilicon layer, the third oxide layer, the second oxide layer formed at the bottom of the body region and part of the drift region, and the heavily doped silicon layer formed at the heavily doped polysilicon layer, the bottom of the body region and part of the drift region together serve as a second gate, and the remaining heavily doped silicon layer and the remaining second oxide layer together serve as a second field plate.

[0016] Furthermore, the heavily doped silicon layer is made of polycrystalline silicon.

[0017] Furthermore, the heavily doped silicon layer is made of single crystal silicon.

[0018] Furthermore, the formation of the substrate includes: providing an SOI substrate, the SOI substrate including, from bottom to top, the first substrate layer, the first oxide layer and the heavily doped silicon layer; forming a pasting oxide layer on the surface of the heavily doped silicon layer; providing a second substrate layer, and forming the second oxide layer on the second substrate layer; using the pasting oxide layer to bond the second oxide layer to the heavily doped silicon layer; using an etching process to remove part of the second substrate layer and part of the second oxide layer to form the substrate.

[0019] Furthermore, the second oxide layer includes: a gate oxide layer and a field plate oxide layer, the gate oxide layer extends from the bottom of the body region to the bottom of a portion of the drift region, the field plate oxide layer is formed at the bottom of a portion of the drift region, and the thickness of the field plate oxide layer is greater than the thickness of the gate oxide layer.

[0020] Furthermore, the forming of the second oxide layer on the second substrate layer includes: forming a sacrificial oxide layer on the second substrate layer; removing part of the sacrificial oxide layer by an etching process to form an etching window; removing part of the second substrate layer through the etching window to form a stepped second substrate layer; forming a thermal oxide layer on the surface of the sacrificial oxide layer and the surface of the second substrate layer not covered by the sacrificial oxide layer by a thermal oxidation process, using the remaining sacrificial oxide layer and the thermal oxide layer thereon as the gate oxide layer, and using the thermal oxide layer on the exposed second substrate layer as the field plate oxide layer.

[0021] Further, the body region, the drift region, the third oxide layer, the heavily doped polysilicon layer, the first gate and the first field plate are formed in the following manner: before the second substrate layer and the second oxide layer are removed by an etching process to form the substrate, the body region, the drift region and the first field plate oxide layer are formed on the second substrate layer; wherein the first field plate oxide layer is the oxide layer of the first field plate; after the second substrate layer and the second oxide layer are removed by an etching process to form the substrate, the first gate oxide layer is formed, and the first field plate oxide layer is formed between the demarcated heavily doped polysilicon layer and the second substrate layer and the first field plate oxide layer protruding from the heavily doped silicon layer. The third oxide layer is formed between the second oxide layer; wherein the first gate oxide layer is the oxide layer of the first gate; a polysilicon layer is formed on the surface of the exposed heavily doped silicon layer and the second substrate layer; a portion of the polysilicon is removed by an etching process, and the polysilicon layer on the exposed heavily doped silicon layer, the polysilicon layer on the first gate oxide layer and the polysilicon layer on a portion of the first field plate oxide layer are retained, the polysilicon layer on the exposed heavily doped silicon layer serves as the heavily doped polysilicon layer, the first gate oxide layer and the polysilicon layer thereon serve as the first gate, and the first field plate oxide layer and the polysilicon layer on a portion of the first field plate oxide layer serve as the first field plate.

[0022] Furthermore, the method also includes: forming an oxidizing dielectric layer on the surface of the substrate; forming contact holes in the oxidizing dielectric layer by an etching process, wherein the contact holes are respectively in contact with the source, the drain, the first gate and the heavily doped silicon layer; forming metal electrodes in the contact holes by a deposition process, and the oxidizing dielectric layer between two adjacent metal electrodes serves as the oxidizing isolation layer.

[0023] A third aspect of the present invention provides a chip, which includes the lateral double diffused field effect transistor described above.

[0024] A fourth aspect of the present invention provides a circuit comprising the lateral double diffused field effect transistor described above.

[0025] Through the technical solution provided by the present invention, the present invention has at least the following technical effects:

[0026] The lateral double diffused field effect transistor of the present invention comprises a substrate, which comprises, from bottom to top, a first substrate layer, a first oxide layer, a heavily doped silicon layer, a second oxide layer and a second substrate layer, wherein the second substrate layer and the second oxide layer protrude from the upper surface of the heavily doped silicon layer in a stepped manner; a body region, a drift region, a source electrode, a drain electrode, a first gate electrode and a first field plate are formed on the second substrate layer; the first substrate layer and the body region have a first conductivity type, and the heavily doped silicon layer and the drift region have a second conductivity type; the second oxide layer comprises a gate oxide layer and a field plate oxide layer, wherein the gate oxide layer extends from the bottom of the body region to the bottom of a portion of the drift region, the field plate oxide layer is formed at the bottom of a portion of the drift region, and the thickness of the field plate oxide layer is greater than the thickness of the gate oxide layer. A heavily doped polysilicon layer and a third oxide layer are formed on the upper surface of the heavily doped silicon layer not covered by the second oxide layer and the second substrate layer, wherein the third oxide layer is located between the heavily doped polysilicon layer and the second substrate layer and the second oxide layer protruding from the heavily doped silicon layer, and the third oxide layer is in close contact with the body region formed on the second substrate layer, and the heavily doped polysilicon layer has the second conductivity type. The heavily doped polysilicon layer, the third oxide layer, the second oxide layer formed at the bottom of the body region and part of the drift region, and the heavily doped silicon layer formed at the heavily doped polysilicon layer, the bottom of the body region, and part of the drift region are used together as the second gate, and the remaining heavily doped silicon layer and the remaining second oxide layer are used together as the second field plate. The present invention adds a second gate and a second field plate on the basis of the first field plate and the first gate, so that the carriers can not only reach the drain from the bottom of the first gate and the first field plate, but also reach the bottom of the drift region along the third oxide layer and the second oxide layer at the bottom of the body region, and then reach the drain from the bottom of the drift region, thereby increasing the flow channel of the carriers. Therefore, through the lateral double diffused field effect transistor provided by the present invention, the carrier flow channel can be increased, the operating current of the lateral double diffused field effect transistor can be increased, the driving capability can be improved, so as to better drive the load, improve the output power of the transistor, thereby enhancing the signal transmission capability, improving the switching speed of the transistor, reducing the breaking loss, and under the same operating current requirement, the transistor area can be reduced and the production cost can be reduced.

[0027] Other features and advantages of the present invention will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings are used to provide a further understanding of the embodiments of the present invention and constitute a part of the specification. Together with the following specific implementations, they are used to explain the embodiments of the present invention, but do not constitute a limitation on the embodiments of the present invention. In the accompanying drawings:

[0029] Figure 1 A schematic structural diagram of a first substrate layer, a first oxide layer and a heavily doped silicon layer formed in a method for manufacturing a lateral double diffused field effect transistor provided in an embodiment of the present invention;

[0030] Figure 2 A schematic diagram of the structure of a second substrate layer being formed in the method for manufacturing a lateral double diffused field effect transistor provided by an embodiment of the present invention;

[0031] Figure 3 A schematic diagram of the structure of the second substrate layer after etching formed in an embodiment of the method for manufacturing a lateral double diffused field effect transistor provided in an embodiment of the present invention;

[0032] Figure 4 A schematic structural diagram of a second substrate layer and a second oxide layer formed in an implementation of a method for manufacturing a lateral double diffused field effect transistor provided in an embodiment of the present invention;

[0033] Figure 5 A schematic structural diagram of a substrate formed in an implementation of a method for manufacturing a lateral double diffused field effect transistor provided in an embodiment of the present invention;

[0034] Figure 6 A schematic structural diagram of a body region and a drift region formed in an implementation of a method for manufacturing a lateral double diffused field effect transistor provided in an embodiment of the present invention;

[0035] Figure 7 A schematic structural diagram of a first field plate oxide layer formed in an implementation of a method for manufacturing a lateral double diffused field effect transistor provided in an embodiment of the present invention;

[0036] Figure 8 A schematic structural diagram of a second substrate layer and a second oxide layer protruding from a heavily doped silicon layer formed in an implementation of a method for manufacturing a lateral double diffused field effect transistor provided in an embodiment of the present invention;

[0037] Fig. 9 A schematic structural diagram of a third oxide layer formed in an implementation of a method for manufacturing a lateral double diffused field effect transistor provided in an embodiment of the present invention;

[0038] Fig.10 A schematic structural diagram of a heavily doped polysilicon layer, a first gate and a first field plate formed in an implementation of a method for manufacturing a lateral double diffused field effect transistor provided in an embodiment of the present invention;

[0039] Fig.11A schematic diagram of the structure of a source and a drain formed in an implementation of a method for manufacturing a lateral double diffused field effect transistor provided in an embodiment of the present invention;

[0040] Fig.12 A schematic structural diagram of a lateral double diffused field effect transistor formed in an implementation of a method for manufacturing a lateral double diffused field effect transistor provided in an embodiment of the present invention;

[0041] Fig.13 The present invention provides a flowchart of a method for manufacturing a lateral double diffused field effect transistor according to an embodiment of the present invention.

[0042] Description of Reference Numerals

[0043] 1-first substrate layer; 2-first oxide layer; 3-heavily doped silicon layer; 4-second substrate layer; 5-second oxide layer; 6-gate oxide layer; 7-field plate oxide layer; 8-body region; 9-drift region; 10-first gate oxide layer; 11-first field plate oxide layer; 12-third oxide layer; 13-heavily doped polysilicon layer; 14-first gate; 15-first field plate; 16-source; 17-drain; 18-oxidation isolation layer; 19-metal electrode. DETAILED DESCRIPTION

[0044] The specific implementation of the embodiment of the present invention is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described here is only used to illustrate and explain the embodiment of the present invention, and is not used to limit the embodiment of the present invention.

[0045] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0046] In the present invention, unless otherwise specified, directional words such as "up, down, top, bottom" are usually used with reference to the directions shown in the drawings or are used to describe the relative positional relationships of components in the vertical, perpendicular or gravity direction.

[0047] The present invention will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

[0048] Please refer to Fig.12In a first aspect, an embodiment of the present invention provides a lateral double diffused field effect transistor, the lateral double diffused field effect transistor comprising: a body region 8, a drift region 9, a source 16, a drain 17, a first gate 14 and a first field plate 15, the lateral double diffused field effect transistor further comprising: a substrate, the substrate comprising, from bottom to top, a first substrate layer 1, a first oxide layer 2, a heavily doped silicon layer 3, a second oxide layer 5 and a second substrate layer 4, the second substrate layer 4 and the second oxide layer 5 protrude from the upper surface of the heavily doped silicon layer 3 in a stepped manner; the body region 8, the drift region 9, the source 16, the drain 17, the first gate 14 and the first field plate 15, the lateral double diffused field effect transistor further comprising: a substrate, the substrate comprising, from bottom to top, a first substrate layer 1, a first oxide layer 2, a heavily doped silicon layer 3, a second oxide layer 5 and a second substrate layer 4, the second substrate layer 4 and the second oxide layer 5 protrude from the upper surface of the heavily doped silicon layer 3 in a stepped manner; the body region 8, the drift region 9, the source 16, the The drain 17, the first gate 14 and the first field plate 15 are formed on the second substrate layer 4; the first substrate layer 1 and the body region 8 have a first conductivity type, the heavily doped silicon layer 3 and the drift region 9 have a second conductivity type, and the first conductivity type and the second conductivity type have different ion doping types; the second oxide layer 5 includes: a gate oxide layer 6 and a field plate oxide layer 7, the gate oxide layer 6 extends from the bottom of the body region 8 to the bottom of a portion of the drift region 9, the field plate oxide layer 7 is formed at the bottom of a portion of the drift region 9, and the thickness of the field plate oxide layer 7 is greater than the thickness of the gate oxide layer 6;

[0049] A heavily doped polysilicon layer 13 and a third oxide layer 12 are formed on the upper surface of the heavily doped silicon layer 3 not covered by the second oxide layer 5 and the second substrate layer 4, the third oxide layer 12 is located between the heavily doped polysilicon layer 13 and the second substrate layer 4 and the second oxide layer 5 protruding from the heavily doped silicon layer 3, and the third oxide layer 12 is in close contact with the body region 8 formed on the second substrate layer 4; the heavily doped polysilicon layer 13 has a second conductivity type;

[0050] The heavily doped polysilicon layer 13, the third oxide layer 12, the second oxide layer 5 formed at the bottom of the body region 8 and at the bottom of a portion of the drift region 9, and the heavily doped silicon layer 3 formed at the bottom of the heavily doped polysilicon layer 13, the bottom of the body region 8 and at the bottom of a portion of the drift region 9 together serve as a second gate, and the remaining heavily doped silicon layer 3 and the remaining second oxide layer 5 together serve as a second field plate.

[0051] Specifically, in the embodiment of the present invention, the substrate of the lateral double diffused field effect transistor includes, from bottom to top, a first substrate layer 1, a first oxide layer 2, a heavily doped silicon layer 3, a second oxide layer 5, and a second substrate layer 4. The second substrate layer 4 and the second oxide layer 5 protrude from the upper surface of the heavily doped silicon layer 3 in a stepped manner, and the body region 8, the drift region 9, the source 16, the drain 17, the first gate 14, and the first field plate 15 are formed on the second substrate layer 4. The first substrate layer 1 and the body region 8 have a first conductivity type, the heavily doped silicon layer 3 and the drift region 9 have a second conductivity type, and the ion doping types of the first conductivity type and the second conductivity type are different. A heavily doped polysilicon layer 13 and a third oxide layer 12 are formed on the upper surface of the heavily doped silicon layer 3 not covered by the second oxide layer 5 and the second substrate layer 4. The third oxide layer 12 is located between the heavily doped polysilicon layer 13 and the second substrate layer 4 and the second oxide layer 5 protruding from the heavily doped silicon layer 3, and the third oxide layer 12 is in close contact with the body region 8 formed on the second substrate layer 4. The heavily doped polysilicon layer 13 has a second conductivity type.

[0052] The heavily doped polysilicon layer 13, the third oxide layer 12, the second oxide layer 5 formed at the bottom of the body region 8 and the bottom of part of the drift region 9, and the heavily doped silicon layer 3 formed at the bottom of the heavily doped polysilicon layer 13, the bottom of the body region 8 and the bottom of part of the drift region 9 together serve as the second gate, and the remaining heavily doped silicon layer 3 and the remaining second oxide layer 5 together serve as the second field plate. The second oxide layer 5 includes a gate oxide layer 6 and a field plate oxide layer 7. The gate oxide layer 6 extends from the bottom of the body region 8 to the bottom of part of the drift region 9. The field plate oxide layer 7 is formed at the bottom of part of the drift region 9. The thickness of the field plate oxide layer 7 is greater than that of the gate oxide layer 6. In this way, the second field plate can withstand a larger voltage. On the basis of the first field plate 15 and the first gate 14, a second gate and a second field plate are added. The carriers can not only Fig.12 As shown by the solid arrow in the middle, in the body region 8, the channel from the source 16 along the bottom of the first gate 14 enters the drift region 9, and then reaches the drain 17 along the bottom of the first field plate 15. Fig.12 As shown by the hollow arrow, in the body region 8, the carriers go from the source 16 along the third oxide layer 12 to the second oxide layer 5, and then enter the drift region 9 along the second oxide layer 5, and directly reach the drain 17 from the bottom of the drift region 9, or first reach the bottom of the first field plate 15, and then reach the drain 17 along the bottom of the first field plate 15, thereby increasing multiple carrier flow channels.

[0053] The lateral double diffused field effect transistor provided by the present invention can increase the carrier flow channel, increase the operating current of the lateral double diffused field effect transistor, and improve the driving capability, thereby better driving the load, increasing the output power of the transistor, thereby enhancing the signal transmission capability, increasing the switching speed of the transistor, and reducing the breaking loss. Under the same operating current requirement, the transistor area can be reduced and the production cost can be reduced.

[0054] Further, the thickness of the first field plate oxide layer 11 is greater than the thickness of the field plate oxide layer 7 ; wherein the first field plate oxide layer 11 is the oxide layer of the first field plate 15 .

[0055] Specifically, in the embodiment of the present invention, the thickness of the first field plate oxide layer 11 is greater than the thickness of the field plate oxide layer 7, the distance between the first field plate 15 and the drain 17 is relatively close, and the larger thickness of the first field plate oxide layer 11 can withstand a larger electric field. The second field plate is relatively far from the drain 17, and the electric field it withstands is smaller than the first field plate 15, and the thickness of the field plate oxide layer 7 can be thinner.

[0056] The lateral double diffused field effect transistor provided by the present invention can increase the breakdown voltage of the first field plate, so that the transistor can operate safely at a higher voltage, reduce the risk of failure due to excessive voltage, and extend the life of the transistor.

[0057] Furthermore, the heavily doped silicon layer 3 is made of polycrystalline silicon.

[0058] Furthermore, the heavily doped silicon layer 3 is made of single crystal silicon.

[0059] Furthermore, the heavily doped silicon layer 3 , the second oxide layer 5 and the second substrate layer 4 are provided by an SOI substrate.

[0060] Specifically, in the embodiment of the present invention, the heavily doped silicon layer 3 can be made of polycrystalline silicon or single crystal silicon, and those skilled in the art can choose according to actual conditions. In this embodiment, the heavily doped silicon layer 3 is preferably made of polycrystalline silicon, so that the polycrystalline silicon can be directly provided by the SOI substrate without re-manufacturing, which can save manufacturing costs, simplify the manufacturing process, and improve the manufacturing efficiency of the transistor.

[0061] Furthermore, the lateral double diffused field effect transistor further includes: metal electrodes 19 formed on the source 16 , the drain 17 , the first gate 14 and the heavily doped silicon layer 3 , respectively; and an oxide isolation layer 18 formed between two adjacent metal electrodes 19 .

[0062] Specifically, in the embodiment of the present invention, metal electrodes 19 are formed on the source 16, the drain 17, the first gate 14 and the heavily doped silicon layer 3. An oxide isolation layer 18 is formed between two adjacent metal electrodes 19 to isolate the two adjacent metal electrodes 19.

[0063] Please refer to Fig.13 The second aspect of the present invention provides a method for manufacturing a lateral double diffused field effect transistor, the method comprising:

[0064] S101: forming a substrate; wherein the substrate comprises, from bottom to top, a first substrate layer 1, a first oxide layer 2, a heavily doped silicon layer 3, a second oxide layer 5, and a second substrate layer 4, wherein the second substrate layer 4 and the second oxide layer 5 protrude from the upper surface of the heavily doped silicon layer 3 in a stepped manner; the first substrate layer 1 has a first conductivity type, the heavily doped silicon layer 3 has a second conductivity type, and the first conductivity type and the second conductivity type have different ion doping types; the second oxide layer 5 comprises: a gate oxide layer 6 and a field plate oxide layer 7, wherein the gate oxide layer 6 extends from the bottom of the body region 8 to the bottom of a portion of the drift region 9, the field plate oxide layer 7 is formed at the bottom of the portion of the drift region 9, and the thickness of the field plate oxide layer 7 is greater than the thickness of the gate oxide layer 6;

[0065] S102: forming a heavily doped polysilicon layer 13 and a third oxide layer 12 on the upper surface of the heavily doped silicon layer 3 not covered by the second oxide layer 5 and the second substrate layer 4, wherein the third oxide layer 12 is located between the heavily doped polysilicon layer 13 and the second substrate layer 4 and the second oxide layer 5 protruding from the heavily doped silicon layer 3, and the third oxide layer 12 is in close contact with the body region 8 to be formed on the second substrate layer 4; the heavily doped polysilicon layer 13 has a second conductivity type;

[0066] S103: forming a body region 8, a drift region 9, a source 16, a drain 17, a first gate 14 and a first field plate 15 on the second substrate layer 4; the body region 8 has a first conductivity type, and the drift region has a second conductivity type; wherein the heavily doped polysilicon layer 13, the third oxide layer 12, the second oxide layer 5 formed at the bottom of the body region 8 and part of the bottom of the drift region 9, and the heavily doped silicon layer 3 formed at the heavily doped polysilicon layer 13, the bottom of the body region 8 and part of the bottom of the drift region 9 together serve as a second gate, and the remaining heavily doped silicon layer 3 and the remaining second oxide layer 5 together serve as a second field plate.

[0067] Specifically, firstly perform step S101: forming a substrate; wherein, the substrate comprises, from bottom to top, a first substrate layer 1, a first oxide layer 2, a heavily doped silicon layer 3, a second oxide layer 5 and a second substrate layer 4, the second substrate layer 4 and the second oxide layer 5 protrude from the upper surface of the heavily doped silicon layer 3 in a stepped manner; the first substrate layer 1 has a first conductivity type, the heavily doped silicon layer 3 has a second conductivity type, and the first conductivity type and the second conductivity type have different ion doping types; the second oxide layer 5 comprises: a gate oxide layer 6 and a field plate oxide layer 7, the gate oxide layer 6 extends from the bottom of the body region 8 to the bottom of a portion of the drift region 9, the field plate oxide layer 7 is formed at the bottom of the portion of the drift region 9, and the thickness of the field plate oxide layer 7 is greater than the thickness of the gate oxide layer 6.

[0068] Furthermore, the heavily doped silicon layer 3 is made of polycrystalline silicon.

[0069] Furthermore, the heavily doped silicon layer 3 is made of single crystal silicon.

[0070] Furthermore, the formation of the substrate includes: providing an SOI substrate, the SOI substrate including, from bottom to top, the first substrate layer 1, the first oxide layer 2 and the heavily doped silicon layer 3; forming a pasting oxide layer on the surface of the heavily doped silicon layer 3; providing a second substrate layer 4, and forming the second oxide layer 5 on the second substrate layer 4; using the pasting oxide layer to bond the second oxide layer 5 to the heavily doped silicon layer 3; using an etching process to remove part of the second substrate layer 4 and part of the second oxide layer 5 to form the substrate.

[0071] Furthermore, the forming of the second oxide layer 5 on the second substrate layer 4 includes: forming a sacrificial oxide layer on the second substrate layer 4; removing part of the sacrificial oxide layer by an etching process to form an etching window; removing part of the second substrate layer 4 through the etching window to form a stepped second substrate layer 4; forming a thermal oxide layer on the surface of the sacrificial oxide layer and the surface of the second substrate layer 4 not covered by the sacrificial oxide layer by a thermal oxidation process, using the remaining sacrificial oxide layer and the thermal oxide layer thereon as the gate oxide layer 6, and using the thermal oxide layer on the exposed second substrate layer 4 as the field plate oxide layer 7.

[0072] Specifically, the lateral double diffused field effect transistor provided in the embodiment of the present invention can be an N-type lateral double diffused field effect transistor or a P-type lateral double diffused field effect transistor. When the lateral double diffused field effect transistor is an N-type lateral double diffused field effect transistor, the first doping type is P-type and the second doping type is N-type; when the lateral double diffused field effect transistor is a P-type lateral double diffused field effect transistor, the first doping type is N-type and the second doping type is P-type. The present invention does not limit this. The following text embodiment only takes the N-type lateral double diffused field effect transistor as an example for explanation.

[0073] In the embodiment of the present invention, a substrate is first formed, and the substrate is formed by bonding a silicon substrate and a substrate having an oxide layer and a heavily doped silicon layer, wherein the heavily doped silicon layer can be polycrystalline silicon or single crystal silicon. Figure 1As shown, in one possible embodiment, the heavily doped silicon layer 3 is made of polycrystalline silicon. A P-type first substrate layer 1 is first provided, and a first oxide layer 2 is generated on the first substrate layer 1 by a thermal oxidation process, and then a layer of N-type heavily doped polycrystalline silicon is grown on the first oxide layer 2 by a vapor deposition process as the heavily doped silicon layer 3. Then, a thin adhesive oxide layer is thermally oxidized on the upper surface of the heavily doped silicon layer 3. In another possible embodiment, the heavily doped silicon layer 3 is made of single crystal silicon. The substrate having an oxide layer and a heavily doped silicon layer can be directly provided by an SOI substrate, which saves the manufacturing cost of the substrate, saves the process flow, and improves the manufacturing efficiency of the transistor. The SOI substrate includes, from bottom to top: a P-type first substrate layer 1, a first oxide layer 2 and an N-type heavily doped silicon layer 3, and then, a thin adhesive oxide layer is thermally oxidized on the upper surface of the heavily doped silicon layer 3.

[0074] Then, a P-type second substrate layer 4 is provided, and a second oxide layer 5 is formed on the second substrate layer 4. The second oxide layer 5 includes: a gate oxide layer 6 and a field plate oxide layer 7, the gate oxide layer 6 extends from the bottom of the body region 8 to the bottom of a portion of the drift region 9, and the field plate oxide layer 7 is formed at the bottom of the portion of the drift region 9. In a possible implementation, the gate oxide layer 6 and the field plate oxide layer 7 have the same thickness, and in this case, the second oxide layer 5 of a designed thickness can be directly generated by thermal oxidation on the second substrate layer 4.

[0075] In another possible implementation, in order to make the second field plate bear a larger voltage, the thickness of the field plate oxide layer 7 is greater than the thickness of the gate oxide layer 6. Figure 2 The P-type second substrate layer 4 shown in the figure is formed by thermally oxidizing a thick silicon dioxide layer on the second substrate layer 4, forming a photoresist on the silicon dioxide layer, exposing and developing the photoresist, forming an etching window in the photoresist, etching the sacrificial oxide layer using the etching window, forming an etching window in the sacrificial oxide layer, and exposing a portion of the second substrate layer 4. The second substrate layer 4 is etched by a dry etching process to form a Figure 3 The stepped second substrate layer 4 is shown. Figure 4 As shown, a thermal oxide layer is formed on the surface of the sacrificial oxide layer and the surface of the second substrate layer 4 not covered by the sacrificial oxide layer by a thermal oxidation process, and the thermal oxide layer is thinned, and the remaining sacrificial oxide layer and the thermal oxide layer thereon are used as the gate oxide layer 6, and the thermal oxide layer on the exposed second substrate layer 4 is used as the field plate oxide layer 7.

[0076] Next, the second substrate layer 4 is turned over and attached to the adhesive oxide layer on the surface of the first substrate layer 1 to form a Figure 5 The substrate shown in FIG. The substrate comprises, from bottom to top, a first substrate layer 1, a first oxide layer 2, a heavily doped silicon layer 3, a second oxide layer 5 and a second substrate layer 4.

[0077] Then, step S102 is performed: a heavily doped polysilicon layer 13 and a third oxide layer 12 are formed on the upper surface of the heavily doped silicon layer 3 not covered by the second oxide layer 5 and the second substrate layer 4, wherein the third oxide layer 12 is located between the heavily doped polysilicon layer 13 and the second substrate layer 4 and the second oxide layer 5 protruding from the heavily doped silicon layer 3, and the third oxide layer 12 is in close contact with the body region 8 to be formed on the second substrate layer 4; the heavily doped polysilicon layer 13 has a second conductivity type.

[0078] Further, the body region 8, the drift region 9, the third oxide layer 12, the heavily doped polysilicon layer 13, the first gate 14 and the first field plate 15 are formed in the following manner: before the second substrate layer 4 and the second oxide layer 5 are removed by an etching process to form the substrate, the body region 8, the drift region 9 and the first field plate oxide layer 11 are formed on the second substrate layer 4; wherein the first field plate oxide layer 11 is the oxide layer of the first field plate 15; after the second substrate layer 4 and the second oxide layer 5 are removed by an etching process to form the substrate, the first gate oxide layer 10 is formed, and the heavily doped polysilicon layer 13 and the second substrate layer 4 protruding from the heavily doped silicon layer 3 are formed. The third oxide layer 12 is formed between the second oxide layers 5; wherein the first gate oxide layer 10 is the oxide layer of the first gate 14; a polysilicon layer is formed on the exposed surfaces of the heavily doped silicon layer 3 and the second substrate layer 4; a portion of the polysilicon is removed by an etching process, and the polysilicon layer on the exposed heavily doped silicon layer 3, the polysilicon layer on the first gate oxide layer 10, and the polysilicon layer on a portion of the first field plate oxide layer 11 are retained; the polysilicon layer on the exposed heavily doped silicon layer 3 serves as the heavily doped polysilicon layer 13, the first gate oxide layer 10 and the polysilicon layer thereon serve as the first gate 14, and the first field plate oxide layer 11 and the polysilicon layer on a portion of the first field plate oxide layer 11 serve as the first field plate 15.

[0079] Specifically, in the embodiment of the present invention, after the substrate is formed by pasting, a photoresist is formed on the surface of the second substrate layer 4, an ion implantation window is formed on the photoresist by exposure and development, and N-type ions are implanted into the second substrate layer 4 through the ion input window to form a Figure 6 The drift region 9 shown is removed from the photoresist. Photoresist is formed again, an ion implantation window is formed on the photoresist by exposure and development, and P-type ions are implanted into the second substrate layer 4 through the ion input window to form a body region 8, and the photoresist is removed.

[0080] A thin layer of silicon dioxide is thermally oxidized on the surface of the second substrate layer 4, and then a thick layer of silicon dioxide is chemically vapor deposited to form a photoresist on the surface of the silicon dioxide. The photoresist is dry-etched to retain part of the silicon dioxide on the surface of the drift region 9, so as to form a Figure 7 The first field plate oxide layer 11 is shown. The photoresist is removed and the thin silicon dioxide layer is removed by wet etching.

[0081] The etching process is used to remove part of the body region 8 and the second oxide layer 5 below the body region 8 to form Figure 8 As shown, the second substrate layer 4 and the second oxide layer 5 protrude from the upper surface of the heavily doped silicon layer 3 in a stepped manner. Fig. 9 As shown, the surface of the transistor is then thermally oxidized to form a thin oxide layer on the second substrate layer 4, the upper surface of the heavily doped silicon layer 3, and the body region 8 and the side surface of the second oxide layer 5. The oxide layer on the heavily doped silicon layer 3 is removed by wet etching, and the oxide layer on the body region 8 and the side surface of the second oxide layer 5 is used as the third oxide layer 12, and the oxide layer on part of the body region 8 and the drift region 9 is used as the first gate oxide layer 10.

[0082] like Fig.10 As shown, a N-type heavily doped polysilicon layer is formed on the surface of the exposed heavily doped silicon layer 3 and the second substrate layer 4 by low-pressure chemical vapor deposition process, and the excess polysilicon on the surface is removed to the designed height by chemical mechanical polishing. A photoresist is formed, and the photoresist is exposed and developed to form an etching window. A portion of the polysilicon is removed through the etching window, and the polysilicon layer on the exposed heavily doped silicon layer 3, the polysilicon layer on the first gate oxide layer 10, and the polysilicon layer on a portion of the first field plate oxide layer 11 are retained. The polysilicon layer on the exposed heavily doped silicon layer 3 is used as a heavily doped polysilicon layer 13, the first gate oxide layer 10 and the polysilicon layer thereon are used as a first gate 14, and the first field plate oxide layer 11 and the polysilicon layer on a portion of the first field plate oxide layer 11 are used as a first field plate 15.

[0083] Finally, step S103 is performed: a body region 8, a drift region 9, a source 16, a drain 17, a first gate 14 and a first field plate 15 are formed on the second substrate layer 4; the body region 8 has a first conductivity type, and the drift region 9 has a second conductivity type.

[0084] Specifically, in the embodiment of the present invention, a photoresist is formed on the surface of the substrate, the photoresist is exposed and developed to form an ion implantation window, N-type ions are implanted into the second substrate layer 4 through the ion implantation window, the photoresist is removed, and annealing is performed to form a Fig.11 A source 16 and a drain 17 are shown.

[0085] Furthermore, the method also includes: forming an oxidizing dielectric layer on the surface of the substrate; forming contact holes in the oxidizing dielectric layer by an etching process, wherein the contact holes are respectively in contact with the source 16, the drain 17, the first gate 14 and the heavily doped silicon layer 3; forming a metal electrode 19 in the contact hole by a deposition process, and the oxidizing dielectric layer between two adjacent metal electrodes 19 serves as the oxidizing isolation layer 18.

[0086] Specifically, in the embodiment of the present invention, Fig.12 As shown, an oxidized dielectric layer is formed on the surface of the substrate, and a portion of the oxidized dielectric layer is removed to form contact holes, which are respectively in contact with the source 16, the drain 17, the first gate 14 and the heavily doped silicon layer 3. A layer of metal is physically vapor deposited on the surface of the substrate, and a metal electrode 19 is formed in the contact hole to lead out the source 16, the drain 17, the first gate 14 and the heavily doped silicon layer 3. The oxidized dielectric layer between two adjacent metal electrodes 19 serves as an oxidized isolation layer 18.

[0087] A third aspect of the present invention provides a chip, which includes the lateral double diffused field effect transistor described above.

[0088] A fourth aspect of the present invention provides a circuit comprising the lateral double diffused field effect transistor described above.

[0089] The preferred embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the present invention is not limited to the specific details in the above embodiments. Within the technical concept of the present invention, a variety of simple modifications can be made to the technical solution of the present invention, and these simple modifications all belong to the protection scope of the present invention.

[0090] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not further describe various possible combinations.

[0091] In addition, various embodiments of the present invention may be arbitrarily combined, and as long as they do not violate the concept of the present invention, they should also be regarded as the contents disclosed by the present invention.

Claims

1. A lateral double diffused field effect transistor, comprising: A body region, a drift region, a source, a drain, a first gate and a first field plate, wherein the lateral double diffused field effect transistor further comprises: A substrate, the substrate comprising, from bottom to top, a first substrate layer, a first oxide layer, a heavily doped silicon layer, a second oxide layer, and a second substrate layer, wherein the second substrate layer and the second oxide layer protrude from the upper surface of the heavily doped silicon layer in a stepped manner; the body region, the drift region, the source, the drain, the first gate, and the first field plate are formed on the second substrate layer; the first substrate layer and the body region have a first conductivity type, the heavily doped silicon layer and the drift region have a second conductivity type, and the ion doping types of the first conductivity type and the second conductivity type are different; the second oxide layer comprises: a gate oxide layer and a field plate oxide layer, the gate oxide layer extends from the bottom of the body region to the bottom of a portion of the drift region, the field plate oxide layer is formed at the bottom of a portion of the drift region, and the thickness of the field plate oxide layer is greater than the thickness of the gate oxide layer; A heavily doped polysilicon layer and a third oxide layer are formed on an upper surface of the heavily doped silicon layer that is not covered by the second oxide layer and the second substrate layer, the third oxide layer is located between the heavily doped polysilicon layer, the second substrate layer protruding from the heavily doped silicon layer, and the second oxide layer, and the third oxide layer is in close contact with a body region formed on the second substrate layer; the heavily doped polysilicon layer has a second conductivity type; The heavily doped polysilicon layer, the third oxide layer, the second oxide layer formed at the bottom of the body region and part of the drift region, and the heavily doped silicon layer formed at the bottom of the heavily doped polysilicon layer, the bottom of the body region and part of the drift region together serve as a second gate, and the remaining heavily doped silicon layer and the remaining second oxide layer together serve as a second field plate.

2. The lateral double diffused field effect transistor according to claim 1, characterized in that: The thickness of the first field plate oxide layer is greater than the thickness of the field plate oxide layer; wherein the first field plate oxide layer is the oxide layer of the first field plate.

3. The lateral double diffused field effect transistor according to claim 1, characterized in that: The heavily doped silicon layer is made of polysilicon.

4. The lateral double diffused field effect transistor according to claim 1, characterized in that: The heavily doped silicon layer is made of single crystal silicon.

5. The lateral double diffused field effect transistor according to claim 4, characterized in that: The heavily doped silicon layer, the second oxide layer and the second substrate layer are provided by an SOI substrate.

6. The lateral double diffused field effect transistor according to claim 1, characterized in that: The lateral double diffused field effect transistor further comprises: Metal electrodes are formed on the source electrode, the drain electrode, the first gate electrode and the heavily doped silicon layer respectively; An oxide isolation layer is formed between two adjacent metal electrodes.

7. A method for manufacturing a lateral double diffused field effect transistor, characterized in that: The method for manufacturing a lateral double diffused field effect transistor comprises: A substrate is formed; wherein the substrate comprises, from bottom to top, a first substrate layer, a first oxide layer, a heavily doped silicon layer, a second oxide layer, and a second substrate layer, wherein the second substrate layer and the second oxide layer protrude from the upper surface of the heavily doped silicon layer in a stepped manner; the first substrate layer has a first conductivity type, the heavily doped silicon layer has a second conductivity type, and the first conductivity type and the second conductivity type have different ion doping types; the second oxide layer comprises: a gate oxide layer and a field plate oxide layer, wherein the gate oxide layer extends from the bottom of the body region to the bottom of a portion of the drift region, the field plate oxide layer is formed at the bottom of the portion of the drift region, and the thickness of the field plate oxide layer is greater than the thickness of the gate oxide layer; forming a heavily doped polysilicon layer and a third oxide layer on the upper surface of the heavily doped silicon layer not covered by the second oxide layer and the second substrate layer, wherein the third oxide layer is located between the heavily doped polysilicon layer and the second substrate layer protruding from the heavily doped silicon layer and the second oxide layer, and the third oxide layer is in close contact with a body region to be formed on the second substrate layer; the heavily doped polysilicon layer has a second conductivity type; A body region, a drift region, a source, a drain, a first gate and a first field plate are formed on the second substrate layer; the body region has a first conductivity type, and the drift region has a second conductivity type; wherein the heavily doped polysilicon layer, the third oxide layer, the second oxide layer formed at the bottom of the body region and part of the drift region, and the heavily doped silicon layer formed at the heavily doped polysilicon layer, the bottom of the body region and part of the drift region together serve as a second gate, and the remaining heavily doped silicon layer and the remaining second oxide layer together serve as a second field plate.

8. The method for manufacturing a lateral double diffused field effect transistor according to claim 7, characterized in that: The heavily doped silicon layer is made of polysilicon.

9. The method for manufacturing a lateral double diffused field effect transistor according to claim 7, characterized in that: The heavily doped silicon layer is made of single crystal silicon.

10. The method for manufacturing a lateral double diffused field effect transistor according to claim 9, characterized in that: The forming substrate comprises: Providing an SOI substrate, the SOI substrate comprising, from bottom to top, the first substrate layer, the first oxide layer and the heavily doped silicon layer; forming an adhesive oxide layer on the surface of the heavily doped silicon layer; Providing a second substrate layer, and forming the second oxide layer on the second substrate layer; bonding the second oxide layer to the heavily doped silicon layer using the adhesive oxide layer; A portion of the second substrate layer and a portion of the second oxide layer are removed by an etching process to form the substrate.

11. The method for manufacturing a lateral double diffused field effect transistor according to claim 10, characterized in that: The forming of the second oxide layer on the second substrate layer comprises: forming a sacrificial oxide layer on the second substrate layer; Using an etching process to remove part of the sacrificial oxide layer to form an etching window; removing a portion of the second substrate layer through the etching window to form a stepped second substrate layer; A thermal oxide layer is formed on the surface of the sacrificial oxide layer and the surface of the second substrate layer not covered by the sacrificial oxide layer by a thermal oxidation process, the remaining sacrificial oxide layer and the thermal oxide layer thereon are used as the gate oxide layer, and the thermal oxide layer on the exposed second substrate layer is used as the field plate oxide layer.

12. The method for manufacturing a lateral double diffused field effect transistor according to claim 10, characterized in that: The body region, the drift region, the third oxide layer, the heavily doped polysilicon layer, the first gate and the first field plate are formed in the following manner: Before removing a portion of the second substrate layer and a portion of the second oxide layer by an etching process to form the substrate, the body region, the drift region and the first field plate oxide layer are formed on the second substrate layer; wherein the first field plate oxide layer is the oxide layer of the first field plate; After the substrate is formed by removing part of the second substrate layer and part of the second oxide layer by an etching process, a first gate oxide layer is formed, and the third oxide layer is formed between the delineated heavily doped polysilicon layer and the second substrate layer and the second oxide layer protruding from the heavily doped silicon layer; wherein the first gate oxide layer is an oxide layer of the first gate; forming a polysilicon layer on the exposed heavily doped silicon layer and the surface of the second substrate layer; An etching process is used to remove part of the polysilicon, and the polysilicon layer on the exposed heavily doped silicon layer, the polysilicon layer on the first gate oxide layer, and the polysilicon layer on part of the first field plate oxide layer are retained. The polysilicon layer on the exposed heavily doped silicon layer serves as the heavily doped polysilicon layer, the first gate oxide layer and the polysilicon layer thereon serve as the first gate, and the first field plate oxide layer and the polysilicon layer on part of the first field plate oxide layer serve as the first field plate.

13. The method for manufacturing a lateral double diffused field effect transistor according to claim 7, characterized in that: The method further comprises: forming an oxidizing medium layer on the surface of the substrate; Forming contact holes in the oxide dielectric layer by an etching process, wherein the contact holes are in contact with the source electrode, the drain electrode, the first gate electrode and the heavily doped silicon layer respectively; A metal electrode is formed in the contact hole by a deposition process, and the oxide medium layer between two adjacent metal electrodes serves as an oxide isolation layer.

14. A chip, characterized in that: The chip comprises the lateral double diffused field effect transistor according to any one of claims 1 to 6.

15. A circuit, characterized in that: The circuit comprises the lateral double diffused field effect transistor according to any one of claims 1-6.