Silicon carbide transistor discrete device and preparation method thereof

Abstract

The present application is applicable to the field of semiconductor device technology, and provides a silicon carbide transistor discrete device and a preparation method thereof, wherein the device includes a SiC MOSFET chip and a SiC SBD chip on the top of a copper frame; a drain terminal, a source terminal, a Kelvin terminal and a gate terminal are provided on the side of the copper frame; the drain terminal is connected to the copper frame; the other terminals are electrically isolated from the copper frame; the upper surface of the SiC MOSFET chip has a source pad and a gate pad; the source pad includes a first, a second and a third source pad; the upper surface of the SiC SBD chip has an anode pad; the first source pad is connected to the anode pad, the second source pad is connected to the source terminal, the third source pad is connected to the Kelvin terminal, and the gate pad is connected to the gate terminal, so that the chip is connected in anti-parallel. The present application can reduce the freewheeling and switching losses of SiC MOSFET, reduce costs, disperse the heat consumption of the device, improve the heat dissipation capacity of the device, and meet the application of high-power scenarios.

Description

Technical Field

[0001] The present application belongs to the technical field of semiconductor devices, and in particular, relates to a discrete silicon carbide transistor device and a method for preparing the same. Background Art

[0002] Silicon carbide is a third-generation semiconductor with a large bandgap, high thermal conductivity, and high saturation drift velocity. SiC MOSFET made from it has smaller conduction loss, switching loss, and higher switching frequency. Its overall performance is better than traditional power devices such as Si IGBT. It has great application potential in the fields of electric vehicles, wind power storage, and industrial control.

[0003] However, the parasitic body diode of SiC MOSFET is SiC PiN diode, which has a high conduction voltage drop of about 3V~5V, which leads to an increase in conduction loss during reverse freewheeling of the device; SiC PiN is a bipolar device, and when it is turned off, it takes a certain amount of time to extract the unbalanced carriers in the drift region, which leads to large reverse recovery losses of the device; and as the turn-on time of the SiCPiN diode accumulates, the energy released by the long-term recombination of electrons and holes will induce a bipolar degradation effect, reducing the reliability of SiC MOSFET.

[0004] At present, the solution is to integrate an anti-parallel silicon carbide Schottky diode (Schottky Barrier Diode, SBD) inside the SiC MOSFET chip as the freewheeling diode of the SiC MOSFET. The on-state voltage drop of the SiC SBD is as low as about 1V, which greatly reduces the freewheeling conduction loss; the SiC SBD is a unipolar device with very small reverse recovery loss; and there is no bipolar degradation effect, so the reliability is high. However, the cost of integrating the SiC SBD inside the SiC MOSFET chip is relatively high, and the heat generation is relatively concentrated, which is not conducive to the promotion and use of the device in high-power scenarios. Summary of the invention

[0005] In order to overcome the problems existing in the related technology, the embodiments of the present application provide a silicon carbide transistor discrete device and a preparation method thereof, which can reduce the follow-on loss and switching loss of the SiC MOSFET device, while reducing the cost of the device, dissipating the heat consumption of the device, and improving the heat dissipation capacity of the device to meet the application of high-power scenarios.

[0006] This application is implemented through the following technical solutions:

[0007] In a first aspect, an embodiment of the present application provides a silicon carbide transistor discrete device, including: a copper frame, a SiC MOSFET chip, a SiC SBD chip, a drain terminal, a source terminal, a Kelvin terminal, a gate terminal, a source pad, a gate pad, and an anode pad;

[0008] A SiC MOSFET chip and a SiC SBD chip are arranged above the copper frame; a drain terminal, a source terminal, a Kelvin terminal and a gate terminal are arranged on the side of the copper frame; the upper surface of the drain terminal is flush with the upper surface of the copper frame and is connected to the copper frame; the upper surfaces of the source terminal, the Kelvin terminal and the gate terminal are all flush with the upper surface of the copper frame and are electrically isolated from the copper frame;

[0009] The upper surface of the SiC MOSFET chip is provided with a source pad and a gate pad; the source pad includes a first source pad, a second source pad and a third source pad;

[0010] An anode pad is provided on the upper surface of the SiC SBD chip;

[0011] The first source pad is connected to the anode pad, the second source pad is connected to the source terminal, the third source pad is connected to the Kelvin terminal, and the gate pad is connected to the gate terminal, so that the SiC MOSFET chip and the SiC SBD chip are connected in anti-parallel.

[0012] In one embodiment, the first source pad is connected to the anode pad via a double bonding wire; the second source pad is connected to the source terminal via a double bonding wire; the third source pad is connected to the Kelvin terminal via a single bonding wire; and the gate pad is connected to the gate terminal via a single bonding wire.

[0013] In one embodiment, the first source pad is connected to the anode pad through a single bonding wire; the second source pad is connected to the source terminal through a single bonding wire; the anode pad is connected to the source terminal through a single bonding wire; the third source pad is connected to the Kelvin terminal through a single bonding wire; and the gate pad is connected to the gate terminal through a single bonding wire.

[0014] In one embodiment, it further comprises a bonding material; the bonding material is nanosilver;

[0015] The SiC MOSFET chip and the SiC SBD chip are attached to the upper surface of the copper frame by adhesive material.

[0016] In one embodiment, it also includes a heat dissipation copper sheet and a ceramic gasket;

[0017] The ceramic gasket is located on the upper surface of the heat dissipation copper sheet;

[0018] The copper frame is located on the upper surface of the ceramic spacer.

[0019] In one embodiment, it further includes a plastic packaging material;

[0020] The plastic packaging material is filled in the gap between and around the SiC MOSFET chip and the SiC SBD chip to wrap the SiC MOSFET chip and the SiC SBD chip.

[0021] In one embodiment, the material of the bonding wire includes aluminum, copper or silver.

[0022] In one embodiment, the source pad further includes a fourth source pad; and the gate pad is disposed between the third source pad and the fourth source pad.

[0023] In one embodiment, it further includes a mounting hole;

[0024] The assembly holes are arranged on the upper surface of the copper frame for assembling components.

[0025] In a second aspect, the present application provides a method for preparing a discrete silicon carbide transistor device, comprising:

[0026] The SiC MOSFET chip and the SiC SBD chip are surface mounted on the upper surface of the metal copper frame using the patch process;

[0027] Using a bonding process, the source pad and the gate pad on the upper surface of the SiC MOSFET chip, the anode pad and each terminal on the upper surface of the SiC SBD chip are bonded to form an anti-parallel connection between the SiC MOSFET chip and the SiC SBD chip;

[0028] The injection molding process is used to fill the plastic encapsulation material between the SiC MOSFET chip, the SiC SBD chip and the bonding wire, and then the plastic encapsulation material is cured.

[0029] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0030] In the embodiment of the present application, by adopting the method of anti-parallel silicon carbide Schottky diode outside the SiC MOSFET chip, when a positive voltage is applied between the gate terminal and the Kelvin terminal, the SiC MOSFET channel is turned on, and a forward bias is applied between the drain terminal and the source terminal, and the device is forward-biased; during reverse continuous current, since the conduction voltage drop of the SiC SBD is much smaller than the body diode of the SiCMOSFET, only the SiC SBD is turned on, and the body diode is suppressed. This reduces switching loss and continuous current loss, avoids bipolar degradation, disperses heat loss, improves the heat dissipation capacity of the device, and can meet high-power scenario applications. Heat dissipation is further increased by setting a copper frame.

[0031] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0033] Figure 1 is a schematic structural diagram of a discrete silicon carbide transistor device provided in one embodiment of the present application;

[0034] Figure 2 It is a schematic diagram of a PFC circuit and a CLLC circuit in a high-power scenario provided by an embodiment of the present application;

[0035] Figure 3 : is a schematic diagram comparing the heat dissipation area of ​​one chip and two chips provided in an embodiment of the present application; wherein, Figure 3 (a) is a schematic diagram of a chip; Figure 3 (b) is a schematic diagram of two chips;

[0036] Figure 4 is a schematic structural diagram of another discrete silicon carbide transistor device provided in an embodiment of the present application;

[0037] Figure 5 is a schematic structural diagram of another discrete silicon carbide transistor device provided in one embodiment of the present application;

[0038] Figure 6 is a schematic structural diagram of yet another discrete silicon carbide transistor device provided in one embodiment of the present application;

[0039] Figure 7 is a schematic diagram of a process for preparing a discrete silicon carbide transistor device provided by an embodiment of the present application; wherein, Figure 7 (a) is the first schematic diagram of preparing a discrete silicon carbide transistor device; Figure 7 (b) is the second schematic diagram of preparing a discrete silicon carbide transistor device; Figure 7 (c) is the third schematic diagram of preparing silicon carbide transistor discrete devices. DETAILED DESCRIPTION

[0040] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0041] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0042] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0043] As used in the specification and appended claims of this application, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [described condition or event] is detected" or "in response to detecting [described condition or event]", depending on the context.

[0044] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0045] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0046] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0047] Figure 1 is a schematic diagram of the structure of a discrete silicon carbide transistor device provided in an embodiment of the present application, with reference to Figure 1 , the detailed description of the silicon carbide transistor discrete device is as follows:

[0048] An embodiment of the present application provides a silicon carbide transistor discrete device, including: a copper frame 1, a SiC MOSFET chip 2, a SiC SBD chip 3, a drain terminal 4, a source terminal 5, a Kelvin terminal 6, a gate terminal 7, a source pad 21, a gate pad 22 and an anode pad 31.

[0049] A SiC MOSFET chip 2 and a SiC SBD chip 3 are arranged above the copper frame 1; a drain terminal 4, a source terminal 5, a Kelvin terminal 6 and a gate terminal 7 are arranged on the side of the copper frame 1; the upper surface of the drain terminal 4 is flush with the upper surface of the copper frame 1 and is connected to the copper frame 1; the upper surfaces of the source terminal 5, the Kelvin terminal 6 and the gate terminal 7 are all flush with the upper surface of the copper frame 1 and are electrically isolated from the copper frame 1.

[0050] The upper surface of the SiC MOSFET chip 2 is provided with a source pad 21 and a gate pad 22; the source pad 21 includes a first source pad 211, a second source pad 212 and a third source pad 213. Among them, because the source pad 21 includes multiple pads, Figure 1 The source pad 21 is not marked.

[0051] An anode pad 31 is provided on the upper surface of the SiC SBD chip 3 .

[0052] The first source pad 211 is connected to the anode pad 31 , the second source pad 212 is connected to the source terminal 5 , the third source pad 213 is connected to the Kelvin terminal 6 , and the gate pad 22 is connected to the gate terminal 7 , so that the SiC MOSFET chip 2 and the SiC SBD chip 3 are connected in anti-parallel.

[0053] Exemplarily, the source pad 21 also includes a fourth source pad 214; the gate pad 22 is arranged between the third source pad 213 and the fourth source pad 214. The third source pad 213 and the fourth source pad 214 are symmetrically arranged on the right side of the SiC MOSFET chip 2 and on both sides of the gate pad 22, which is convenient for connection and use. If only one source pad is arranged on the right side of the SiC MOSFET chip 2, the placement direction of the chip is limited. If there are two pads, the placement position and direction of the chip can be more flexible.

[0054] This embodiment reduces the SiC MOSFET device's follow-on loss and switching loss by packaging the SiC SBD in anti-parallel, while reducing the device's cost, dissipating the device's heat consumption, and improving the heat dissipation capability, which is conducive to meeting the application requirements of high-power scenarios.

[0055] High power scenarios such as Figure 2As shown in the figure, in a 20kW bidirectional on-board charger, the PFC (Power Factor Correction) circuit is composed of six SiC MOSFET devices, and the CLLC circuit is composed of eight SiC MOSFET devices. Since the power supply is large, the SiC MOSFET is required to have low losses and good heat dissipation. Therefore, in order to reduce losses, an anti-parallel SBD is required, which reduces the SiC MOSFET device's freewheeling loss and switching loss while reducing the device's cost. As for the heat dissipation problem, if the device adopts the method of integrating an anti-parallel silicon carbide Schottky diode (Schottky Barrier Diode, SBD) inside the SiC MOSFET chip, such as Figure 3 As shown in (a), since it has only one chip, the heat dissipation area is small, the thermal resistance is large, and the heat dissipation is poor, which will cause the junction temperature to rise and cannot meet the application of high-power scenarios; if the device adopts the method of anti-parallel silicon carbide Schottky diode outside the SiC MOSFET chip, such as Figure 3 As shown in (b), under a certain power consumption, since there are two chips to disperse the heat at the same time, the heat dissipation area is large, the total thermal resistance is small, and the heat dissipation is good, which can meet the use of high-power scenarios.

[0056] In one embodiment, the copper frame may be a TO-247PLUS frame, such as Figure 1 As shown, this embodiment introduces the characteristics of the TO-247PLUS packaged automotive-grade low-loss silicon carbide transistor discrete device based on the above embodiment. The first source pad 211 is connected to the anode pad 31 through a double bonding wire; the second source pad 212 is connected to the source terminal 5 through a double bonding wire; the third source pad 213 is connected to the Kelvin terminal 6 through a single bonding wire; the gate pad 22 is connected to the gate terminal 7 through a single bonding wire.

[0057] When a positive voltage is applied between the gate terminal 7 and the Kelvin terminal 6, the SiC MOSFET channel is turned on. At this time, a forward bias is applied between the drain terminal 4 and the source terminal 5, and the device is forward-conducted. During reverse freewheeling, since the conduction voltage drop of the SiC SBD is much smaller than the body diode of the SiC MOSFET, only the SiC SBD is turned on, and the body diode is suppressed. This reduces switching loss and freewheeling loss, avoids bipolar degradation, disperses heat loss, and improves the heat dissipation capacity of the device, which can meet high-power scene applications.

[0058] Exemplarily, the silicon carbide transistor discrete device further includes a bonding material 8, such as Figure 4 and Figure 5As shown, the SiC MOSFET chip 2 and the SiC SBD chip 3 are attached to the upper surface of the copper frame 1 by means of an adhesive material 8. The adhesive material 8 may be nano silver, which plays a key role in enabling the device to pass the automotive reliability standard.

[0059] In one embodiment, the copper frame may be a TO-247 frame, such as Figure 4 As shown, this embodiment introduces the characteristics of a low-loss silicon carbide transistor discrete device in a TO-247 package based on the above embodiment. The first source pad 211 is connected to the anode pad 31 through a single bonding wire; the second source pad 212 is connected to the source terminal 5 through a single bonding wire; the anode pad 31 is connected to the source terminal 5 through a single bonding wire; the third source pad 213 is connected to the Kelvin terminal 6 through a single bonding wire; and the gate pad 22 is connected to the gate terminal 7 through a single bonding wire.

[0060] When a positive voltage is applied between the gate terminal 7 and the Kelvin terminal 6, the SiC MOSFET channel is turned on. At this time, a forward bias is applied between the drain terminal 4 and the source terminal 5, and the device is forward-conducted. During reverse freewheeling, since the conduction voltage drop of the SiC SBD is much smaller than the body diode of the SiC MOSFET, only the SiC SBD is turned on, and the body diode is suppressed. This reduces switching loss and freewheeling loss, avoids bipolar degradation, disperses heat loss, and improves the heat dissipation capacity of the device, which can meet high-power scene applications.

[0061] Exemplarily, the SiC MOSFET chip 2 and the SiC SBD chip 3 are attached to the upper surface of the copper frame 1 by means of an adhesive material 8 . The adhesive material 8 may be tin soldering to play a role in bonding the chips.

[0062] In one embodiment, the material of the bonding wire includes aluminum, copper or silver.

[0063] In one embodiment, the silicon carbide transistor discrete device further includes a heat dissipation copper sheet 9 and a ceramic gasket 10, such as Figure 6 shown.

[0064] The ceramic gasket 10 is located on the upper surface of the heat dissipation copper plate 9 ; the copper frame 1 is located on the upper surface of the ceramic gasket 10 .

[0065] For example, the heat dissipation copper sheet 9 is located at the bottom, which plays a supporting and heat dissipation role. The ceramic gasket 10 is located above the heat dissipation copper sheet 9, and the ceramic gasket 10 plays an insulating role. The two are bonded together by high-temperature solder sintering. The copper frame 1 is located above the ceramic gasket 9, and the two are also bonded together by high-temperature solder sintering.

[0066] This embodiment introduces a ceramic gasket into the device structure, which reduces the man-hours and costs of assembling the entire device, and the heat dissipation is further improved compared to a device without a ceramic gasket.

[0067] In one embodiment, a plastic packaging material 11 is also included, such as Figure 4-Figure 6 The plastic packaging material 11 is filled in the gap between the SiC MOSFET chip 2 and the SiC SBD chip 3 and around the gap, and the SiC MOSFET chip 2 and the SiC SBD chip 3 are wrapped.

[0068] Exemplarily, the molding compound 11 fills the gaps between the SiC MOSFET chip 2, the SiC SBD chip 3 and the bonding wires and wraps them. After curing, moisture isolation is formed to protect the device. The molding compound provides a physical barrier for the chip and the bonding wires, effectively preventing moisture, pollutants, dust, mechanical shock, chemical corrosion and other factors in the external environment from directly damaging the chip and the bonding wires.

[0069] Different application scenarios and needs have different requirements for the performance of plastic encapsulation materials. For example, the automotive electronics field has high requirements for the high temperature and high pressure resistance of plastic encapsulation materials; while the consumer electronics field pays more attention to the appearance, feel and other properties of plastic encapsulation materials. Therefore, when choosing plastic encapsulation materials, you need to choose the appropriate model according to your application scenarios and needs. Figure 5 As shown, the model of the plastic encapsulation material 11 may be EME-G720C, which has a higher glass transition temperature, so that the device can maintain stable performance at a higher temperature, which is particularly important for electronic devices that need to work under extreme temperature conditions. Figure 6 As shown, the model of the plastic packaging material 11 may be EME-E500HA, which has good insulation performance to prevent problems such as current leakage and short circuit.

[0070] In one embodiment, it further comprises an assembly hole 12. The assembly hole 12 is arranged on the upper surface of the copper frame 1 and is used for assembling components.

[0071] During the design, an assembly hole 12 is reserved to facilitate assembly with other devices when in use, or to facilitate assembly of additional devices on the silicon carbide transistor discrete device.

[0072] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0073] In the embodiment of the present application, there is a body diode inside the SiC MOSFET chip itself, and the performance needs to be improved by an external anti-parallel SiC SBD. The two chips are sealed by using an anti-parallel silicon carbide Schottky diode outside the SiC MOSFET chip 2. When a positive voltage is applied between the gate terminal 7 and the Kelvin terminal 6, the SiC MOSFET channel is turned on. At this time, a forward bias is applied between the drain terminal 4 and the source terminal 5, and the device is forward-conducted; during reverse flow, since the conduction voltage drop of the SiC SBD is much smaller than the body diode of the SiC MOSFET, only the SiC SBD is turned on, and the body diode is suppressed. This reduces switching loss and continuous flow loss, avoids bipolar degradation, disperses heat consumption, improves the heat dissipation capacity of the device, and can meet high-power scene applications. Heat dissipation is further increased by providing a copper frame 1, a heat dissipation copper sheet 9, and a ceramic gasket 10.

[0074] See also Figure 7 The present application embodiment provides a method for preparing a silicon carbide transistor discrete device, and the method comprises:

[0075] First, the SiC MOSFET chip 2 and the SiC SBD chip 3 are surface mounted on the upper surface of the metal copper frame 1 by using the patch process. Figure 7 As shown in (a) in the figure. Under a certain power consumption, since two chips disperse the heat at the same time, the heat dissipation area is large, the total thermal resistance is small, and the heat dissipation is good, which can meet the use of high-power scenarios.

[0076] Then, a bonding process is used to bond the source pad 21 and the gate pad 22 on the upper surface of the SiC MOSFET chip 2, and the anode pad 31 on the upper surface of the SiC SBD chip 3 to each terminal, so that the SiC MOSFET chip 2 and the SiC SBD chip 3 are connected in anti-parallel. Figure 7 As shown in (b) in the figure, by connecting the SBD in anti-parallel, the SiC MOSFET device's follow-on loss and switching loss are reduced, while the device cost is reduced.

[0077] Finally, the injection molding process is used to fill the plastic packaging material 11 between the SiC MOSFET chip 2, the SiC SBD chip 3 and the bonding wire, and then the plastic packaging material 11 is cured. Figure 7 As shown in (c) in the figure, after the plastic encapsulation material 11 is filled, it effectively prevents moisture, pollutants, dust, mechanical shock, chemical corrosion and other factors in the external environment from directly damaging the chip and the bonding wire, so that the device can maintain stable performance at a higher temperature while having good insulation performance.

[0078] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0079] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A silicon carbide transistor discrete device, characterized in that: include: Copper frame, SiC MOSFET chip, SiC SBD chip, drain terminal, source terminal, Kelvin terminal, gate terminal, source pad, gate pad and anode pad; The SiC MOSFET chip and the SiC SBD chip are arranged above the copper frame; the drain terminal, the source terminal, the Kelvin terminal and the gate terminal are arranged on the side of the copper frame; the upper surface of the drain terminal is flush with the upper surface of the copper frame and is connected to the copper frame; the upper surfaces of the source terminal, the Kelvin terminal and the gate terminal are all flush with the upper surface of the copper frame and are electrically isolated from the copper frame; The upper surface of the SiC MOSFET chip is provided with the source pad and the gate pad; the source pad includes a first source pad, a second source pad and a third source pad; The anode pad is disposed on the upper surface of the SiC SBD chip; The first source pad is connected to the anode pad, the second source pad is connected to the source terminal, the third source pad is connected to the Kelvin terminal, and the gate pad is connected to the gate terminal, so that the SiCMOSFET chip and the SiC SBD chip are connected in anti-parallel.

2. The silicon carbide transistor discrete device according to claim 1, characterized in that: The first source pad is connected to the anode pad via a double bonding wire; the second source pad is connected to the source terminal via a double bonding wire; the third source pad is connected to the Kelvin terminal via a single bonding wire; and the gate pad is connected to the gate terminal via a single bonding wire.

3. The silicon carbide transistor discrete device according to claim 1, characterized in that: The first source pad is connected to the anode pad via a single bonding wire; the second source pad is connected to the source terminal via a single bonding wire; the anode pad is connected to the source terminal via a single bonding wire; the third source pad is connected to the Kelvin terminal via a single bonding wire; and the gate pad is connected to the gate terminal via a single bonding wire.

4. The silicon carbide transistor discrete device according to claim 1, characterized in that: Also includes a bonding material; the bonding material is nano silver; The SiC MOSFET chip and the SiC SBD chip are attached to the upper surface of the copper frame through the adhesive material.

5. The silicon carbide transistor discrete device according to any one of claims 1 to 4, characterized in that: It also includes copper heat sinks and ceramic gaskets; The ceramic gasket is located on the upper surface of the heat dissipation copper sheet; The copper frame is located on the upper surface of the ceramic gasket.

6. The silicon carbide transistor discrete device according to any one of claims 1 to 4, characterized in that: Also includes plastic packaging materials; The plastic packaging material is filled in the gap between and around the SiC MOSFET chip and the SiC SBD chip to wrap the SiC MOSFET chip and the SiC SBD chip.

7. The silicon carbide transistor discrete device according to claim 2, characterized in that: The material of the bonding wire includes aluminum, copper or silver.

8. The silicon carbide transistor discrete device according to claim 1, characterized in that: The source pad further includes a fourth source pad; and the gate pad is disposed between the third source pad and the fourth source pad.

9. The silicon carbide transistor discrete device according to claim 1, characterized in that: Also includes mounting holes; The assembly holes are arranged on the upper surface of the copper frame and are used for assembling components.

10. A method for preparing a discrete silicon carbide transistor device, characterized in that: include: The SiC MOSFET chip and the SiC SBD chip are surface mounted on the upper surface of the metal copper frame using the patch process; Using a bonding process, bonding the source pad and the gate pad on the upper surface of the SiC MOSFET chip, and the anode pad and each terminal on the upper surface of the SiC SBD chip, so that the SiC MOSFET chip and the SiC SBD chip are connected in anti-parallel; The injection molding process is adopted to fill the molding compound between the SiC MOSFET chip, the SiC SBD chip and the bonding wire, and then the molding compound is cured.

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