Composite substrate and manufacturing method thereof
By setting the charge trapping region and grooves in the buried layer on the semiconductor substrate layer, the crosstalk problem in the radio frequency substrate is solved, the resistivity and mechanical strength are improved, and it is suitable for the manufacturing of semiconductor devices with high frequency and low loss.
Patent Information
- Application Number
- CN202310679445.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-08
- Publication Date
- 2024-12-10
AI Technical Summary
The crosstalk problem caused by parasitic circuits in the RF field is particularly large in the loss of semiconductor substrates, which is difficult to meet the stringent requirements of electrical properties.
A composite substrate structure is designed, including a support substrate layer, a patterned buried layer and a growth substrate layer, and a partially penetrated groove is provided in the buried layer, and the support substrate layer includes a charge trapping region, and the charge trapping region and groove are projected in a plane. The shapes overlap, and the resistivity is increased by setting a charge trapping region on the substrate layer, reducing the impact of crosstalk, and attenuating stress through the grooves in the buried layer, improving mechanical strength.
It has achieved the improvement of the resistivity and mechanical strength of semiconductor devices, reduced RF loss, and is suitable for the manufacturing of semiconductor devices with high frequency and low loss.
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Figure CN119108402A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor substrates, and in particular to a composite substrate and a method for manufacturing the same. Background Art
[0002] A typical substrate structure with an insulating buried layer in the prior art includes three layers, namely, a support layer, an insulating layer on the surface of the support layer, and a device layer on the surface of the insulating layer.
[0003] If the above substrate is used in the radio frequency field, more stringent requirements are placed on the electrical properties of the substrate. The transmission of radio frequency signals in the device layer will form a parasitic circuit in the support layer, and thus be subject to crosstalk from the support layer. Moreover, as the frequency increases, the effect of crosstalk becomes more and more obvious.
[0004] Therefore, it is necessary to provide a composite substrate and a method for manufacturing the same to increase the resistivity of the semiconductor structure and thereby reduce the crosstalk effect, so as to prepare a high-frequency, low-loss semiconductor device. Summary of the invention
[0005] In view of this, the embodiments of the present disclosure provide a composite substrate and a method for manufacturing the same to solve the technical problem of high-resistance SOI radio frequency loss in the prior art.
[0006] According to one aspect of the present disclosure, an embodiment of the present disclosure provides a composite substrate, including:
[0007] a supporting substrate layer;
[0008] A patterned buried layer located on the supporting substrate layer, the buried layer having a plurality of grooves arranged at intervals and at least partially penetrating the buried layer;
[0009] a growth substrate layer located on the buried layer;
[0010] Wherein, the supporting substrate layer comprises a charge trapping region, and the charge trapping region overlaps with the projection shape of the groove on the plane where the supporting substrate layer is located.
[0011] As an optional embodiment, the composite substrate further comprises:
[0012] A metal silicide layer wraps the upper and lower surfaces of the buried layer.
[0013] As an optional embodiment, the charge-trapping region contains doping ions, and the doping ion content of the charge-trapping region increases, decreases, or first increases and then decreases in a direction away from the growth substrate layer.
[0014] As an optional embodiment, in a direction perpendicular to the plane where the supporting substrate layer is located, the cross-sectional shape of the charge trapping region includes any one of a rectangular, a triangular, a trapezoidal and a water drop shape.
[0015] As an optional embodiment, the projection shape of the groove on the plane where the supporting substrate layer is located includes any one of a triangle, a circle, an ellipse, a polygon, a strip and a mesh.
[0016] As an optional embodiment, the number of the grooves per unit area gradually decreases from the center to the edge, or the projection area of the grooves on the plane where the supporting substrate layer is located gradually decreases from the center to the edge.
[0017] As an optional embodiment, the thickness of the charge trapping region is less than or equal to the thickness of the supporting substrate layer.
[0018] As an optional embodiment, the supporting substrate layer further comprises a substrate structure region wrapping the charge trapping region, the conductivity type of the substrate structure region is n-type or p-type, and the conductivity type of the charge trapping region is opposite to that of the substrate structure region.
[0019] As an optional embodiment, the charge trapping region is located inside the supporting substrate layer, and the substrate structure region wraps the upper and lower surfaces and side walls of the charge trapping region; or
[0020] The charge trapping region penetrates through the supporting substrate layer, and the substrate structure region wraps around the sidewall of the charge trapping region; or
[0021] The charge trapping region partially penetrates the supporting substrate layer, and the substrate structure region wraps the lower surface and sidewalls of the charge trapping region.
[0022] As an optional embodiment, the substrate structure region has a resistivity of at least 100 Ohm·cm
[0023] As an optional embodiment, the material of the substrate structure region includes high-resistance silicon.
[0024] As an optional embodiment, the supporting substrate layer has a resistivity of at least 1000 Ohm·cm.
[0025] As an optional embodiment, the material of the support substrate layer and the growth substrate layer includes silicon.
[0026] As an optional embodiment, the material of the buried layer includes at least one of silicon oxide, silicon nitride, silicon oxynitride and aluminum nitride.
[0027] According to another aspect of the present disclosure, an embodiment of the present disclosure provides a method for manufacturing a composite substrate, comprising the following steps:
[0028] S1, providing a supporting substrate layer;
[0029] S2, preparing a buried layer on the supporting substrate layer;
[0030] S3, patterning and etching the buried layer to form a groove that at least partially penetrates the buried layer;
[0031] S4, forming a charge trapping region in the supporting substrate layer below the groove, wherein the charge trapping region overlaps with a projection shape of the groove on the plane where the supporting substrate layer is located;
[0032] S5. Bonding a growth substrate layer on a side of the buried layer away from the supporting substrate layer.
[0033] As an optional embodiment, the method of forming the charge trapping region in the supporting substrate layer below the groove in step S4 is ion implantation, and the doping ion content, depth and thickness of the charge trapping region are controlled by controlling the energy of the ion implantation.
[0034] As an optional embodiment, the method for forming a charge trapping region in the supporting substrate layer below the groove in step S4 is that the groove penetrates the buried layer, the surface of the supporting substrate layer exposed by the groove is etched to prepare a pit, and the charge trapping region is epitaxially grown in the pit.
[0035] As an optional embodiment, the method of forming a charge trapping region in the supporting substrate layer below the groove in step S4 is that the groove penetrates the buried layer, fills the heavily doped semiconductor layer in the groove, forms the charge trapping region below the heavily doped semiconductor layer by diffusion, and then removes the heavily doped semiconductor layer.
[0036] The present disclosure provides a composite substrate and a manufacturing method thereof, wherein the composite substrate comprises a supporting substrate layer, a buried layer and a growth substrate layer which are stacked in sequence, wherein the buried layer has a groove which at least partially penetrates the buried layer, and the supporting substrate layer comprises a charge trapping region, wherein the charge trapping region overlaps with the projection shape of the groove on the plane where the supporting substrate layer is located. The composite substrate provided by the present disclosure provides a charge trapping region on the supporting substrate layer, and utilizes the charge trapping region to deplete the charge of the supporting substrate layer, thereby increasing the resistivity of the composite substrate and reducing the crosstalk effect, so as to prepare a high-frequency, low-loss semiconductor device; the groove is provided in the buried layer, so as to attenuate the stress transmitted from the growth substrate layer to the supporting substrate layer, so as to increase the mechanical strength of the composite substrate and avoid deformation in the subsequent epitaxial process. BRIEF DESCRIPTION OF THE DRAWINGS
[0037] Figure 1a to Figure 1b Shown is a schematic structural diagram of a composite substrate provided in one embodiment of the present disclosure.
[0038] Figure 2Shown is a schematic structural diagram of a composite substrate provided in one embodiment of the present disclosure.
[0039] Figure 3a to Figure 3c FIG. 1 is a schematic diagram showing the change of the doping ion content in the charge trapping region according to an embodiment of the present disclosure.
[0040] Figures 4a to 4c Shown is a schematic structural diagram of a composite substrate provided in one embodiment of the present disclosure.
[0041] Figure 5a to Figure 5c Shown is a schematic structural diagram of a composite substrate provided in one embodiment of the present disclosure.
[0042] Figure 6a to Figure 6b FIG. 1 is a top view of a buried layer according to an embodiment of the present disclosure.
[0043] Figure 7 Shown is a schematic flow chart of a composite substrate manufacturing method provided in one embodiment of the present disclosure.
[0044] Figures 8 to 13 Shown is a schematic structural diagram of a composite substrate intermediate structure provided in one embodiment of the present disclosure. DETAILED DESCRIPTION
[0045] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.
[0046] In order to solve the technical problem of high-resistance SOI radio frequency loss in the prior art, the present disclosure provides a composite substrate and a manufacturing method thereof, wherein the composite substrate comprises a supporting substrate layer, a buried layer and a growth substrate layer which are stacked in sequence, the buried layer having a groove which at least partially penetrates the buried layer, and the supporting substrate layer comprises a charge trapping region, and the projection shape of the charge trapping region and the groove on the plane where the supporting substrate layer is located overlap. The composite substrate provided by the present disclosure arranges a charge trapping region on the supporting substrate layer, utilizes the charge trapping region to deplete the charge of the supporting substrate layer, improves the resistivity of the composite substrate, reduces the crosstalk effect, and prepares a high-frequency, low-loss semiconductor device; the groove is arranged in the buried layer, which can attenuate the stress transmitted from the growth substrate layer to the supporting substrate layer, so as to improve the mechanical strength of the composite substrate and avoid deformation in the subsequent epitaxial process.
[0047] Below is a combination of Figures 1 to Fig.13 The composite substrate and the method for manufacturing the composite substrate mentioned in the present disclosure are further illustrated.
[0048] Figure 1a to Figure 1bThe composite substrate provided by one embodiment of the present disclosure is shown as a schematic diagram of the structure. The composite substrate comprises: a supporting substrate layer 10; a patterned buried layer 20 located on the supporting substrate layer 10, wherein the buried layer 20 has a plurality of grooves 21 arranged at intervals and at least partially penetrating the buried layer 20; a growth substrate layer 30 located on the buried layer 20; wherein the supporting substrate layer 10 comprises a charge trapping region 12, and the projection shape of the charge trapping region 12 and the groove 21 on the plane where the supporting substrate layer 10 is located overlaps. The groove 21 may completely penetrate the buried layer 20, such as Figure 1a The groove 21 may also partially penetrate the buried layer 20, such as Figure 1b shown.
[0049] In one embodiment, Figure 2 FIG. 1 is a schematic diagram of the structure of a composite substrate provided by an embodiment of the present disclosure. Figure 2 As shown, the composite substrate further includes a metal silicide layer 13 wrapping the upper and lower surfaces of the buried layer 20. The interface state at the interface between silicon and silicon dioxide will introduce mobile charges, causing radio frequency loss at high frequencies. The buried layer 20 is wrapped with the metal silicide layer 13, thereby avoiding radio frequency loss caused by the interface state between the buried layer 20 and the growth substrate layer 30, and between the buried layer 20 and the supporting substrate layer 10.
[0050] In one embodiment, the supporting substrate layer 10 further includes a substrate structure region 11 encapsulating a charge trapping region 12. The material of the substrate structure region 11 includes high-resistance silicon. The conductivity type of the substrate structure region 11 is n-type or p-type. The conductivity type of the charge trapping region 12 is opposite to that of the substrate structure region 11. A depletion layer is formed by using the charge trapping region 12 and the substrate structure region 11 of opposite conductivity types to deplete the charge of the supporting substrate layer 10, thereby increasing the resistivity of the supporting substrate layer 10. The substrate structure region 11 has a resistivity of at least 100 Ohm·cm. The depletion layer is designed so that the supporting substrate layer 10 has a resistivity of at least 1000 Ohm·cm.
[0051] In one embodiment, Figure 3a to Figure 3c FIG. 1 is a schematic diagram showing a change in the doping ion content of the charge trapping region according to an embodiment of the present disclosure. The charge trapping region 12 contains doping ions, and the doping ion content of the charge trapping region 12 increases in a direction away from the growth substrate layer 30 (e.g. Figure 3a As shown), decreasing (as Figure 3b as shown) or increase first and then decrease (as shown Figure 3c By designing the doping ion content of the charge trapping region 12 and improving the charge distribution of the charge trapping region 12, the isolation effect of the depletion layer can be further improved to increase the resistivity of the composite substrate.
[0052] In one embodiment, Figures 4a to 4cFIG. 1 is a schematic diagram of the structure of a composite substrate provided by an embodiment of the present disclosure. The thickness of the charge trapping region 12 is less than or equal to the thickness of the supporting substrate layer 10. When the thickness of the charge trapping region 12 is less than the thickness of the supporting substrate layer 10, the charge trapping region 12 is located inside the supporting substrate layer 10, and the substrate structure region 11 wraps the upper and lower surfaces and side walls of the charge trapping region 12 (such as Figure 4a As shown), or the charge trapping region 12 partially penetrates the supporting substrate layer 10, and the substrate structure region 11 wraps the lower surface and sidewall of the charge trapping region 12 (as shown in FIG. Figure 4b When the thickness of the charge trapping region 12 is equal to the thickness of the supporting substrate layer 10, the charge trapping region 12 penetrates the supporting substrate layer 10, and the substrate structure region 11 wraps the sidewall of the charge trapping region 12 (as shown in FIG. Figure 4c When the charge trapping region 12 is located inside the supporting substrate layer 10, the crystal quality on the surface of the supporting substrate layer 10 is better, which is conducive to the growth of the subsequent epitaxial layer; when the charge trapping region 12 penetrates the supporting substrate layer 10, the charge of the supporting substrate layer 10 is more thoroughly depleted, further improving the resistivity of the composite substrate.
[0053] In one embodiment, Figure 5a to Figure 5c FIG. 1 is a schematic diagram of the structure of a composite substrate provided by an embodiment of the present disclosure. In a direction perpendicular to the plane where the supporting substrate layer 10 is located, the cross-sectional shape of the charge trapping region 12 includes any one of a rectangular, a triangular, a trapezoidal, and a water drop shape. The cross-sectional shape of the charge trapping region 12 can be a rectangular (e.g. Figure 4c As shown), triangle (as Figure 5a As shown), trapezoidal (as Figure 5b as shown) or teardrop-shaped (as Figure 5c As shown in FIG. 1 , the present disclosure does not impose any specific limitation on the cross-sectional shape of the charge trapping region 12 .
[0054] In one embodiment, the projection shape of the groove 21 penetrating the buried layer 20 on the plane where the supporting substrate layer 10 is located includes any one of a triangle, a circle, an ellipse, a polygon, a strip and a mesh. The charge trapping region 12 overlaps with the projection shape of the groove 21 on the plane where the supporting substrate layer 10 is located. By controlling the shape of the groove 21 and the shape of the charge trapping region 12, the charge trapping region 12 is evenly distributed in the supporting substrate layer 10, and the charge of the supporting substrate layer 10 is evenly depleted, thereby improving the resistivity of the composite substrate. The groove 21 set in the buried layer 20 can also attenuate the stress transmitted from the growth substrate layer 30 to the supporting substrate layer 10, so as to improve the mechanical strength of the composite substrate and avoid deformation during the subsequent epitaxial process.
[0055] In one embodiment, Figure 6a to Figure 6b FIG. 2 is a top view of a buried layer according to an embodiment of the present disclosure. The number of grooves 21 penetrating the buried layer 20 decreases gradually from the center to the edge per unit area (eg, Figure 6aAlternatively, the projection area of the groove 21 penetrating the buried layer 20 on the plane where the supporting substrate layer 10 is located gradually decreases from the center to the edge (as shown in FIG. Figure 6b As shown). By designing the number or size of the grooves 21, on the one hand, the stress distribution of the composite substrate can be adjusted to improve the mechanical strength of the composite substrate, and on the other hand, the number or size of the charge trapping region 12 can be adjusted, thereby improving the charge distribution of the charge trapping region 12 in the support substrate layer 10, further improving the charge depletion effect, and improving the resistivity of the composite substrate. In one embodiment, the material of the support substrate layer 10 and the growth substrate layer 30 includes silicon. The support substrate layer 10 has a (111) crystal orientation or a (100) crystal orientation, and the growth substrate layer 30 has a (111) crystal orientation. The growth substrate 30 is used for the subsequent growth of an epitaxial layer to make a semiconductor structure. The (111) crystal plane of single crystal silicon is more conducive to the epitaxial growth of the epitaxial structure layer of the III-V compound material.
[0056] In one embodiment, the material of the buried layer 20 includes at least one of silicon oxide, silicon nitride, silicon oxynitride and aluminum nitride. The material of the buried layer 20 is a polar material, which refers to a material with polar bonds inside the material, such as metal oxide / nitride, non-metal oxide / nitride and compound semiconductor. The polar bonds in the polar material are exposed on the surface and used for bonding, which is conducive to forming a more solid bonding interface. The material of the buried layer 20 is selected from at least one of silicon oxide, silicon nitride, silicon oxynitride and aluminum nitride. The above materials are both common insulating materials and common polar materials, taking into account both insulating properties and bonding properties, and are therefore preferred materials.
[0057] An embodiment of the present disclosure also provides a method for manufacturing a composite substrate. Figure 7 FIG. 1 is a schematic diagram of a process for manufacturing a composite substrate provided by an embodiment of the present disclosure. Figures 8 to 13 FIG. 1 is a schematic diagram of a composite substrate intermediate structure provided by an embodiment of the present disclosure. Figure 7 As shown, the manufacturing method includes:
[0058] Step S1: Figure 8 As shown, a supporting substrate layer 10 is provided. The material of the supporting substrate 10 includes silicon. The supporting substrate layer 10 has a (111) crystal orientation or a (100) crystal orientation.
[0059] Step S2: Fig. 9As shown, a buried layer 20 is prepared on the supporting substrate layer 10. The material of the buried layer 20 includes at least one of silicon oxide, silicon nitride, silicon oxynitride and aluminum nitride. The preparation method of the buried layer 20 includes thermal oxidation or low-pressure chemical deposition. When the material of the buried layer 20 is silicon dioxide, the supporting substrate layer 10 can be treated by thermal oxidation to form the buried layer 20 on the upper surface of the supporting substrate layer 10. The buried layer 20 can also be formed on the supporting substrate layer 10 by low-pressure chemical deposition. The buried layer 20 is made of silicon oxide, silicon nitride, silicon oxynitride or aluminum nitride.
[0060] In one embodiment, metal may be deposited before and after step S2 to wrap the upper and lower surfaces of the buried layer 20, and a metal silicide layer 13 wrapping the buried layer 20 is formed after annealing to solve the RF loss problem caused by the interface state between silicon and silicon dioxide.
[0061] Step S3: Fig.10 As shown, the buried layer 20 is patterned and etched to form a groove 21 that penetrates the buried layer 20. The groove 21 may also partially penetrate the buried layer 20. The projection shape of the groove 21 on the plane where the supporting substrate layer 10 is located includes any one of a triangle, a circle, an ellipse, a polygon, a strip, and a mesh.
[0062] Step S4: Fig.11 As shown, a charge trapping region 12 is formed in the supporting substrate layer 10 below the groove 21, and the charge trapping region 12 overlaps with the projection shape of the groove 21 on the plane where the supporting substrate layer 10 is located, and the supporting substrate layer 10 also includes a substrate structure region 11 that wraps the charge trapping region 12. The charge trapping region 12 overlaps with the projection shape of the groove 21 on the plane where the supporting substrate layer 10 is located. The conductivity type of the substrate structure region 11 is n-type or p-type, and the conductivity type of the charge trapping region 12 is opposite to the conductivity type of the substrate structure region 11.
[0063] In one embodiment, the method of forming the charge trapping region 12 in the supporting substrate layer 10 below the groove 21 in step S4 is ion implantation, and the doping ion content, depth and thickness of the charge trapping region 12 are controlled by controlling the energy of the ion implantation. The doping ion content of the charge trapping region 12 can be controlled to increase in a direction away from the growth substrate layer 30 (e.g., Figure 3a ), decreasing (such as Figure 3b ) or increase first and then decrease (such as Figure 3c). By designing the doping ion content of the charge trapping region 12 and improving the charge distribution of the charge trapping region 12, the isolation effect of the depletion layer can be further improved to increase the resistivity of the composite substrate. The depth and thickness of the charge trapping region 12 can also be controlled by controlling the energy of the ion injection. The thickness of the charge trapping region 12 is less than or equal to the thickness of the supporting substrate layer 10. When the thickness of the charge trapping region 12 is less than the thickness of the supporting substrate layer 10, the charge trapping region 12 is located inside the supporting substrate layer 10, and the substrate structure region 11 wraps the upper and lower surfaces and side walls of the charge trapping region 12 (such as Figure 4a As shown), or the charge trapping region 12 partially penetrates the supporting substrate layer 10, and the substrate structure region 11 wraps the lower surface and sidewall of the charge trapping region 12 (as shown in FIG. Figure 4b When the thickness of the charge trapping region 12 is equal to the thickness of the supporting substrate layer 10, the charge trapping region 12 penetrates the supporting substrate layer 10, and the substrate structure region 11 wraps the sidewall of the charge trapping region 12 (as shown in FIG. Figure 4c As shown). When the charge trapping region 12 is located inside the supporting substrate layer 10, the crystal quality of the surface of the supporting substrate layer 10 is good, which is conducive to the growth of the subsequent epitaxial layer; when the charge trapping region 12 penetrates the supporting substrate layer 10, the charge of the supporting substrate layer 10 is more thoroughly depleted, further improving the resistivity of the composite substrate. The patterned buried layer 20 can be directly used as a mask for ion implantation, and the projection shape of the charge trapping region 12 formed by ion implantation is controlled to be the same as that of the groove 21, without the need to make an additional mask layer, which simplifies the process and saves costs.
[0064] In another embodiment, the method for forming the charge trapping region 12 in the supporting substrate layer 10 below the groove 21 in step S4 may be that the groove 21 penetrates the buried layer 20, the surface of the supporting substrate layer 10 exposed by the groove 21 is etched to prepare a pit, and the charge trapping region 12 is epitaxially grown in the pit; the method for forming the charge trapping region 12 in the supporting substrate layer 10 below the groove 21 in step S4 may also be that the groove 21 penetrates the buried layer 20, the heavily doped semiconductor layer 22 is filled in the groove 21, and the charge trapping region 12 (such as Fig.12 The heavily doped semiconductor layer 22 is removed after the heavily doped semiconductor layer 22 is removed. The conductivity type of the heavily doped semiconductor layer 22 is opposite to the conductivity type of the substrate structure region 11. The diffusion effect of the heavily doped semiconductor layer 22, such as Al metal diffusion, is used to reverse the conductivity type of the supporting substrate layer 10 to form a charge trapping region 12. The charge trapping region 12 can form a depletion PN junction with the substrate structure region 11. The present disclosure does not specifically limit the method for forming the charge trapping region 12.
[0065] In one embodiment, the shape of the charge trapping region 12 can be controlled by controlling the shape of the groove 21. In a direction perpendicular to the plane where the supporting substrate layer 10 is located, the cross-sectional shape of the charge trapping region 12 can be a rectangle (eg Figure 4c As shown), triangle (as Figure 5a As shown), trapezoidal (as Figure 5b as shown) or teardrop-shaped (as Figure 5c As shown in FIG. 1 , the present disclosure does not impose any specific limitation on the cross-sectional shape of the charge trapping region 12 .
[0066] In one embodiment, the number and size of the charge trapping regions 12 can be controlled by controlling the number and size of the grooves 21. In a unit area, the number of grooves 21 penetrating the buried layer 20 decreases gradually from the center to the edge (e.g. Figure 6a Alternatively, the projection area of the groove 21 penetrating the buried layer 20 on the plane where the supporting substrate layer 10 is located gradually decreases from the center to the edge (as shown in FIG. Figure 6b By designing the number or size of the grooves 21, on the one hand, the stress distribution of the composite substrate can be adjusted to improve the mechanical strength of the composite substrate, and on the other hand, the number or size of the charge trapping regions 12 can be adjusted to improve the charge distribution of the charge trapping regions 12 in the supporting substrate layer 10, further improve the charge depletion effect, and thus improve the resistivity of the composite substrate.
[0067] Step S5: Fig.13 As shown, a growth substrate layer 30 is bonded to the side of the buried layer 20 away from the supporting substrate layer 10. The material of the growth substrate layer 30 includes silicon. The growth substrate layer 30 has a (111) crystal orientation. The growth substrate 30 is used to subsequently grow an epitaxial layer to make a semiconductor structure. The (111) crystal plane of single crystal silicon is more conducive to the epitaxial growth of the epitaxial structure layer of the III-V compound material.
[0068] The present disclosure provides a composite substrate and a manufacturing method thereof, wherein the composite substrate comprises a supporting substrate layer, a buried layer and a growth substrate layer which are stacked in sequence, wherein the buried layer has a groove which at least partially penetrates the buried layer, and the supporting substrate layer comprises a charge trapping region, wherein the charge trapping region overlaps with the projection shape of the groove on the plane where the supporting substrate layer is located. The composite substrate provided by the present disclosure provides a charge trapping region on the supporting substrate layer, and utilizes the charge trapping region to deplete the charge of the supporting structure layer, thereby increasing the resistivity of the composite substrate and reducing the crosstalk effect, so as to prepare a high-frequency, low-loss semiconductor device; the groove is provided in the buried layer, so as to attenuate the stress transmitted from the growth substrate layer to the supporting substrate layer, so as to increase the mechanical strength of the composite substrate and avoid deformation in the subsequent epitaxial process.
[0069] It should be understood that the term "including" and its variations used in the present disclosure are open inclusions, that is, "including but not limited to". The term "one embodiment" means "at least one embodiment". In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification and the features of different embodiments or examples, unless they are contradictory.
[0070] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.
Claims
1. A composite substrate, characterized in that: include: A supporting substrate layer (10); A patterned buried layer (20) located on the supporting substrate layer (10), the buried layer (20) having a plurality of grooves (21) arranged at intervals and at least partially penetrating the buried layer (20); a growth substrate layer (30) located on the buried layer (20); The supporting substrate layer (10) comprises a charge trapping region (12), and the projected shapes of the charge trapping region (12) and the groove (21) on the plane where the supporting substrate layer (10) is located overlap.
2. The composite substrate according to claim 1, characterized in that The composite substrate further comprises: A metal silicide layer (13) wrapping the upper and lower surfaces of the buried layer (20).
3. The composite substrate according to claim 1, characterized in that The charge trapping region (12) contains doped ions, and the doped ion content of the charge trapping region (12) increases, decreases, or first increases and then decreases in a direction away from the growth substrate layer (30).
4. The composite substrate according to claim 1, characterized in that In a direction perpendicular to the plane where the supporting substrate layer (10) is located, the cross-sectional shape of the charge trapping region (12) includes any one of a rectangular, a triangular, a trapezoidal and a water drop shape.
5. The composite substrate according to claim 1, characterized in that The projection shape of the groove (21) on the plane where the supporting substrate layer (10) is located includes any one of a triangle, a circle, an ellipse, a polygon, a long strip and a mesh.
6. The composite substrate according to claim 1, characterized in that The number of the grooves (21) per unit area gradually decreases from the center to the edge, or the projection area of the grooves (21) on the plane where the supporting substrate layer (10) is located gradually decreases from the center to the edge.
7. The composite substrate according to claim 1, characterized in that The thickness of the charge trapping region (12) is less than or equal to the thickness of the supporting substrate layer (10).
8. The composite substrate according to claim 1, characterized in that The supporting substrate layer (10) further comprises a substrate structure region (11) encapsulating the charge trapping region (12); the conductivity type of the substrate structure region (11) is n-type or p-type; the conductivity type of the charge trapping region (12) is opposite to the conductivity type of the substrate structure region (11).
9. The composite substrate according to claim 8, characterized in that The charge trapping region (12) is located inside the supporting substrate layer (10), and the substrate structure region (11) wraps the upper and lower surfaces and side walls of the charge trapping region (12); or The charge trapping region (12) penetrates the supporting substrate layer (10), and the substrate structure region (11) wraps around the side wall of the charge trapping region (12); or The charge trapping region (12) partially penetrates the supporting substrate layer (10), and the substrate structure region (11) wraps the lower surface and side walls of the charge trapping region (12).
10. The composite substrate according to claim 8, characterized in that The substrate structure region (11) has a resistivity of at least 100 Ohm·cm.
11. The composite substrate according to claim 8, characterized in that The material of the substrate structure region (11) includes high-resistance silicon.
12. The composite substrate according to claim 1, characterized in that The supporting substrate layer (10) has a resistivity of at least 1000 Ohm·cm.
13. The composite substrate according to claim 1, characterized in that The materials of the supporting substrate layer (10) and the growth substrate layer (30) include silicon.
14. The composite substrate according to claim 1, characterized in that The material of the buried layer (20) includes at least one of silicon oxide, silicon nitride, silicon oxynitride and aluminum nitride.
15. A method for manufacturing a composite substrate, characterized in that: The following steps are involved: S1. providing a supporting substrate layer (10); S2, preparing a buried layer (20) on the supporting substrate layer (10); S3, pattern-etching the buried layer (20) to form a groove (21) that at least partially penetrates the buried layer (20); S4, forming a charge trapping region (12) in the supporting substrate layer (10) below the groove (21), wherein the charge trapping region (12) overlaps with a projection shape of the groove (21) on the plane where the supporting substrate layer (10) is located; S5. Bonding a growth substrate layer (30) to a side of the buried layer (20) away from the supporting substrate layer (10).
16. The method for manufacturing a composite substrate according to claim 15, characterized in that: The method for forming the charge trapping region (12) in the supporting substrate layer (10) below the groove (21) in step S4 is ion implantation, and the doping ion content, depth and thickness of the charge trapping region (12) are controlled by controlling the energy of the ion implantation.
17. The method for manufacturing a composite substrate according to claim 15, characterized in that: The method for forming the charge trapping region (12) in the supporting substrate layer (10) below the groove (21) in step S4 is that the groove (21) penetrates the buried layer (20), the surface of the supporting substrate layer (10) exposed by the groove (21) is etched to prepare a pit, and the charge trapping region (12) is epitaxially grown in the pit.
18. The method for manufacturing a composite substrate according to claim 15, characterized in that: The method for forming the charge trapping region (12) in the supporting substrate layer (10) below the groove (21) in step S4 is that the groove (21) penetrates the buried layer (20), a heavily doped semiconductor layer (22) is filled in the groove (21), the charge trapping region (12) is formed below the heavily doped semiconductor layer (22) by diffusion, and then the heavily doped semiconductor layer (22) is removed.