Serial data receiving method, communication baud rate detection module and asynchronous transceiving transmitter

Abstract

The invention discloses a serial data receiving method, a communication baud rate detection module and an asynchronous transceiving transmitter. The serial data receiving method comprises the following steps: acquiring a starting moment of a synchronization frame; sequentially receiving N byte segments of the synchronization frame, and obtaining a data transmission baud rate according to the duration from the specific edge of the N byte segments to the starting moment; and receiving the data frame based on the data transmission baud rate. Wherein the step of sequentially receiving the N byte segments and obtaining the data transmission baud rate according to the specific edges of the N byte segments and the starting moment comprises the following steps: calculating the ith baud rate based on the duration from the specific edge of the byte segment in the ith time sequence to the starting moment, and carrying out baud rate calibration on the ith baud rate based on the data change of the byte segment in the (i + 1) th time sequence; and determining the (N-1) Baud rate as the data transmission Baud rate after the calibration result meets the set requirement. According to the serial data receiving method, the error rate caused by clock skew can be effectively reduced, and the data transmission precision is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of data communication, and in particular to a serial data receiving method, a communication baud rate detection module and an asynchronous receiving and transmitting transmitter. Background Art

[0002] UART (Universal Asynchronous Receiver / Transmitter) is a serial communication protocol widely used in computers and embedded systems. The UART protocol transmits data between two devices through serial communication, usually including a transmitter and a receiver. One of the core parameters of UART communication is the baud rate, which is the number of bits transmitted per second. In order to ensure the accuracy of data transmission, the sender and the receiver must use the same baud rate. However, in actual applications, due to hardware differences, environmental factors, etc., the baud rates of the sender and the receiver may deviate, resulting in unstable or even failed communication.

[0003] Traditional UART communication methods usually rely on a pre-set fixed baud rate, which is prone to data loss or errors when the baud rate is not matched accurately. In addition, as the communication environment changes, the fixed baud rate setting may not be able to adapt to the new communication conditions, further affecting the stability of communication. Therefore, how to achieve baud rate calibration and ensure the stability of UART communication has become an urgent problem to be solved.

[0004] In the prior art, there are some methods that attempt to solve the baud rate matching problem. For example, by using a high-precision clock source to reduce the baud rate deviation, or dynamically adjusting the baud rate during the communication process. However, these methods usually require additional hardware support or complex algorithm implementation, which increases the cost and complexity of the system. Summary of the invention

[0005] In order to solve the above technical problems, the present invention provides a serial data receiving method, a communication baud rate detection module and an asynchronous transceiver transmitter, which have a higher tolerance for quantization errors of received data and can improve the accuracy and stability of data transmission.

[0006] According to one aspect of the present invention, a serial data receiving method is provided, wherein the serial data is composed of a synchronization frame and a data frame, wherein the synchronization frame includes N byte segments, N is a non-zero natural number, and the serial data receiving method includes: obtaining the start time of the synchronization frame; receiving the N byte segments of the synchronization frame in sequence, and obtaining a data transmission baud rate according to a duration from a specific edge of the N byte segments to the start time; receiving the data frame based on the data transmission baud rate, wherein the sequentially receiving the N byte segments and obtaining the data transmission baud rate according to the specific edge of the N byte segments and the start time includes: calculating an i-th baud rate based on a duration from the specific edge of a byte segment of an i-th timing sequence to the start time, and performing baud rate calibration on the i-th baud rate based on data changes of a byte segment of an i+1-th timing sequence, i being a non-zero natural number less than N; and determining the N-1-th baud rate as the data transmission baud rate after the calibration result meets the set requirements.

[0007] Optionally, the baud rate calibration for the i-th baud rate based on the data change of the byte segment of the i+1th timing sequence includes: receiving the data of the byte segment of the i+1th timing sequence based on the i-th baud rate; comparing the obtained data of the byte segment of the i+1th timing sequence with the agreed data, if the two are the same, continuing to receive subsequent data, if the two are different, discarding the entire data packet.

[0008] Optionally, the duration from the specific edge of the byte segment of the i-th timing sequence to the start time is obtained by a baud rate count value generated by an uninterrupted counter, and the uninterrupted counter is used to start uninterrupted counting when the start time is detected, and output a baud rate count value each time a specific edge is detected. The serial data receiving method further includes: using an edge counter to count the number of the specific edges to obtain an edge count value, wherein the i-th baud rate is calculated using the following formula:

[0009] Among them, Bri is the i-th baud rate, A i is the baud rate count value, and Q is the edge count value.

[0010] Optionally, the start time is the starting edge of the byte segment of the 1st timing sequence, and the specific edge is the ending edge of the byte segment from the 1st timing sequence to the N-1th timing sequence, wherein the preset character of the synchronization frame is 0xAA, the starting edge of the byte segment of the 1st timing sequence is the falling edge from the high level to the low level, and the ending edge of the byte segment from the 1st timing sequence to the N-1th timing sequence is the rising edge from the low level to the high level.

[0011] Optionally, each of the N byte segments includes 2 bits of data, the agreed data corresponding to the byte segments from the 2nd timing sequence to the N-1th timing sequence is "10", and the agreed data corresponding to the byte segment of the Nth timing sequence is "11".

[0012] According to another aspect of the present invention, there is provided a communication baud rate detection module for an asynchronous receiving and transmitting transmitter, comprising: a baud rate detection logic unit, for obtaining the start time of a synchronization frame, and receiving N byte segments of the synchronization frame in sequence, and obtaining multiple baud rates according to the duration from a specific edge of the N byte segments to the start time; a microcontroller, for setting the data transmission baud rate according to the multiple baud rates, and receiving the data frame based on the data transmission baud rate; wherein the baud rate detection logic unit is used to calculate the i-th baud rate based on the duration from the specific edge of the byte segment of the i-th timing sequence to the start time in the process of obtaining multiple baud rates according to the duration from the specific edge of the N byte segments to the start time, i being a non-zero natural number less than N, and the communication baud rate detection module further comprises: a synchronization frame data detection logic unit, for performing baud rate calibration on the i-th baud rate based on the data change of the byte segment of the i+1th timing sequence, and controlling the microcontroller to determine the N-1th baud rate as the data transmission baud rate after the calibration result meets the set requirements.

[0013] Optionally, the baud rate detection logic unit includes: an uninterrupted counter, used to start uninterrupted counting when the start time is detected, and output a baud rate count value each time a specific edge is detected, wherein the baud rate count value corresponds to the duration from the specific edge of the corresponding byte segment to the start time; an edge counter, used to count the number of the specific edges to obtain an edge count value; and a baud rate calculation module, used to calculate the multiple baud rates according to the baud rate count value and the edge count value, wherein the baud rate calculation module uses the following formula to calculate the i-th baud rate corresponding to the byte segment of the i-th timing sequence:

[0014] Among them, Bri is the i-th baud rate, A i is the baud rate count value, and Q is the edge count value.

[0015] Optionally, the synchronization frame data detection logic unit is used to perform the following operations during the baud rate calibration of the i-th baud rate based on the data change of the byte segment of the i+1th timing sequence: compare the data of the byte segment of the i+1th timing sequence received based on the i-th baud rate with the agreed data; if the two are the same, continue to receive subsequent data; if the two are different, the output calibration result does not meet the set requirements and the entire data packet is discarded.

[0016] Optionally, the start time is the starting edge of the byte segment of the 1st timing sequence, and the specific edge is the ending edge of the byte segment from the 1st timing sequence to the N-1th timing sequence, wherein the preset character of the synchronization frame is 0xAA, the starting edge of the byte segment of the 1st timing sequence is the falling edge from the high level to the low level, and the ending edge of the byte segment from the 1st timing sequence to the N-1th timing sequence is the rising edge from the low level to the high level.

[0017] Optionally, each of the N byte segments includes 2 bits of data, the agreed data corresponding to the byte segments from the 2nd timing sequence to the N-1th timing sequence is "10", and the agreed data corresponding to the byte segment of the Nth timing sequence is "11".

[0018] Optionally, the communication baud rate detection module also includes: a baud rate data register, used to store multiple baud rates output by the baud rate detection logic unit, so that the microcontroller can read and set the data transmission baud rate; a synchronization frame data cache register, used to cache the data of the synchronization frame, so that the synchronization frame data detection logic unit can read; and a baud rate detection control unit, used to control the operating state of the baud rate detection logic unit according to the detection result output by the synchronization frame data detection logic unit, wherein the baud rate detection control unit is used to shut down the baud rate detection logic unit when the calibration result output by the synchronization frame data detection logic unit does not meet the set requirements.

[0019] According to another aspect of the present invention, an asynchronous receiving / transmitting transmitter is provided, comprising: an asynchronous receiving / transmitting module for converting received serial data into parallel data; and the above-mentioned communication baud rate detection module, wherein the communication baud rate detection module is used to control the data transmission rate of the asynchronous receiving / transmitting module.

[0020] In summary, the serial data receiving method for a UART device of an embodiment of the present invention obtains multiple baud rates according to the duration from a specific edge of multiple byte segments in a synchronization frame to the start time, and then calibrates the data transmission baud rate multiple times according to the multiple baud rates, and verifies the data of the specific byte segment during the calibration, which can effectively reduce the bit error rate caused by clock deviation and improve the accuracy and stability of data transmission. In addition, the data receiving method of an embodiment of the present invention has a higher tolerance for the quantization error of the received data and lower requirements for the communication hardware, so that the receiving end can better adapt to the baud rate of the sending end and improve the compatibility between different devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings.

[0022] Figure 1 A schematic structural diagram of a UART device with a baud rate detection and setting function according to a first embodiment of the present invention is shown.

[0023] Figure 2 A schematic diagram showing a synchronization frame of a UART serial communication protocol according to a first embodiment of the present invention.

[0024] Figure 3 A schematic diagram showing the structure of a baud rate detection logic unit in a UART device according to a first embodiment of the present invention is shown.

[0025] Figure 4 FIG. 4 is a flow chart of a serial data receiving method according to a second embodiment of the present invention.

[0026] Figure 5 Show Figure 4 Specific flow chart of step S302 in FIG. DETAILED DESCRIPTION

[0027] Reference will now be made in detail to the exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings.Where possible, the same reference numerals will be used throughout the drawings to refer to the same or like parts.

[0028] In the specification, it should be noted that similar reference numerals that have been used to represent similar parts in other drawings are used for these elements as much as possible. In the following description, when functions and configurations known to those skilled in the art are not related to the basic configuration of the present disclosure, their detailed description will be omitted. The terms described in the specification should be understood as follows.

[0029] The advantages and features of the present disclosure and their implementation methods will be described through the following embodiments described with reference to the accompanying drawings. However, the present disclosure can be implemented in different forms and should not be interpreted as being limited to the embodiments described herein. Rather, these embodiments are provided to make the present disclosure comprehensive and complete, so as to fully convey the scope of the present disclosure to those skilled in the art. In addition, the present disclosure is limited only by the scope of the claims.

[0030] The shapes, sizes, ratios, angles, and quantities disclosed in the drawings used to describe the embodiments of the present disclosure are merely examples, and the present disclosure is therefore not limited to the illustrated details. Similar reference numerals always represent similar elements. In the following description, when it is determined that a detailed description of a related known function or construction will inevitably obscure the focus of the present disclosure, the detailed description will be omitted.

[0031] As those skilled in the art can fully understand, the features of the various embodiments of the present disclosure can be partially or completely combined or combined with each other, and can interoperate and technically drive each other in various ways. The embodiments of the present disclosure can be performed independently of each other, or can be performed together in a mutually dependent relationship.

[0032] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0033] Figure 1 FIG. 2 is a schematic diagram showing the structure of a UART device with a baud rate detection setting function according to a first embodiment of the present invention. Figure 1 As shown, the UART device 100 of this embodiment includes a programmable logic device (PLD) 101 and a microcontroller unit (MCU) 102. The programmable logic device 101 is implemented by, for example, CHIP (universal integrated circuit), CPLD (Complex Programmable Logic Device) or FPGA (Field-Programmable Gate Array). A universal asynchronous receiving / transmitting module 110 and a communication baud rate detection module 120 are configured in the programmable logic device 101. The asynchronous receiving / transmitting module 110 is used to convert the serial data received from the external communication device 200 into parallel data and send it to the MCU 102, or convert the parallel data from the MCU 102 into serial data and send it to the external communication device 200, and the communication baud rate detection module 120 is used to realize the real-time configuration of the communication baud rate according to the serial data from the receiving end, so as to control the data transmission rate between the programmable logic device 101 and the external communication device 200.

[0034] Furthermore, the asynchronous receiving / transmitting module 110 includes a receiving / transmitting control register 111, a receiving / transmitting data register 112 and a receiving / transmitting logic controller 113. The receiving / transmitting control register 111 performs read and write control on the data bits in the register through the MCU 102, and is used to control whether the receiving / transmitting logic controller 113 is in a transmitting mode or a receiving mode. The receiving / transmitting data register 112 is used to store data to be received or transmitted. The receiving / transmitting logic controller 113 is used to connect to the data communication bus, and store the serial data received on the data communication bus Rx into the receiving / transmitting data register 112 according to the control command from the receiving / transmitting control register 111, or send the data in the receiving / transmitting data register 112 to the external communication device 200 through the data communication bus Tx.

[0035] Further, the communication baud rate detection module 120 includes a baud rate detection logic unit 121, a baud rate data register 122, a baud rate detection control unit 123, a synchronization frame data buffer register 124 and a synchronization frame data detection logic unit 125. Among them, the baud rate detection logic unit 121 is used to connect to the data communication bus Rx, and calculate multiple baud rates according to the synchronization frame of the serial data received on the data communication bus Rx. The baud rate data register 122 is used to receive and store the baud rate detected by the baud rate detection logic unit 121, so that the MCU 102 can read the baud rate and set the data transmission baud rate. The synchronization frame data buffer register 124 is used to cache the data of the synchronization frame of the serial data received on the data communication bus Rx. The synchronization frame data detection logic unit 125 is used to compare the data of the specific byte segment of the synchronization frame stored in the synchronization frame data buffer register 124 with the agreed data, and obtain the detection result according to the comparison result. The baud rate detection control unit 123 is used to control the operation state of the baud rate detection logic unit 121 according to the detection result output by the synchronization frame data detection logic unit 125.

[0036] In an exemplary implementation, the UART device may be disposed in the communication interface of the MCU 102. Of course, the present invention is not limited thereto, and those skilled in the art may specifically set the location of the UART device according to actual conditions.

[0037] Figure 2 A schematic diagram showing a synchronization frame of a UART serial communication protocol according to a first embodiment of the present invention. Figure 3 A schematic diagram of the structure of a baud rate detection logic unit in a UART device according to an embodiment of the present invention is shown. Figure 2 and Figure 3 The working principle of the baud rate detection logic unit of this embodiment is described.

[0038] like Figure 2 As shown, the serial data used by the UART device of this embodiment includes a synchronization frame and one or more subsequent data frames. The UART device uses the synchronization frame in the serial data to perform data synchronization and detect errors.

[0039] In an exemplary embodiment, the serial data uses a synchronization frame with a preset character of 0xAA for baud rate calibration and data packet verification. Figure 2 As shown, the synchronization frame includes a start bit S, a plurality of data bits B0 to B7, and an end bit E. Further, in this embodiment, the synchronization frame is divided into N byte segments, N is a non-zero natural number (in a specific embodiment, N=5), the byte segment of the first timing sequence includes the start bit S and the data bit B0, the byte segment of the second timing sequence includes the data bits B1 and B2, and so on, the byte segment of the fifth timing sequence includes the data bit B7 and the end bit E. The baud rate detection logic unit 121 is used to obtain the start time of the synchronization frame during the serial communication process, and then sequentially receive the N byte segments of the synchronization frame, calculate multiple baud rates according to the duration from the specific edge of the N byte segments to the start time, and then the MCU102 obtains the data transmission baud rate according to the multiple baud rates, and receives one or more data frames after the synchronization frame based on the data transmission baud rate.

[0040] Figure 3 FIG. 2 is a schematic diagram showing the structure of a baud rate detection logic unit in a UART device according to a first embodiment of the present invention. Figure 3 As shown, the baud rate detection logic unit 121 of this embodiment includes an uninterrupted counter 1211, an edge counter 1212 and a baud rate calculation module 1213. Among them, the uninterrupted counter 1211 is used to start uninterrupted counting at the start time of the synchronization frame, and output the baud rate count value Ai (i=1, 2, ..., N-1) every time a specific edge of a byte segment is detected, so each baud rate count value Ai represents the duration from the specific edge of each byte segment to the start time. The edge counter 1212 is used to count the specific edges of the synchronization frame, and is used to add 1 to the count value when each specific edge is detected, and output the edge count value Q. The baud rate calculation module 1213 is used to receive the baud rate count value Ai and the edge count value Q, determine the baud rate division ratio according to the edge count value Q, and then calculate the baud rate Bri (i=1, 2, ..., N-1) according to the baud rate count value Ai and the edge count value Q. Furthermore, the i-th baud rate is calculated using the following formula:

[0041]

[0042] Among them, Bri is the i-th baud rate, Ai is the baud rate count value, that is, the duration from the specific edge of the byte segment of the i-th timing sequence to the starting time, and 2Q is the baud rate division ratio obtained according to the edge count value Q.

[0043] Furthermore, the start time is the start edge of the byte segment of the 1st timing sequence, and the specific edge is the end edge of the byte segment of the 1st timing sequence to the N-1th timing sequence. Furthermore, since the start bit S in the synchronization frame of this embodiment is 1 bit of "0" (low level), and since the UART communication protocol is transmitted from low level to high level, the transmitted data bit B0 is also 1 bit of "0", and the data bits B1 to B7 are 1 bit of "1" (high level) and 1 bit of "0" that change alternately, so the start time is the falling edge from high level to low level before the start bit S, and the specific edge is the rising edge from low level to high level of each byte segment.

[0044] Example, reference Figures 1 to 3 , the non-stop counter 1211 starts counting from 0 when the first falling edge is detected, and the initial value Q of the edge counter 1212 is 0, the asynchronous receiving / transmitting module 110 and the baud rate detection logic unit 121 receive the byte segment of the first timing sequence according to the initial baud rate, that is, the start bit S and the data bit B0, when the first rising edge arrives after the byte segment of the first timing sequence is received, the baud rate count value output by the non-stop counter 1211 becomes A1, and the count value of the edge counter 1212 is also increased by 1, that is, Q=1 at this time, and then the baud rate Br1=A1 / 2 at this time can be obtained through the baud rate calculation module 1213 according to the above calculation formula. Then, the MCU 102 controls the asynchronous receiving / transmitting module 110 to receive the byte segment of the second timing sequence, that is, the data bits B1 and B2, according to the baud rate Br1. When the second rising edge arrives after the byte segment of the second timing sequence is received, the baud rate count value output by the uninterruptible counter 1211 becomes A2, and the edge count value Q output by the edge counter 1212 is Q=2. Then, the new baud rate Br2=A2 / 4 is obtained through the baud rate calculation module 1213. MCU 102 then controls the asynchronous receiving / transmitting module 110 to receive the byte segment of the third timing sequence according to the new baud rate Br2, and so on, until MCU 102 controls the asynchronous receiving / transmitting module 110 to receive the byte segment of the fifth timing sequence according to the baud rate Br4, that is, after the data bit B7 and the end bit E, indicating that the entire synchronous frame reception is completed. At this time, MCU 102 uses baud rate Br4 as the final data transmission baud rate, and controls the data transmission rate of one or more data frames after the asynchronous receiving / transmitting module 110 receives the synchronous frame according to baud rate Br4.

[0045] Furthermore, the communication baud rate detection module 120 of the present embodiment is also used to collect and update the data transmission baud rate of the UART device in real time according to the rising edge of the synchronization frame, and at the same time, perform data verification according to a specific byte segment of the synchronization frame through the synchronization frame data buffer register 124 and the synchronization frame data detection logic unit 125. Taking 0xAA as a data packet of the synchronization frame as an example, the agreed data of the byte segment from the 2nd timing sequence to the N-1th timing sequence is "10", and the agreed data of the byte segment of the Nth timing sequence is "11". The following takes the byte segment of the second timing sequence and the byte segment of the fifth timing sequence as examples. In the second timing sequence, after the data of the byte segments B1 and B2 of the second timing sequence received according to the data transmission rate set by the baud rate Br1 are stored in the synchronous frame data buffer register 124, the synchronous frame data detection logic unit 125 determines whether the data stored in the synchronous frame data buffer register 124 is the agreed data "10". If so, it means that the data verification of the byte segment of the second timing sequence is correct, and the step of calculating the baud rate Br2 is continued; if not, it means that the data verification of the byte segment of the second timing sequence is wrong, and the synchronous frame data detection logic unit 125 reports an interrupt to the MCU 102 to discard the entire data packet. At the same time, the baud rate detection control unit 123 controls the counter in the baud rate detection logic unit 121 to stop counting and reset according to the detection result of the synchronous frame data detection logic unit 125. For the byte segment of the 5th timing sequence, the synchronization frame data detection logic unit 125 determines whether the data bit B7 and the end bit E stored in the synchronization frame data cache register 124 are "11". If so, it means that the data verification of the byte segment of the 5th timing sequence is correct, and the MCU 102 sets the baud rate Br4 stored in the baud rate data register 122 as the final data transmission baud rate; if not, the entire data packet is discarded.

[0046] Figure 4 FIG. 2 is a flow chart of a serial data receiving method according to a second embodiment of the present invention, wherein the serial data receiving method is used in the UART device in the first embodiment. Figure 4 As shown, the serial data receiving method of this embodiment includes:

[0047] Step S301, obtaining the start time of the synchronization frame. Specifically, the UART device of this embodiment uses a synchronization frame with a preset character of 0xAA to perform baud rate calibration and data packet verification, and its format is a 1-bit start bit "0" followed by 8-bit data bits (8-bit data bits are sent from low to high), so the start time of the synchronization frame is the falling edge before the start bit S, and the UART device is used to detect the falling edge of the low level of the synchronization frame as the start time to perform automatic baud rate detection.

[0048] Step S302, sequentially receive N byte segments of the synchronization frame, and obtain the data transmission baud rate according to the duration from the specific edge of the N byte segments to the start time. Specifically, the synchronization frame in this embodiment is divided into N byte segments, N is a non-zero natural number (in a specific embodiment, N=5), the byte segment of the first timing sequence includes the start bit S and the data bit B0, the byte segment of the second timing sequence includes the data bits B1 and B2, and so on, the byte segment of the fifth timing sequence includes the data bit B7 and the end bit E. The specific edge is the end edge of each byte segment. Since the 8-bit data bit is "01" that changes alternately, the end edge of each byte segment is the rising edge from the low level to the high level. The baud rate detection logic unit 121 in the UART device 100 sequentially receives the N byte segments of the synchronization frame during the serial communication process, calculates multiple baud rates according to the duration from the rising edge of the N byte segments to the start time, and then determines the data transmission baud rate during the serial communication process according to the multiple baud rates.

[0049] Step S303, receiving a data frame based on the data transmission baud rate. Specifically, the multiple baud rates obtained by the baud rate detection logic unit 121 are stored in the baud rate data register 122, and the MCU 102 reads the latest stored baud rate in the baud rate data register 122 after the synchronization frame ends and sets the data transmission baud rate, and then controls the data transmission rate of receiving the subsequent one or more data frames based on the data transmission baud rate.

[0050] Figure 5 Show Figure 4 Detailed flow chart of step S302 in FIG. Figure 5 As shown, in a further embodiment, the step of sequentially receiving N byte segments of a synchronization frame and obtaining a data transmission baud rate according to a duration from a specific edge of the N byte segments to a start time further includes the following steps:

[0051] Step S320, set i=0, where i represents the timing sequence of the currently received byte segment.

[0052] Step S321, set i=i+1.

[0053] Step S322, calculate the i-th baud rate based on the duration from the specific edge of the byte segment of the i-th timing sequence to the start time. The specific edge is the end edge of each byte segment, that is, the rising edge of each byte segment from a low level to a high level. The start time is the start edge of the byte segment of the first timing sequence, that is, the falling edge before the start bit S.

[0054] In this step, the uninterrupted counter 1211 counts continuously from the start of the synchronization frame according to the reference clock, and outputs the baud rate count value Ai (i=1, 2, ..., N-1) each time a rising edge of a byte segment is detected, so each baud rate count value Ai represents the duration from a specific edge of each byte segment to the start time. Further, the counting method of the uninterrupted counter 1211 is continuous accumulation, clearing before counting, accumulating 1 when each reference clock arrives, and outputting the count value each time a rising edge is detected.

[0055] In this step, the rising edges in the synchronization frame are counted by the edge counter 1212. The edge count value 1212 is counted in a continuous accumulation manner, cleared before counting, and accumulated by 1 when each rising edge of the synchronization frame arrives, and the counting result is output as the edge count value.

[0056] In this step, the baud rate calculation module 1213 is also used to calculate the baud rate Bri (i=1, 2, ..., N-1) of the i-th timing sequence according to the previously obtained baud rate count value Ai and edge count value Q. Further, the i-th baud rate is calculated using the following formula:

[0057]

[0058] Among them, Bri is the i-th baud rate, A i is the baud rate count value, that is, the duration from the specific edge of the byte segment of the i-th timing sequence to the starting time, and 2Q is the baud rate division ratio obtained according to the edge count value Q.

[0059] Step S323, based on the i-th baud rate, the data of the byte segment of the i+1th timing sequence is received. For example, the uninterruptible counter 1211 starts counting from 0 when the first falling edge is detected, and the initial value Q of the edge counter 1212 is 0, the asynchronous receiving / transmitting module 110 and the baud rate detection logic unit 121 receive the byte segment of the first timing sequence according to the initial baud rate, that is, the start bit S and the data bit B0, when the first rising edge after the byte segment of the first timing sequence is received, the baud rate count value output by the uninterruptible counter 1211 becomes A1, and the count value of the edge counter 1212 is also increased by 1, that is, Q=1 at this time, and then the baud rate Br1=A1 / 2 can be obtained by the baud rate calculation module 1213 according to the above calculation formula. Then, the MCU 102 controls the asynchronous receiving / transmitting module 110 to receive the byte segment of the second timing sequence, that is, the data bits B1 and B2, according to the baud rate Br1. When the second rising edge arrives after the byte segment of the second timing sequence is received, the baud rate count value output by the uninterruptible counter 1211 becomes A2, and the edge count value Q output by the edge counter 1212 is Q=2. Then, the new baud rate Br2=A2 / 4 is obtained through the baud rate calculation module 1213. MCU 102 then controls the asynchronous receiving / transmitting module 110 to receive the byte segment of the third timing sequence according to the new baud rate Br2, and so on, until MCU 102 controls the asynchronous receiving / transmitting module 110 to receive the byte segment of the fifth timing sequence according to the baud rate Br4, that is, after the data bit B7 and the end bit E, indicating that the entire synchronous frame reception is completed. At this time, MCU 102 uses baud rate Br4 as the final data transmission baud rate, and controls the data transmission rate of one or more data frames after the asynchronous receiving / transmitting module 110 receives the synchronous frame according to baud rate Br4.

[0060] Step S324, determine whether the data of the byte segment of the i+1th timing sequence is the same as the agreed data. If not, proceed to step S325; if so, proceed to step S326. In this step, data verification is performed according to the specific byte segment of the synchronization frame through the synchronization frame data buffer register 124 and the synchronization frame data detection logic unit 125. Taking 0xAA as the data packet of the synchronization frame as an example, the agreed data of the byte segment from the 2nd timing sequence to the N-1th timing sequence is "10", and the agreed data of the byte segment of the Nth timing sequence is "11".

[0061] Step S325: the synchronization frame detection fails and the entire data packet is discarded.

[0062] Step S326, determine whether i is less than N-1. If yes, return to step S321; if no, proceed to step S327.

[0063] Step S327: The synchronization frame detection is successful, and the N-1th baud rate is determined as the data transmission baud rate.

[0064] In summary, the serial data receiving method in the embodiment of the present invention calibrates the baud rate multiple times by collecting the rising edge in the synchronization frame. Compared with the solution in the prior art that uses 20% of the data (2 bits) in the synchronization frame to determine the data transmission baud rate, the present invention increases the baud rate to use 80% of the data (8 bits) in the synchronization frame to determine the baud rate, ensuring that subsequent data is collected using a baud rate with a relatively small error, which can improve the accuracy and precision of data transmission.

[0065] Furthermore, in practical applications, when there is a quantization error in the received data, it is generally manifested in the judgment of "0" and "1" at the level jump edge. The positive deviation is manifested as the high-level pulse width will be significantly shorter than the low-level pulse width when the high and low levels change, and the negative deviation is manifested as the high-level pulse width will be significantly longer than the low-level pulse width when the high and low levels change. The baud rate benchmark is set to 100%, assuming that the low level duration of the byte segment of the first timing sequence is 2α, and the durations of the byte segments of the second to fourth timing sequences are 2β, 2γ, and 2δ, respectively. Thus, the first baud rate Br1=α can be obtained when the first rising edge of the synchronization frame arrives. Check the data of the next 2 bits (i.e., data bits B1 and B2). Assuming that the communication environment of the present invention is the same as that of the prior art, that is, in a data packet with 0xAA as the synchronization frame, the baud rate of the first 2 bits of the synchronization frame has a positive deviation, and the baud rate of the subsequent 8 bits has a negative deviation. Assuming that the maximum error between the actual baud rate and the preset baud rate is x, it can be obtained that α=100%+x, β=γ=δ=100%-x. Then, the second baud rate when the second rising edge arrives can be obtained respectively. When the third rising edge arrives, the third baud rate When the 4th rising edge arrives, the 4th baud rate

[0066] In addition, since the serial data receiving method of this embodiment is midpoint sampling, the maximum error of the subsequent collected data is 50% / 10=5%, that is, the formula can be obtained:

[0067]

[0068] By solving the equation, it can be obtained that the maximum error of the embodiment of the present invention is (-11.1%, 9%). Compared with the maximum error (-2.5%, 2.4%) in the data receiving method of the prior art, the serial data receiving method of the embodiment of the present invention has a higher tolerance for the quantization error of the received data, lower requirements for communication hardware, and better accuracy and precision during data communication.

[0069] In summary, the serial data receiving method for a UART device of an embodiment of the present invention obtains multiple baud rates according to the duration from a specific edge of multiple byte segments in a synchronization frame to the start time, and then calibrates the data transmission baud rate multiple times according to the multiple baud rates, and verifies the data of the specific byte segment during the calibration, which can effectively reduce the bit error rate caused by clock deviation and improve the accuracy and stability of data transmission. In addition, the data receiving method of an embodiment of the present invention has a higher tolerance for the quantization error of the received data and lower requirements for the communication hardware, so that the receiving end can better adapt to the baud rate of the sending end and improve the compatibility between different devices.

[0070] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0071] Finally, it should be noted that: Obviously, the above embodiments are only examples for clearly explaining the present invention, and are not intended to limit the implementation methods. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from this are still within the scope of protection of the present invention.

Claims

1. A method for receiving serial data, wherein the serial data consists of a synchronization frame and a data frame, wherein the synchronization frame includes N byte segments, N is a non-zero natural number, and the method for receiving serial data comprises: Obtaining the start time of the synchronization frame; receiving the N byte segments of the synchronization frame in sequence, and obtaining a data transmission baud rate according to a duration from a specific edge of the N byte segments to the start time; receiving the data frame based on the data transmission baud rate, The sequentially receiving the N byte segments and obtaining the data transmission baud rate according to the specific edge of the N byte segments and the start time comprises: Calculating the i-th baud rate based on the duration from the specific edge of the byte segment of the i-th timing sequence to the start time, and performing baud rate calibration on the i-th baud rate based on the data change of the byte segment of the i+1-th timing sequence, where i is a non-zero natural number less than N; and After the calibration result meets the set requirements, the N-1th baud rate is determined as the data transmission baud rate.

2. The serial data receiving method according to claim 1, wherein: The baud rate calibration of the i-th baud rate based on the data change of the byte segment of the i+1-th timing sequence includes: Receive data of the byte segment of the i+1th timing sequence based on the ith baud rate; The data of the byte segment at the i+1th timing sequence is compared with the agreed data. If the two are the same, the subsequent data is continued to be received. If the two are different, the entire data packet is discarded.

3. The serial data receiving method according to claim 1, wherein: The duration from the specific edge of the byte segment of the i-th timing sequence to the start time is obtained by a baud rate count value generated by an uninterrupted counter, wherein the uninterrupted counter is used to start uninterrupted counting when the start time is detected, and output a baud rate count value each time a specific edge is detected. The serial data receiving method further comprises: An edge counter is used to count the number of the specific edges to obtain an edge count value. The i-th baud rate is calculated using the following formula: Among them, Bri is the i-th baud rate, A i is the baud rate count value, and Q is the edge count value.

4. The serial data receiving method according to claim 1, wherein: The starting time is the starting edge of the byte segment with the first timing sequence, and the specific edge is the ending edge of the byte segment with the first timing sequence to the N-1th timing sequence. Among them, the preset character of the synchronization frame is 0xAA, the starting edge of the byte segment of the first timing sequence is the falling edge from the high level to the low level, and the ending edge of the byte segment from the first timing sequence to the N-1th timing sequence is the rising edge from the low level to the high level.

5. The serial data receiving method according to claim 2, wherein: Each of the N byte segments includes 2 bits of data, the agreed data corresponding to the byte segments from the 2nd to the N-1th timing sequence is "10", and the agreed data corresponding to the byte segment of the Nth timing sequence is "11".

6. A communication baud rate detection module for an asynchronous receiver-transmitter, comprising: A baud rate detection logic unit, used to obtain the start time of a synchronization frame, and sequentially receive N byte segments of the synchronization frame, and obtain multiple baud rates according to the duration from a specific edge of the N byte segments to the start time; A microcontroller, configured to set a data transmission baud rate according to the plurality of baud rates, and receive the data frame based on the data transmission baud rate; The baud rate detection logic unit is used to calculate the i-th baud rate based on the duration from the specific edge of the byte segment of the i-th timing sequence to the start time in the process of obtaining multiple baud rates according to the duration from the specific edge of the N byte segments to the start time, where i is a non-zero natural number less than N, The communication baud rate detection module also includes: a synchronous frame data detection logic unit, which is used to calibrate the i-th baud rate based on the data change of the byte segment of the i+1th timing sequence, and control the microcontroller to determine the N-1th baud rate as the data transmission baud rate after the calibration result meets the set requirements.

7. The communication baud rate detection module according to claim 6, wherein: The baud rate detection logic unit comprises: an uninterrupted counter, configured to start uninterrupted counting when the start time is detected, and output a baud rate count value each time a specific edge is detected, wherein the baud rate count value corresponds to a duration from a specific edge of a corresponding byte segment to the start time; an edge counter, used for counting the number of the specific edges to obtain an edge count value; and a baud rate calculation module, configured to calculate the plurality of baud rates according to the baud rate count value and the edge count value, The baud rate calculation module uses the following formula to calculate the i-th baud rate corresponding to the byte segment of the i-th timing sequence: Among them, Bri is the i-th baud rate, A i is the baud rate count value, and Q is the edge count value.

8. The communication baud rate detection module according to claim 6, wherein: The synchronization frame data detection logic unit is used to perform the following operations during the baud rate calibration of the i-th baud rate based on the data change of the byte segment of the i+1-th timing sequence: The data of the byte segment of the i+1th timing sequence received based on the i-th baud rate is compared with the agreed data. If the two are the same, the subsequent data is continued to be received. If the two are different, the output calibration result does not meet the set requirements and the entire data packet is discarded.

9. The communication baud rate detection module according to claim 6, wherein: The starting time is the starting edge of the byte segment with the first timing sequence, and the specific edge is the ending edge of the byte segment with the first timing sequence to the N-1th timing sequence. Among them, the preset character of the synchronization frame is 0xAA, the starting edge of the byte segment of the first timing sequence is the falling edge from the high level to the low level, and the ending edge of the byte segment from the first timing sequence to the N-1th timing sequence is the rising edge from the low level to the high level.

10. The communication baud rate detection module according to claim 6, wherein: Each of the N byte segments includes 2 bits of data, the agreed data corresponding to the byte segments from the 2nd to the N-1th timing sequence is "10", and the agreed data corresponding to the byte segment of the Nth timing sequence is "11".

11. The communication baud rate detection module according to claim 6, further comprising: A baud rate data register, used for storing a plurality of baud rates output by the baud rate detection logic unit, so that the microcontroller can read and set the data transmission baud rate; A synchronization frame data buffer register, used for buffering the data of the synchronization frame for reading by the synchronization frame data detection logic unit; as well as a baud rate detection control unit, used to control the operating state of the baud rate detection logic unit according to the detection result output by the synchronization frame data detection logic unit, The baud rate detection control unit is used to shut down the baud rate detection logic unit when the calibration result output by the synchronization frame data detection logic unit does not meet the set requirements.

12. An asynchronous receiver-transmitter, comprising: Asynchronous receiving / transmitting module, used for converting received serial data into parallel data; as well as The communication baud rate detection module according to any one of claims 6 to 11, wherein the communication baud rate detection module is used to control the data transmission rate of the asynchronous receiving / transmitting module.

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