Novel nano wall (NWaFET) IC structure of cascade transistor
Through the longitudinally stacked cascade transistor nanowall IC structure, the problem of inability to shorten the channel length and low integration in traditional MOS cascade structure is solved, which achieves higher integration and frequency, and simplifies the process flow and supports multiple This connection method is used to achieve different functions.
Patent Information
- Application Number
- CN202411198893.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-29
- Publication Date
- 2024-12-13
AI Technical Summary
The lateral arrangement of traditional MOS cascade structures leads to problems such as inability to continuously shorten the channel length, large area occupied and low integration.
Using a longitudinally stacked cascade transistor nanowall IC structure, the series, parallel and cascade gain-level structures of multiple nanowall structure transistors are realized by flexibly changing the source, drain and gate connection methods of MOS tubes, and the channel is further shortened. length and increase integration.
The continuous shortening of channel length is achieved, the integration and device operating frequency is improved, and the process flow is simple, allowing flexible transformation of cascade modes to achieve different functions.
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Figure CN119133181A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the field of integrated circuits, in particular to a novel nano-wall IC structure of cascade transistors. Background Art
[0002] The integrated circuit industry has developed rapidly since the 1950s. [1] The number of components on a chip doubles every six months (every 18 months after 1975), and the performance and capacity of semiconductors will grow exponentially. [2] The basis of Moore's Law is the scaling down of integrated circuits. However, according to the IEEE International Roadmap for Devices and Systems (IRDS), the channel length Lch of integrated circuits cannot exceed (be less than) 12nm. [3] , Moore's Law will face the dilemma of being unable to move forward.
[0003] The NWaFET IC structure proposed by our research group has a MOS transistor whose Lch is not determined by lithography but by epitaxial growth, which frees advanced ICs from dependence on EUV lithography machines. Using the NWaFET IC structure, Lch = 5, 4, and 3nm chips can be produced using a 14nm lithography machine, which can enable my country to quickly and thoroughly break through the foreign technology blockade of high-end ICs. The HVTFET (heterojunction vertical channel field effect transistor) and the new nano-wall NWaFET structure before this invention [4-6] , adopting a vertical design scheme, greatly improving the integration of the device, and suppressing the drain-induced barrier lowering (DIBL) effect through a combined structure of heavily doped channel region and lightly doped drift region. HVT and NWaFET structures achieve a further reduction in Lch by adopting heavily doped channel. It is better than the existing fin field effect transistor (FinFET) [7] , Gate-All-Around (GAA) transistor [8] Such devices have a shorter channel length Lch and a higher degree of integration.
[0004] The cascade structure of MOS tubes mainly involves connecting multiple MOS tubes in a specific way to achieve specific circuit functions. This structure is particularly common in analog circuits, and various signal processing is achieved through different connection methods, such as series structure, parallel structure and cascade gain stage.
[0005] Since the cascade structure is a specific connection between multiple MOS tubes, and the traditional cascade structure is composed of horizontally arranged MOS transistors, it will inevitably occupy a large area, which is not conducive to improving the integration level. The fundamental reason is that the channel length of the MOS tube cannot be continuously shortened.
[0006] References
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[0017] [7].Chenming Hu,Lee WC,Kedzierski J,et al.FinFET-a self-aligneddouble-gate MOSFET scalable to 20nm[J].IEEE Transactions on Electron Devices, 2000,
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[0019] [8].JPColinge,MHGao,A.Romano,H.Maes,C.Claeys.Silicon-on-insulator
[0020] "gate-all-around" MOS device[C].1990IEEE SOS / SOI TechnologyConference.Proceedings.KeyWest, FL, USA: IEEE, 1990:137-138. Summary of the invention
[0021] The main purpose of the present invention is to propose a novel nano-wall IC structure model of cascade transistors to solve the problems of the traditional MOS cascade structure being arranged horizontally, the channel length cannot be continuously shortened, the occupied area is large, and the integration is low. To achieve the above purpose, the present invention proposes a novel nano-wall IC structure model of cascade transistors (NWaFET), which can include two or even more vertical MOS structures.
[0022] Technical solution 1 of the present invention is as follows Figure 1 As shown, the active area material is single crystal Si, and each vertical MOS structure is composed of the bottom P-well silicon single crystal semiconductor region 101, the upper N+ active region 102, N-active regions 103, 104, P+ channel regions 105, 106, N-active regions 107, 108, and the top N+ active regions 109, 110. On the sides of each vertical MOS structure are SiO2 insulating layer regions 113, 115, and on both sides of the P+ channel regions 105, 106, the Poly-Si gate electrode regions 111, 112 in the middle of the SiO2 insulating layers 113, 115. In the middle of the two vertical MOS structures is the SiO2 insulating layer region 114. The bottom N+ active region 102 and the top N+ active regions 109, 110 can be flexibly changed to be the source and drain, and the gate electrodes 111, 112 can be respectively led out through metal leads.
[0023] Technical solution 2 of the present invention is as follows Figure 2As shown, the active area material is single crystal Si, and each vertical MOS structure is composed of the bottom N-well silicon single crystal semiconductor region 201, the upper P+ active region 202, P- active regions 203, 204, N+ channel regions 205, 206, P- active regions 207, 208, and the top P+ active regions 209, 210. On the sides of each vertical MOS structure are SiO2 insulating layer regions 113, 115, and on both sides of the N+ channel regions 205, 206, the Poly-Si gate electrode regions 111, 112 in the middle of the SiO2 insulating layers 113, 115. The middle of the two vertical MOS structures is the SiO2 insulating layer region 114. The bottom P+ active region 202 and the top P+ active regions 209, 210 can be flexibly changed to be the source and drain, and the gate electrodes 111, 112 can be respectively led out through metal leads.
[0024] Working in series Figure 3 and Figure 4 As shown, it works in a head-to-tail mode, with the shared active area serving as the source and drain areas of several MOS structures, and the gates are independent of each other. The drain area of M1 and the source area of M2 share an active area; the source area S of M1 and the gate electrode G1 are led out by wires; the drain area D of M2 and the gate electrode G2 are led out by wires. The circuit connection principle when connected in series is as follows Fig. 9 shown.
[0025] Parallel operation Figure 5 and Figure 6 As shown, they work in parallel, and the shared active area serves as the drain area of several MOS structures. The source areas are connected together through interconnection lines, and the gates are connected together through interconnection lines. The gate electrode of M1 is connected to the gate electrode of M2 through interconnection lines, and the lead is G; the source area of M1 is connected to the source area of M2 through interconnection lines, and the lead is S; the drain area of M1 and the drain area of M2 share an active area, and the lead is D through the lead. The circuit connection principle when connected in parallel is as follows Fig.10 shown.
[0026] Cascaded gain stages such as Figure 7 and Figure 8 As shown, the shared active area is used as the source area, the drain of one MOS is connected to the gate of another MOS, and then the remaining gate is used as the input, and the remaining drain is used as the output. The drain area of M1 is connected to the gate electrode of M2 through an interconnection line, and the lead is D1 / G2; the source areas of M1 and M2 share an active area, and the lead is S; the gate electrode G1 of M1 is led out by a lead, and the drain area D2 of M2 is led out by a lead. The circuit connection principle when working as a cascade gain stage is as follows Fig.11 shown.
[0027] Furthermore, the thickness of the N+ type channel semiconductor region of the PMOS is less than 12 nm.
[0028] Furthermore, the doping concentration of the N+ channel semiconductor region of the PMOS is more than 2 orders of magnitude higher than that of the P-drain region.
[0029] Furthermore, the thickness of the P+ type channel semiconductor region of the NMOS is less than 12 nm.
[0030] Furthermore, the doping concentration of the P+ channel semiconductor region of the NMOS is more than 2 orders of magnitude higher than that of the P-drain region.
[0031] Furthermore, the gate electrodes are respectively arranged on the entire area of one side of the semiconductor region or on a local area of one side of the semiconductor region, such as Fig.12 (a) shown.
[0032] Furthermore, the gate electrodes are respectively arranged on the entire area of the two side surfaces of the semiconductor region or on the local area of the two side surfaces of the semiconductor region, such as Fig.12 (b) as shown.
[0033] Furthermore, the gate electrodes are respectively arranged on the entire area of the three sides of the semiconductor region or on the local area of the three sides of the semiconductor region, such as Fig.12 (c) as shown.
[0034] Furthermore, the thickness of all layers ranges from 1nm to 100nm, and the doping concentration ranges from 1e14cm -3 -1e20cm -3 .
[0035] The present invention provides a nano-wall IC structure model of vertically stacked cascade transistors, wherein multiple transistors are connected in a U-shape, and the series connection, parallel connection and cascade connection of multiple nano-wall structure transistors are realized by flexibly changing the source, drain and gate connection modes of the MOS tubes. The present invention can not only improve the integration of the cascade structure, but also continue to reduce the channel length to increase the device operating frequency, and can also realize flexible transformation of the cascade mode, and different connection modes can realize different functions. In the cascade structure model of the present invention, the source and drain regions are the same as those of the ordinary MOS structure, and in addition, there are lightly doped source and drain regions. The channel region is also heavily doped, so that the depletion region can be guaranteed to expand to the lightly doped drain region, thereby overcoming the DIBL effect.
[0036] In summary, the nano-wall IC structure model of the novel cascade transistor in the present invention has the following advantages: 1. The channel length of the nano-wall structure transistor can be continuously shortened, which can not only further reduce the area, improve the integration, but also reduce power consumption. 2. The same structure model can realize flexible transformation of the cascade mode. By simply adjusting the connection mode between the active area and the gate electrode, structures such as series connection, parallel connection and cascade gain stage can be realized.
[0037] 3. The process is simple and easy to implement. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] Figure 1 This is an oblique cross-sectional view of the NMOS nanowall transistor cascade structure model.
[0039] Figure 2 This is an oblique cross-sectional view of the PMOS nanowall transistor cascade structure model.
[0040] Figure 3 An oblique cross-sectional view of a structural model of an NMOS nanowall transistor cascade structure operating in series.
[0041] Figure 4 An oblique cross-sectional view of a structural model of a PMOS nanowall transistor cascade structure working in series.
[0042] Figure 5 An oblique cross-sectional view of a structural model of a cascade structure of NMOS nanowall transistors operating in parallel.
[0043] Figure 6 An oblique cross-sectional view of a structural model of a PMOS nanowall transistor cascade structure operating in parallel.
[0044] Figure 7 An oblique cross-sectional view of a structural model of an NMOS nanowall transistor cascade structure operating as a cascade gain stage.
[0045] Figure 8 An oblique cross-sectional view of a structural model of a PMOS nanowall transistor cascade structure operating as a cascade gain stage.
[0046] Fig. 9 This is the circuit schematic diagram of the cascade structure working in series.
[0047] Fig.10 This is the circuit schematic diagram of the cascade structure working in parallel.
[0048] Fig.11 This is a circuit schematic diagram of the cascade structure working as a cascade gain stage.
[0049] Fig.12 It is a top-down cross-sectional view of the cascade structure model at different channel widths (different numbers of ring gates).
[0050] Fig.13 The output curve simulation diagram of the NMOS nanowall transistor structure when the channel length is 10nm and the lightly doped region is 80nm. (a) is the output curve simulation diagram of the non-series (single MOS) case, and (b) is the output curve simulation diagram when the cascade structure works in series.
[0051] Fig.14 This is a simulation curve of the amplitude-frequency characteristics of the NMOS nanowall transistor cascade structure when it works as a cascade gain stage. DETAILED DESCRIPTION
[0052] Example 1: Cascade structure model as a practical connection method when working in series
[0053] In order to clearly understand the nano-wall (NWaFET) IC structure of a novel cascade transistor of the present invention, this embodiment specifically shows a 3D schematic diagram of a cascade structure model as an actual connection mode when working in series, such as Figure 3 and Figure 4 As shown, the drain region of M1 and the source region of M2 share an active region; the source region S of M1 and the gate electrode G1 are led out by wires; the drain region D of M2 and the gate electrode G2 are led out by wires. The circuit connection principle is as follows Fig. 9 As shown. Under short channel, the output curve of dual-gate MOS will be greatly improved compared with single-gate MOS, and can be used as a constant current source. The simulation results are shown in Fig.13 shown.
[0054] Example 2: Cascade structure model as a practical connection method for parallel operation
[0055] In order to clearly understand the nano-wall (NWaFET) IC structure of a novel cascade transistor of the present invention, this embodiment specifically shows a 3D schematic diagram of a cascade structure model as an actual connection mode when working in parallel, such as Figure 5 and Figure 6 As shown, the gate electrode of M1 is connected to the gate electrode of M2 through an interconnection line, which is led out as G; the source region of M1 is connected to the source region of M2 through an interconnection line, which is led out as S; the drain region of M1 and the drain region of M2 share an active region, which is led out as D through a lead. The circuit connection principle is as follows Fig.10 shown.
[0056] Example 3: Cascade structure model as a practical connection mode when the cascade gain stage works
[0057] In order to clearly understand the nano-wall (NWaFET) IC structure of a novel cascade transistor of the present invention, this embodiment specifically shows a three-dimensional schematic diagram of an actual connection mode when the cascade structure model works as a cascade gain stage, such as Figure 7 and Figure 8 As shown, the drain region of M1 is connected to the gate electrode of M2 through an interconnection line, and the lead is D1 / G2; the source regions of M1 and M2 share an active region, and the lead is S; the gate electrode G1 of M1 is led out by a lead, and the drain region D2 of M2 is led out by a lead. The circuit connection principle is as follows Fig.11At this time, its gain is equivalent to the square of the intrinsic gain of a single nano-wall MOS transistor. The simulation results of the amplitude-frequency characteristics under different Vgs bias are shown in Fig.14 shown.
Claims
1. A new type of cascade transistor nanowall (NWaFET) IC structure, It is characterized in that Each unit contains multiple vertical MOS structures, each of which is composed of N+ region, N- region, P+ channel region, N- region, N+ region and P-well, where the lower N+ region and P-well are shared by multiple vertical MOS tubes. Two vertical MOS tubes are isolated by SiO2, and the gate material is Poly-Si, which is located on the side of the P+ channel region and can be led out through metal wires.
2. A new type of cascade transistor nanowall (NWaFET) IC structure, It is characterized in that Each unit contains multiple vertical MOS structures, each of which is composed of P+ region, P- region, N+ channel region, P- region, P+ region and N-well, among which the lower P+ region and N-well are shared by multiple vertical MOS. Two vertical MOS tubes are isolated by SiO2, and the gate material is Poly-Si, which is located on the side of the N+ channel region and can be led out through metal wires.
3. A new type of cascade transistor nanowall (NWaFET) IC structure, It is characterized in that When working in series, it works in a head-to-tail mode, with the shared active area serving as the source and drain areas of several MOS structures, and the gates are independent of each other. The drain area of M1 and the source area of M2 share an active area; the source area S of M1 and the gate electrode G1 are led out by leads; the drain area D of M2 and the gate electrode G2 are led out by leads.
4. A new type of cascade transistor nano-wall (NWaFET) IC structure, It is characterized in that When working in parallel, they work in parallel, and the shared active area serves as the source area of several MOS structures, and their drain areas are connected together through interconnection lines, and the gates are connected together through interconnection lines. The gate electrode of M1 is connected to the gate electrode of M2 through interconnection lines, and the lead is G; the source area of M1 is connected to the source area of M2 through interconnection lines, and the lead is S; the drain area of M1 and the drain area of M2 share an active area, and the lead is D through the lead.
5. A new type of cascade transistor nano-wall (NWaFET) IC structure, It is characterized in that When working as a cascade gain stage, the shared active area is used as the source area, the drain of one MOS is connected to the gate of another MOS, and then the remaining gate is used as the input and the remaining drain is used as the output. The drain area of M1 is connected to the gate electrode of M2 through an interconnection line, and the lead is D1 / G2; the source areas of M1 and M2 share an active area, which is led to S; the gate electrode G1 of M1 is led out by a lead, and the drain area D2 of M2 is led out by a lead.
6. The vertically arranged transistor cascade integrated circuit structure according to any one of claims 1 to 5, It is characterized in that The thickness of the N-type channel semiconductor region of the PMOS is less than 12 nm, and the thickness of the P-type channel semiconductor region of the NMOS is less than 12 nm.
7. The vertically arranged transistor cascade integrated circuit structure according to any one of claims 1 to 5, It is characterized in that The doping concentration of the N-type channel semiconductor region of the PMOS is more than 2 orders of magnitude higher than that of the P-drain region, and the doping concentration of the P-type channel semiconductor region of the NMOS is more than 2 orders of magnitude higher than that of the N-drain region.
8. The vertically arranged transistor cascade integrated circuit structure according to any one of claims 1 to 5, It is characterized in that The thickness of all layers ranges from 1nm to 100nm, and the doping concentration ranges from 1e14cm -3 -1e20 cm -3 .
9. The vertically arranged transistor cascade integrated circuit structure according to any one of claims 1 to 5, It is characterized in that The gate electrodes are respectively arranged on the entire area of one side of the semiconductor region or on a local area of one side of the semiconductor region; further, the gate electrodes are respectively arranged on the entire area of two side surfaces of the semiconductor region or on a local area of two side surfaces of the semiconductor region; further, the gate electrodes are respectively arranged on the entire area of three side surfaces of the semiconductor region or on a local area of three side surfaces of the semiconductor region.