Five-level assembly line data processing method and device, assembly line, equipment and medium

Abstract

The invention discloses a data processing method and device for a five-level assembly line, the assembly line, equipment and a medium. The method is executed by a microprocessor with a five-stage pipeline structure, and comprises the following steps of: determining whether a first current instruction meets a dispatching condition or not through a decoding stage unit, and dispatching the first current instruction meeting the dispatching condition to an execution stage unit; performing logical operation on at least one second current instruction in the execution level unit through the execution level unit, determining a currently submitted target logical operation result in at least one logical operation result, and submitting the target logical operation result to an execution memory access pipeline register; and through the memory access level unit, determining a target instruction operation result which needs to be acquired by the memory access level unit at present, and submitting the acquired target instruction operation result to the memory access write-back pipeline register. By the adoption of the technical scheme, the problem of resource conflict in an existing five-level assembly line is solved, and the performance of the five-level assembly line can be effectively improved.

Description

Technical Field

[0001] The present invention relates to the field of data processing technology, and in particular to a five-stage pipeline data processing method, device, pipeline, equipment and medium. Background Art

[0002] The five-stage pipeline includes an instruction fetch unit, a decoding unit, an execution unit, a memory access unit, and a write-back unit. In the same time cycle, each unit will perform corresponding data processing on different instructions.

[0003] When an instruction in a five-stage pipeline depends on the running result of the previous instruction, there is data dependency between the two instructions. In the five-stage pipeline structure with sequential single issuance and out-of-order execution, when the two instructions have a write-first-write-later dependency or a write-first-read-later dependency, if the data processing logic of the pipeline is not improved, the execution-level unit will not be able to use the correct data for logical operations.

[0004] In the prior art, for instructions with write-before-read dependency, the pipeline is generally started to execute the current instruction after the result of the previous related instruction is written back to the general register stack, and there is no need to wait for the previous instruction to be written back to the general register stack, but the calculated result is bypassed through the reservation station to the operation unit of the current instruction. The above two methods solve the problem, but the instruction execution efficiency of the first method is low, and the data that can be stored in the reservation station of the second method is limited. For instructions with write-before-write dependency, the existing method generally writes the instruction back in the write-back level unit in order, but it is impossible to make the execution level unit and the memory access level unit submit the execution result in order. Summary of the invention

[0005] The present invention provides a data processing method, device, pipeline, equipment and medium for a five-stage pipeline, which solves the resource conflict problem in the existing five-stage pipeline and can effectively improve the performance of the five-stage pipeline.

[0006] According to one aspect of the present invention, there is provided a five-stage pipeline data processing method, which is executed by a microprocessor having a five-stage pipeline structure, comprising:

[0007] Through the decoding level unit, in each time cycle, according to the instruction information of the first current instruction and the preceding instruction in the decoding level unit, determining whether the first current instruction meets the dispatching condition, and dispatching the first current instruction that meets the dispatching condition to the execution level unit;

[0008] By means of the execution level unit, in each time cycle, a logic operation is performed on at least one second current instruction in the execution level unit, and a logic operation result is obtained, and a target logic operation result currently submitted is determined from at least one logic operation result, and the target logic operation result is submitted to the execution access memory pipeline register;

[0009] Through the memory access stage unit, in each time cycle, the target instruction operation result that the memory access stage unit should currently obtain is determined, and the obtained target instruction operation result is submitted to the memory access write-back pipeline register.

[0010] According to another aspect of the present invention, there is provided a five-stage pipeline data processing device, which is executed by a microprocessor having a five-stage pipeline structure, comprising:

[0011] An instruction dispatching module is used to determine whether the first current instruction meets the dispatching condition according to the instruction information of the first current instruction and the preceding instruction in the decoding level unit in each time cycle through the decoding level unit, and dispatch the first current instruction that meets the dispatching condition to the execution level unit;

[0012] An instruction calculation module, used to perform a logic operation on at least one second current instruction in the execution level unit in each time cycle through the execution level unit, and obtain a logic operation result, and determine a currently submitted target logic operation result from at least one logic operation result, and submit the target logic operation result to the execution access memory pipeline register;

[0013] The operation result memory access module is used to determine the target instruction operation result that the memory access level unit should currently obtain through the memory access level unit in each time cycle, and submit the obtained target instruction operation result to the memory access write-back pipeline register.

[0014] According to another aspect of the present invention, there is provided a five-stage pipeline structure, comprising: an instruction fetch stage unit, a decoding stage unit, an execution stage unit, a memory access stage unit, and a write-back stage unit;

[0015] The instruction fetch unit is used to fetch instructions from memory;

[0016] The decoding level unit, the execution level unit and the memory access level unit are used to execute the five-level pipeline data processing method according to any one of claims 1 to 7;

[0017] Wherein, a group of registers are configured in the execution level unit, and the registers are used to latch the logic operation results of the non-multiplication and division instructions when there are logic operation results of the non-multiplication and division instructions in the execution level unit and the bypass logic is enabled;

[0018] The write-back stage unit is used to write the operation result back to the general register file;

[0019] The five-stage pipeline structure also includes a general register stack, which is used to store operation results. The general register stack uses D flip-flops.

[0020] The five-stage pipeline structure also includes a system status register stack, which is used to store the operation results of system instructions;

[0021] The execution level unit is also used to read system instructions and perform system instruction operations, and the write-back level unit is also used to write the operation results of the system instructions back to the system status register stack.

[0022] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising:

[0023] at least one processor; and

[0024] a memory communicatively connected to the at least one processor; wherein,

[0025] The memory stores a computer program that can be executed by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the five-stage pipeline data processing method described in any embodiment of the present invention.

[0026] According to another aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the five-stage pipeline data processing method described in any embodiment of the present invention when executed.

[0027] The technical solution of the embodiment of the present invention can solve the resource conflict problem of the five-stage pipeline with sequential single issuance and out-of-order execution when there is a write-before-write dependency and a write-before-read dependency, and realize the order-preserving submission of the instructions of the execution stage unit and the memory access stage unit to the pipeline register, through the method that within each time cycle, the decoding stage unit dispatches the first current instruction that meets the dispatch conditions to the execution stage unit, the execution stage unit performs a logical operation on the second current instruction and submits the target logical operation result to the execution memory access pipeline register, and the memory access stage unit submits the target instruction operation result to the memory access write-back stage pipeline register.

[0028] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0030] Figure 1 is a flow chart of a five-stage pipeline data processing method provided according to Embodiment 1 of the present invention;

[0031] Figure 2 is a structural schematic diagram of a basic five-stage pipeline provided according to an embodiment of the present invention;

[0032] Figure 3 is a flow chart of another five-stage pipeline data processing method provided according to the second embodiment of the present invention;

[0033] Figure 4 is a flow chart of another five-stage pipeline data processing method provided according to Embodiment 3 of the present invention;

[0034] Figure 5 is a schematic diagram of a first-in-first-out table provided according to Embodiment 3 of the present invention;

[0035] Figure 6 is a flow chart of another five-stage pipeline data processing method provided according to the fourth embodiment of the present invention;

[0036] Figure 7 is a structural schematic diagram of a five-stage pipeline data processing device provided according to Embodiment 5 of the present invention;

[0037] Figure 8 is a structural schematic diagram of a five-stage pipeline structure provided according to Embodiment 6 of the present invention;

[0038] Fig. 9 It is a schematic diagram of the structure of an electronic device for implementing the five-stage pipeline data processing method of an embodiment of the present invention. DETAILED DESCRIPTION

[0039] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0040] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0041] Embodiment 1

[0042] Figure 1 A flowchart of a data processing method for a five-stage pipeline provided in Embodiment 1 of the present invention. This embodiment is applicable to the situation where each unit in the five-stage pipeline executes the current instruction according to the specified processing logic. The method can be executed by a data processing device of the five-stage pipeline. The data processing device of the five-stage pipeline can be implemented in the form of hardware and / or software. The data processing device of the five-stage pipeline can be configured in a computer or processor with data processing function.

[0043] like Figure 1 As shown, the method includes:

[0044] S110, through the decoding level unit, in each time cycle, according to the instruction information of the first current instruction and the preceding instruction in the decoding level unit, determine whether the first current instruction meets the dispatching condition, and dispatch the first current instruction that meets the dispatching condition to the execution level unit.

[0045] Wherein, determining whether the first current instruction meets the dispatch condition according to the instruction information of the first current instruction and the preceding instruction in the decoding level unit, and dispatching the first current instruction that meets the dispatch condition to the execution level unit includes:

[0046] When the decoding stage determines that all the preceding instructions are single-cycle instructions, the correlation between the first current instruction and the preceding instruction is not detected, and the first current instruction is dispatched to the execution stage unit;

[0047] When the decoding stage determines that there is a multi-cycle instruction in the preceding instruction, the correlation between the first current instruction and the preceding multi-cycle instructions is detected, and according to the detection result, the first current instruction that meets the dispatching condition is dispatched to the execution stage unit.

[0048] First, in order to better understand the technical solution of the present invention, a five-stage pipeline is briefly introduced here. Figure 2is a schematic diagram of an optional basic five-stage pipeline structure, such as Figure 2 As shown, the basic five-stage pipeline may include an instruction fetch unit, a decoding unit, an execution unit, a memory access unit, a write-back unit, and a general register stack for storing results. When an instruction needs to be executed and the execution result is stored, the instruction is first obtained by the instruction fetch unit, and is executed step by step in the order of the above units, and finally written back to the general register stack by the write-back unit. It should be understood that in actual engineering applications, the amount of instruction execution is very large. Therefore, in the same time period, in each level unit, corresponding data processing will be performed on different instructions.

[0049] Among them, the first current instruction may refer to an instruction in the decoding level unit that is ready to be dispatched to the execution level unit in the current time cycle. The predecessor instruction may refer to an instruction that the current unit (the decoding level unit in this step) dispatches to the next level unit at historical time and is still on the pipeline in the current time cycle. It can be understood that within a time cycle, the predecessor instruction of the first current instruction may refer to an instruction located in the execution level unit, the memory access level unit or the write-back level unit and the pipeline registers matched by each unit, and there may be multiple predecessor instructions of the first current instruction.

[0050] Optionally, the time cycle may refer to a preset time beat, for example, 1 millisecond, 10 milliseconds, etc. At each time beat, any unit in the pipeline executes an instruction processing operation.

[0051] Optionally, the instruction information may include whether the instruction is a single-cycle instruction or a multi-cycle instruction, and the correlation information between instructions. The correlation information may include read-before-write correlation, write-before-write correlation, and write-before-read correlation. However, in the five-stage pipeline structure of the present invention with sequential single-issue and out-of-order execution, the read-before-write correlation will not cause problems in logical operations. Therefore, the method provided by the present invention does not involve the read-before-write correlation.

[0052] Optionally, the dispatch conditions may include: when the predecessor instructions of the first current instruction are all single-cycle instructions, the first current instruction immediately satisfies the dispatch conditions; when there are multi-cycle instructions in the predecessor instructions of the first current instruction, the decoding level unit detects the correlation between the first current instruction and the predecessor multi-cycle instructions, the correlation includes RAW (Read After Write) correlation and WAW (Write After Write) correlation, and the predecessor multiple multi-cycle instructions may have RAW correlation and WAW correlation with the first current instruction respectively. When the first current instruction and the predecessor multi-cycle instructions can meet the requirements of direct dispatch, the first current instruction satisfies the dispatch conditions. The specific dispatch requirements between the first current instruction and the predecessor multi-cycle instructions will be described in detail in the following embodiments.

[0053] Optionally, single-cycle instructions are generally addition and subtraction instructions, which are calculated by the adder or subtractor in the execution level unit. Multi-cycle instructions can be multiplication and division instructions, or memory access instructions. The multiplication and division instructions can be calculated by the multiplier or divider in the execution level unit. The memory access instructions also need to be calculated in the execution level unit to resolve the memory access address. Generally, a computing component specifically for calculating memory access level instructions will be configured in the execution level unit.

[0054] S120. Through the execution level unit, in each time cycle, a logical operation is performed on at least one second current instruction in the execution level unit, and a logical operation result is obtained, and a target logical operation result currently submitted is determined in at least one logical operation result, and the target logical operation result is submitted to the execution memory access pipeline register.

[0055] Optionally, the execution level unit may include a plurality of logic operation components, such as an adder, a multiplier, a divider, etc. The logic operation components are used to operate on the instructions dispatched to the execution level unit to obtain operation results.

[0056] Optionally, the execution level unit may operate on logic operation instructions to obtain logic operation results of each logic operation instruction. The execution level unit may also operate on memory access instructions, and the operation result of the memory access instruction may be a memory access address.

[0057] Optionally, the second current instruction may refer to an instruction that is prepared to be operated in the execution level unit within the current time period. When the second current instruction is a logic operation instruction, that is, an addition and subtraction instruction or a multiplication and division instruction, a logic operation is performed on the second current instruction to obtain a logic operation result. However, there may also be a memory access level instruction in the execution level unit, and the memory access level instruction can perform memory access address operations in the execution level unit.

[0058] like Figure 2As shown, the five-stage pipeline includes an instruction fetch unit, a decoding unit, an execution unit, and a memory access unit, and also includes a pipeline register that matches it. The instruction fetch unit matches the instruction fetch decoding pipeline register, the decoding unit matches the decoding execution pipeline register, the execution unit can match the execution memory access pipeline register, the memory access unit can match the memory access write-back pipeline register, and the write-back unit can directly write the result back to the general register stack.

[0059] Optionally, only one instruction result can be stored in each pipeline register of the five-stage pipeline in the same time cycle.

[0060] Optionally, in the execution level unit, when addition and subtraction instructions and multiplication and division instructions are completed at the same time, the calculation results of the instructions can be submitted to the execution memory access pipeline register in order according to the order in which the two instructions are dispatched to the execution level unit. However, in general, since the multiplication and division instructions take a long time to operate, the multiplication and division instructions are dispatched to the execution level unit earlier than the two instructions that are completed at the same time.

[0061] S130. Determine, through the memory access stage unit, in each time period, the target instruction operation result that the memory access stage unit should currently obtain, and submit the obtained target instruction operation result to the memory access write-back pipeline register.

[0062] Optionally, it is determined that the target instruction that the memory access level unit should currently obtain may be a logic operation instruction or a memory access instruction.

[0063] The technical solution of the embodiment of the present invention can solve the resource conflict problem of the five-stage pipeline with sequential single issuance and out-of-order execution when there is a write-before-write dependency and a write-before-read dependency, and realize the order-preserving submission of the instructions of the execution stage unit and the memory access stage unit to the pipeline register, through the method that within each time cycle, the decoding stage unit dispatches the first current instruction that meets the dispatch conditions to the execution stage unit, the execution stage unit performs a logical operation on the second current instruction and submits the target logical operation result to the execution memory access pipeline register, and the memory access stage unit submits the target instruction operation result to the memory access write-back stage pipeline register.

[0064] Embodiment 2

[0065] Figure 3 This is a flow chart of another five-stage pipeline data processing method provided by the second embodiment of the present invention. Based on the above embodiment, this embodiment specifically describes the method of dispatching the first current instruction by the decoding stage unit. Figure 3 As shown, the method includes:

[0066] S210 , when the decoding stage determines that all the preceding instructions are single-cycle instructions, the correlation between the first current instruction and the preceding instructions is not detected, and the first current instruction is dispatched to the execution stage unit.

[0067] It can be understood that when the decoding level unit dispatches the first current instruction, if the preceding instructions in the pipeline are all single-cycle instructions, since the single-cycle instructions have a short calculation time, sequential issuance and sequential writing can be achieved. Therefore, there is no resource conflict problem and the first current instruction can be dispatched directly.

[0068] S220 , when it is determined through the decoding stage unit that there is no correlation between the first current instruction and the preceding multi-cycle instructions, the first current instruction is dispatched to the execution stage unit.

[0069] Optionally, when there is no correlation between the first current instruction and the preceding multi-cycle instructions, there is no resource conflict problem, and the first current instruction can be dispatched directly.

[0070] S230. When it is determined through the decoding level unit that the first current instruction has only a RAW correlation with the preceding multi-cycle instructions, the dispatching of the first current instruction is stopped, and the decoding level unit, the instruction fetch level unit, and the pipeline registers matching the decoding level unit and the instruction fetch level unit are blocked until the RAW correlation between the first current instruction and the preceding multi-cycle instructions is released, and then the first current instruction is dispatched to the execution level unit.

[0071] Among them, the decoding stage unit can be matched with the decoding execution pipeline register, and the instruction fetching stage unit can be matched with the instruction fetch decoding pipeline register.

[0072] Optionally, removing the RAW dependency between the first current instruction and each preceding multi-cycle instruction includes the following two situations: the result calculation of the multiplication and division instructions with RAW dependency in the execution level unit is completed and ready to be submitted to the execution memory access pipeline register, and the result preparation of the memory access instruction with RAW dependency in the memory access level unit is completed and ready to be submitted to the memory access write-back pipeline register.

[0073] S240 , when it is determined through the decoding stage unit that the first current instruction and the preceding multi-cycle instructions have only a write-before-write (WAW) correlation, determine whether the current instruction is a single-cycle instruction or a multi-cycle instruction.

[0074] S250. Through the decoding level unit, when it is determined that the first current instruction is a single-cycle instruction, the logical operation results of the preceding multiplication and division instructions with WAW correlation are submitted to the execution memory access pipeline register, and / or the memory access results of the preceding memory access instructions with WAW correlation are submitted to the memory access write-back pipeline register, and then the first current instruction is dispatched to the execution level unit.

[0075] S260 , when it is determined through the decoding stage unit that the first current instruction is a multi-cycle instruction, the first current instruction is dispatched to the execution stage unit.

[0076] S270. When it is determined through the decoding level unit that the first current instruction has both RAW correlation and WAW correlation with the preceding multiple multi-cycle instructions, if the first current instruction and the preceding multi-cycle instructions can satisfy the conditions for dispatching the first current instruction to the execution level unit, the first current instruction is dispatched to the execution level unit.

[0077] Among them, step S250 and step S260 are subordinate steps of step S240, and there is no necessary sequence relationship between step S250 and step S260. Except for step S250 and step S260, there is no necessary sequence relationship between other steps in this embodiment.

[0078] The technical solution of the embodiment of the present invention can solve the resource conflict problem caused by the dispatch order of the decoding stage unit by judging whether the first current instruction and the preceding instruction are single-cycle instructions, multi-cycle instructions and the correlation relationship between instructions under specified conditions. It has a simple design and higher versatility, and can effectively improve the performance of the five-stage pipeline.

[0079] Embodiment 3

[0080] Figure 4 This is a flowchart of another five-stage pipeline data processing method provided by the third embodiment of the present invention. Based on the above embodiment, this embodiment specifically describes the method for submitting the target logic operation result. Figure 4 As shown, the method includes:

[0081] S310. Perform a logic operation on at least one second current instruction in the execution level unit in each time period through the execution level unit, and obtain a logic operation result.

[0082] S320, determining, through the execution level unit, the order in which the instructions matching the results of the logic operations in the execution level unit are dispatched to the execution level unit, and whether the instructions are single-cycle instructions or multi-cycle instructions.

[0083] Optionally, each instruction dispatched by the memory access level unit to the execution level unit may have an ID (Identity Document), and the memory access level unit may record the dispatch order of each instruction through the ID. The execution level unit can determine the order in which each instruction is dispatched to the execution level unit by obtaining the ID of each instruction and the dispatch order stored in the memory access level unit.

[0084] S330. If it is determined through the execution level unit that only the logic operation result of the single-cycle instruction exists in the execution level unit, the logic operation result of the single-cycle instruction is determined as the target logic operation result.

[0085] It is understandable that for a single-cycle instruction, the logical operation must be completed in sequence. Therefore, only when there is only the logical operation result of the single-cycle instruction in the execution level unit, the logical operation result can be directly sent to the execution memory access pipeline register.

[0086] S340. If it is determined through the execution stage unit that there is at least one logic operation result of a multi-cycle instruction in the execution stage unit, the logic operation result of the multi-cycle instruction first dispatched to the execution stage unit is determined as the target logic operation result.

[0087] If it is determined that there is at least one logic operation result of a multi-cycle instruction in the execution stage unit, determining the logic operation result of the multi-cycle instruction first dispatched to the execution stage unit as the target logic operation result may include:

[0088] By the execution level unit, when there is a logic operation result of a multiplication instruction and a logic operation result of a division instruction in the execution level unit, a first-in-first-out table is obtained in the execution level unit;

[0089] Wherein, the FIFO table matches a set pointer, and the pointer points to the instruction row that is first written into the execution level unit in the FIFO table;

[0090] Obtaining, by the execution level unit, a tag value of a multiplication and division indicator in the instruction line currently pointed to by the pointer;

[0091] By executing the stage unit, when the tag value of the multiplication and division indicator matches the multiplication operation, determining the logic operation result of the multiplication instruction output by the multiplication operation module in the execution stage unit as the target logic operation result;

[0092] By executing the stage unit, when the tag value of the multiplication and division indicator matches the division operation, the logic operation result of the division instruction output by the division operation module in the execution stage unit is determined as the target logic operation result.

[0093] Figure 5 is a schematic diagram of an optional first-in-first-out table. Figure 5As shown, the FIFO table may include multiple entries, and the multi-cycle instructions may be stored in the FIFO table by row, and the 0th to 2nd bits may store the ID of each multi-cycle instruction; the 3rd bit may store the high and low bit indications of the multiplication result of each multi-cycle instruction, indicating that the multiplication instruction result corresponding to the entry takes the high bit or the low bit, the high bit is set to 1, and the low bit is set to 0; the 4th bit may store the division result indication of each multi-cycle instruction, indicating that the division operation result corresponding to the entry is the remainder or the quotient, the quotient is set to 0, and the remainder is set to 1; the 5th bit may store the multiplication type indication of each multi-cycle instruction, indicating that the instruction corresponding to the entry is a multiplication instruction of a signed number multiplied by an unsigned number, and the high bit of the signed number is 1, which is valid when it is 1; the 6th bit may store the multiplication and division indications of each multi-cycle instruction, indicating that the entry corresponds to a multiplication or division instruction, the multiplication instruction is set to 1, and the division instruction is set to 0.

[0094] Optionally, when the marker value of the multiplication and division indicator in the instruction line currently pointed to by the pointer is 1, it is determined to be a multiplication instruction; when the marker value is 0, it is determined to be a division instruction.

[0095] S350, submitting the target logic operation result to the execution memory access pipeline register.

[0096] Among them, step S330 and step S340 are subordinate steps of step S320, and there is no necessary sequence relationship between step S330 and step S340.

[0097] The technical solution of the embodiment of the present invention, when there are multiple logic operation results of multi-cycle instructions in the execution level unit, determines the instruction dispatch order according to a preset first-in-first-out table, and determines the target logic operation result accordingly, and submits the target logic operation result to the execution access pipeline register. This enables the execution level unit to submit multi-cycle instructions in order, solves the resource conflict problem, has a simple design and higher versatility, and can effectively improve the performance of the five-level pipeline.

[0098] Furthermore, through the execution level unit, when there is a non-multiplication and division instruction in the logic operation unit of the execution level unit, the source operand of the non-multiplication and division instruction is a bypass feedback signal, and within the current time cycle, there is also a logic operation result of a multiplication and division instruction in the execution level unit, the logic operation result of the non-multiplication and division instruction is stored in a register configured in the execution level unit, and the logic operation result of the multiplication and division instruction is submitted to the execution memory access pipeline register.

[0099] The bypass feedback signal may include a signal for executing a memory access pipeline register, a memory access write-back pipeline register, and / or a general register file feedback.

[0100] Embodiment 4

[0101] Figure 6 This is a flowchart of another five-stage pipeline data processing method provided by the fourth embodiment of the present invention. Based on the above embodiment, this embodiment specifically describes a method for the memory access stage unit to determine the target instruction operation result that the memory access stage unit should currently obtain. Figure 6 As shown, the method includes:

[0102] S410. If it is determined through the memory access stage unit that the memory access result of the memory access instruction does not exist in the current five-stage pipeline structure, the logical operation result in the memory access pipeline register is executed as the target instruction operation result.

[0103] S420. Through the memory access level unit, if it is determined that the memory access result of the memory access instruction exists in the current five-level pipeline structure, and the logical operation result of the single-cycle instruction is stored in the memory access pipeline register, the memory access result of the memory access instruction is used as the target instruction operation result, and the execution level unit, the memory access level unit, the instruction fetch level unit and the pipeline registers matching each unit are blocked within the current time cycle.

[0104] Among them, the execution level unit can be matched with the execution memory access pipeline register, and the memory access level unit can be matched with the memory access write-back pipeline register.

[0105] S430. If it is determined through the memory access level unit that there is a memory access result of the memory access instruction in the current five-level pipeline structure, and the logical operation result of the multiplication and division instruction is stored in the memory access pipeline register, the ID of the memory access instruction and the ID of the multiplication and division instruction are obtained.

[0106] S440, the memory access level unit determines the instruction that is first dispatched to the execution level unit among the memory access instructions and the multiplication and division logic instructions according to the ID of the memory access instruction, the ID of the multiplication and division instruction, and the queue information of the multi-cycle dispatch queue sent by the decoding level unit to the memory access level unit, and uses its operation result as the target instruction operation result.

[0107] S450, submitting the obtained target instruction operation result to the memory access write-back pipeline register.

[0108] Among them, step S440 is a subordinate step of step S430, and there is no necessary sequence relationship between steps S410, S420 and S430.

[0109] The technical solution of the embodiment of the present invention can achieve order-preserving submission of multi-cycle instructions by the memory access level unit and solve the resource conflict problem by determining the target instruction operation result among the instruction operation results that can be obtained by the memory access level unit. It has a simple design and higher versatility, and can effectively improve the performance of the five-stage pipeline.

[0110] Embodiment 5

[0111] Figure 7 The structure diagram of a five-stage pipeline data processing device provided in the fifth embodiment of the present invention is shown in FIG. Figure 7 As shown, the device includes: an instruction dispatching module 510, an instruction calculating module 520 and an operation result accessing module 530.

[0112] The instruction dispatch module 510 is used to determine whether the first current instruction meets the dispatch conditions through the decoding level unit in each time cycle based on the instruction information of the first current instruction and the previous instruction in the decoding level unit, and dispatch the first current instruction that meets the dispatch conditions to the execution level unit.

[0113] The instruction calculation module 520 is used to perform logical operations on at least one second current instruction in the execution level unit in each time cycle through the execution level unit, and obtain the logical operation result, and determine the currently submitted target logical operation result in at least one logical operation result, and submit the target logical operation result to the execution memory access pipeline register.

[0114] The operation result memory access module 530 is used to determine the target instruction operation result that the memory access level unit should currently obtain in each time cycle through the memory access level unit, and submit the obtained target instruction operation result to the memory access write-back pipeline register.

[0115] The technical solution of the embodiment of the present invention can solve the resource conflict problem of the five-stage pipeline with sequential single issuance and out-of-order execution when there is a write-before-write dependency and a write-before-read dependency, and realize the order-preserving submission of the instructions of the execution stage unit and the memory access stage unit to the pipeline register, through the method that within each time cycle, the decoding stage unit dispatches the first current instruction that meets the dispatch conditions to the execution stage unit, the execution stage unit performs a logical operation on the second current instruction and submits the target logical operation result to the execution memory access pipeline register, and the memory access stage unit submits the target instruction operation result to the memory access write-back stage pipeline register.

[0116] Based on the above embodiments, the instruction dispatch module 510 can be specifically used for:

[0117] When the decoding stage determines that all the preceding instructions are single-cycle instructions, the correlation between the first current instruction and the preceding instruction is not detected, and the first current instruction is dispatched to the execution stage unit;

[0118] When the decoding stage determines that there is a multi-cycle instruction in the preceding instruction, the correlation between the first current instruction and the preceding multi-cycle instructions is detected, and according to the detection result, the first current instruction that meets the dispatching condition is dispatched to the execution stage unit.

[0119] Based on the above embodiments, the instruction dispatch module 510 may be further specifically used for:

[0120] When it is determined by the decode stage unit that there is no correlation between the first current instruction and the preceding multi-cycle instructions, the first current instruction is dispatched to the execution stage unit;

[0121] When it is determined through the decoding stage unit that the first current instruction has only a write-before-read RAW correlation with each of the preceding multi-cycle instructions, the dispatching of the first current instruction is stopped, and the decoding stage unit, the fetch stage unit, and the pipeline registers matching the decoding stage unit and the fetch stage unit are blocked until the RAW correlation between the first current instruction and each of the preceding multi-cycle instructions is released, and the first current instruction is dispatched to the execution stage unit;

[0122] Among them, the decoding stage unit matches the decoding execution pipeline register, and the instruction fetching stage unit matches the instruction fetch decoding pipeline register;

[0123] When it is determined by the decoding level unit that the first current instruction and the preceding multi-cycle instructions have only a write-before-write (WAW) correlation, determining that the current instruction is a single-cycle instruction or a multi-cycle instruction;

[0124] When it is determined that the first current instruction is a single-cycle instruction, the decoder unit submits the logic operation result of the preceding multiplication and division instruction with WAW correlation to the execution memory access pipeline register, and / or submits the memory access result of the preceding memory access instruction with WAW correlation to the memory access write-back pipeline register, and then dispatches the first current instruction to the execution unit;

[0125] dispatching the first current instruction to the execution stage unit when determining, by the decode stage unit, that the first current instruction is a multi-cycle instruction;

[0126] Through the decoding level unit, when it is determined that the first current instruction has both RAW correlation and WAW correlation with the preceding multiple multi-cycle instructions, if the first current instruction and the preceding multi-cycle instructions can satisfy the conditions for dispatching the first current instruction to the execution level unit, the first current instruction is dispatched to the execution level unit.

[0127] Based on the above embodiments, the instruction calculation module 520 can be specifically used for:

[0128] Determining, through the execution level unit, the order in which the instructions matching the results of the logic operations in the execution level unit are dispatched to the execution level unit, and whether the instructions are single-cycle instructions or multi-cycle instructions;

[0129] If it is determined by the execution level unit that only the logic operation result of the single-cycle instruction exists in the execution level unit, the logic operation result of the single-cycle instruction is determined as the target logic operation result;

[0130] If it is determined through the execution stage unit that there is at least one logic operation result of a multi-cycle instruction in the execution stage unit, the logic operation result of the multi-cycle instruction first dispatched to the execution stage unit is determined as the target logic operation result.

[0131] Based on the above embodiments, the instruction calculation module 520 may be further specifically used for:

[0132] By the execution level unit, when there is a logic operation result of a multiplication instruction and a logic operation result of a division instruction in the execution level unit, a first-in-first-out table is obtained in the execution level unit;

[0133] Wherein, the FIFO table matches a set pointer, and the pointer points to the instruction row that is first written into the execution level unit in the FIFO table;

[0134] Obtaining, by the execution level unit, a tag value of a multiplication and division indicator in the instruction line currently pointed to by the pointer;

[0135] By executing the stage unit, when the tag value of the multiplication and division indicator matches the multiplication operation, determining the logic operation result of the multiplication instruction output by the multiplication operation module in the execution stage unit as the target logic operation result;

[0136] By executing the stage unit, when the tag value of the multiplication and division indicator matches the division operation, the logic operation result of the division instruction output by the division operation module in the execution stage unit is determined as the target logic operation result.

[0137] Based on the above embodiments, the operation result storage access module 530 can be specifically used for:

[0138] If it is determined through the memory access level unit that the memory access result of the memory access instruction does not exist in the current five-level pipeline structure, the logical operation result in the memory access pipeline register is executed as the target instruction operation result;

[0139] Through the memory access level unit, if it is determined that the memory access result of the memory access instruction exists in the current five-level pipeline structure, and the logical operation result of the single-cycle instruction is stored in the memory access pipeline register, the memory access result of the memory access instruction is used as the target instruction operation result, and the execution level unit, the memory access level unit, the instruction fetch level unit and the pipeline registers matching each unit are blocked in the current time cycle;

[0140] Among them, the execution level unit matches the execution memory access pipeline register, and the memory access level unit matches the memory access write-back pipeline register;

[0141] If it is determined through the memory access level unit that there is a memory access result of the memory access instruction in the current five-level pipeline structure, and the logic operation result of the multiplication and division instruction is stored in the memory access pipeline register, the ID of the memory access instruction and the ID of the multiplication and division instruction are obtained;

[0142] The memory access level unit determines the instruction that is first dispatched to the execution level unit among the memory access instructions and the multiplication and division logic instructions based on the ID of the memory access instruction, the ID of the multiplication and division instruction, and the queue information of the multi-cycle dispatch queue sent by the decoding level unit to the memory access level unit, and uses its calculation result as the target instruction calculation result.

[0143] On the basis of the above embodiments, a bypass feedback module may also be included, which is specifically used for:

[0144] By means of the execution level unit, when there is a non-multiplication and division instruction in the logic operation unit of the execution level unit, the source operand of the non-multiplication and division instruction is the bypass feedback signal, and in the current time cycle, there is also a logic operation result of a multiplication and division instruction in the execution level unit, the logic operation result of the non-multiplication and division instruction is stored in a register configured in the execution level unit, and the logic operation result of the multiplication and division instruction is submitted to the execution access memory pipeline register;

[0145] The bypass feedback signal includes a signal of executing a memory access pipeline register, a memory access write-back pipeline register and / or a general register file feedback.

[0146] The data processing device of the five-stage pipeline provided in the embodiment of the present invention can execute the data processing method of the five-stage pipeline provided in any embodiment of the present invention, and has the functional modules and beneficial effects corresponding to the execution method.

[0147] Embodiment 6

[0148] Figure 8 This is a schematic diagram of a five-stage pipeline structure provided by Embodiment 6 of the present invention. Figure 8 As shown, the five-stage pipeline structure includes an instruction fetch unit 610, a decode unit 620, an execution unit 630, a memory access unit 640, and a write-back unit 650. Among them:

[0149] The instruction fetch stage unit 610 is used to fetch instructions from the memory.

[0150] The decoding stage unit 620 , the execution stage unit 630 , and the memory access stage unit 640 are used to execute the five-stage pipeline data processing method described in any embodiment of the present invention.

[0151] Optionally, the instruction fetch level unit may include an instruction fetch decoding pipeline register 611, the decoding level unit may include a decoding execution pipeline register 621, the execution level unit may include an execution memory access pipeline register 631, and the memory access level unit may include a memory access write-back level pipeline register 641.

[0152] Among them, the execution level unit 630 is configured with a group of registers 632, and the registers are used to latch the logic operation results of non-multiplication and division instructions when there are logic operation results of non-multiplication and division instructions in the execution level unit and the bypass logic is enabled.

[0153] Specifically, register 632 can be used to latch the operation results of non-multiplication and division instructions when the non-multiplication and division instruction results are ready, the bypass logic is enabled, and the multiplication and division instruction results are also ready. The bypass feedback signal comes from the bypass feedback signal of the execution memory access pipeline register, the memory access write back pipeline register and / or the general register stack feedback.

[0154] Optionally, the five-stage pipeline structure may further include a general register stack 660 , which may be used to store operation results. The general register stack 660 may be a D flip-flop.

[0155] The write-back stage unit 650 is used to write the operation result back to the general register file 660 .

[0156] The five-stage pipeline structure also includes a system status register stack 670, which is used to store the operation results of system instructions.

[0157] The execution level unit 630 is further used to read system instructions and perform system instruction operations, and the write-back level unit 650 is further used to write the operation results of the system instructions back to the system status register file.

[0158] The technical solution of the embodiment of the present invention, by configuring a register group in the execution level unit in the five-level pipeline structure, configuring a system status register stack in the five-level pipeline structure, and utilizing the five-level pipeline structure proposed by the present invention to perform data processing, can solve the resource conflict problem of the five-level pipeline with sequential single issuance and out-of-order execution when there is a write-before-write dependency and a write-before-read dependency, and realize the order-preserving submission of instructions of the execution level unit and the memory access level unit to the pipeline register. The design is simple and has higher versatility, and can effectively improve the performance of the five-level pipeline.

[0159] Embodiment 7

[0160] Fig. 9A schematic diagram of the structure of an electronic device 10 that can be used to implement an embodiment of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.

[0161] like Fig. 9 As shown, the electronic device 10 includes at least one processor 11, and a memory connected to the at least one processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 to the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0162] A number of components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0163] The processor 11 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The processor 11 executes the various methods and processes described above, such as the data processing method of the five-stage pipeline described in the embodiment of the present invention. That is:

[0164] Through the decoding level unit, in each time cycle, according to the instruction information of the first current instruction and the preceding instruction in the decoding level unit, determining whether the first current instruction meets the dispatching condition, and dispatching the first current instruction that meets the dispatching condition to the execution level unit;

[0165] By means of the execution level unit, in each time cycle, a logic operation is performed on at least one second current instruction in the execution level unit, and a logic operation result is obtained, and a target logic operation result currently submitted is determined from at least one logic operation result, and the target logic operation result is submitted to the execution access memory pipeline register;

[0166] Through the memory access stage unit, in each time cycle, the target instruction operation result that the memory access stage unit should currently obtain is determined, and the obtained target instruction operation result is submitted to the memory access write-back pipeline register.

[0167] In some embodiments, the data processing method of the five-stage pipeline can be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 18. In some embodiments, part or all of the computer program can be loaded and / or installed on the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the data processing method of the five-stage pipeline described above can be performed. Alternatively, in other embodiments, the processor 11 can be configured to execute the data processing method of the five-stage pipeline in any other appropriate manner (for example, by means of firmware).

[0168] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0169] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0170] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in combination with an instruction execution system, device or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0171] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0172] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0173] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0174] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0175] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A five-stage pipeline data processing method, executed by a microprocessor having a five-stage pipeline structure, characterized in that: include: Determining, by the decoder unit, in each time period, whether the first current instruction meets a dispatch condition based on instruction information of the first current instruction and a preceding instruction in the decoder unit, and dispatching the first current instruction that meets the dispatch condition to the execution unit; Performing a logic operation on at least one second current instruction in the execution stage unit in each time cycle, obtaining a logic operation result, determining a currently submitted target logic operation result from the at least one logic operation result, and submitting the target logic operation result to an execution memory access pipeline register; The memory access stage unit determines the target instruction operation result that the memory access stage unit should currently obtain in each time cycle, and submits the obtained target instruction operation result to the memory access write-back pipeline register.

2. The method according to claim 1, characterized in that Determining whether the first current instruction meets a dispatch condition based on instruction information of a first current instruction and a preceding instruction in a decode-level unit, and dispatching the first current instruction that meets the dispatch condition to an execution-level unit, including: When the decode stage determines that all preceding instructions are single-cycle instructions, the first current instruction is dispatched to the execution stage unit without detecting the correlation between the first current instruction and the preceding instructions; When the decode stage determines that there is a multi-cycle instruction in the preceding instruction, the correlation between the first current instruction and the preceding multi-cycle instructions is detected, and according to the detection result, the first current instruction that meets the dispatching conditions is dispatched to the execution stage unit.

3. The method according to claim 2, characterized in that When determining that a multi-cycle instruction exists in a preceding instruction through a decoding stage, detecting a correlation between a first current instruction and each of the preceding multi-cycle instructions, and dispatching the first current instruction that meets the dispatching condition to an execution stage unit according to the detection result, including: dispatching the first current instruction to the execution stage unit when it is determined by the decode stage unit that there is no correlation between the first current instruction and the preceding multi-cycle instructions; When it is determined by the decode stage unit that the first current instruction has only a write-before-read RAW dependency with each of the preceding multi-cycle instructions, dispatching the first current instruction is stopped, and the decode stage unit, the instruction fetch stage unit, and pipeline registers matching the decode stage unit and the instruction fetch stage unit are blocked until the RAW dependencies between the first current instruction and each of the preceding multi-cycle instructions are removed, and then the first current instruction is dispatched to the execute stage unit; Among them, the decode stage unit matches the decode execution pipeline register, and the finger fetch stage unit matches the finger fetch decode pipeline register; The RAW dependency between the first current instruction and each preceding multi-cycle instruction is removed, including: if there is a RAW dependency between the first current instruction and a multiplication or division instruction in an execution-level unit, upon detecting that a logic operation result of the multiplication or division instruction with the RAW dependency in the execution-level unit is ready to be dispatched to an execution memory access pipeline register, determining that the RAW dependency between the first current instruction and the preceding multi-cycle instruction in the execution-level unit is removed; if there is a RAW dependency between the first current instruction and a memory access instruction in the memory access level unit, upon detecting that a logic operation result of the memory access instruction with the RAW dependency in the memory access level unit is ready to be dispatched to a memory access write-back pipeline register, determining that the RAW dependency between the first current instruction and the preceding multi-cycle instruction in the memory access level unit is removed; When it is determined by the decoding stage unit that the first current instruction and the preceding multi-cycle instructions have only a write-before-write (WAW) dependency, determining whether the current instruction is a single-cycle instruction or a multi-cycle instruction; When determining, by the decode stage unit, that the first current instruction is a single-cycle instruction, submitting a logical operation result of a preceding multiplication or division instruction with WAW dependency to an execution memory access pipeline register and / or submitting a memory access result of a preceding memory access instruction with WAW dependency to a memory access write-back pipeline register, the first current instruction is dispatched to the execution stage unit; dispatching the first current instruction to the execution stage unit when determining, by the decode stage unit, that the first current instruction is a multi-cycle instruction; Through the decoding level unit, when it is determined that the first current instruction has both RAW correlation and WAW correlation with the preceding multiple multi-cycle instructions, if the first current instruction and the preceding multi-cycle instructions can meet the conditions for dispatching the first current instruction to the execution level unit, the first current instruction will be dispatched to the execution level unit.

4. The method according to claim 1, wherein Determining, by executing the level unit, a currently submitted target logic operation result from at least one logic operation result, including: Determining, through the execution stage unit, the order in which instructions matching the results of the logic operations in the execution stage unit are dispatched to the execution stage unit, and whether the instructions are single-cycle instructions or multi-cycle instructions; If it is determined by the execution level unit that only the logic operation result of the single-cycle instruction exists in the execution level unit, the logic operation result of the single-cycle instruction is determined as the target logic operation result; If it is determined by the execution stage unit that there is at least one logic operation result of a multi-cycle instruction in the execution stage unit, the logic operation result of the multi-cycle instruction first dispatched to the execution stage unit is determined as the target logic operation result.

5. The method according to claim 4, characterized in that If it is determined that there is at least one logic operation result of a multi-cycle instruction in the execution stage unit, the logic operation result of the multi-cycle instruction first dispatched to the execution stage unit is determined as the target logic operation result, including: By the execution level unit, when there is a logic operation result of a multiplication instruction and a logic operation result of a division instruction in the execution level unit, a first-in-first-out table is obtained in the execution level unit; wherein the first-in-first-out table matches a set pointer, the pointer pointing to the instruction row first written into the execution level unit in the first-in-first-out table; Obtaining, through the execution level unit, a tag value of a multiplication and division indicator in an instruction line currently pointed to by a pointer; By executing the stage unit, when the tag value of the multiplication and division indicator matches the multiplication operation, determining the logic operation result of the multiplication instruction output by the multiplication operation module in the execution stage unit as the target logic operation result; By executing the stage unit, when the tag value of the multiplication and division indicator matches the division operation, the logic operation result of the division instruction output by the division operation module in the execution stage unit is determined as the target logic operation result.

6. The method according to claim 1, wherein The memory access level unit determines the target instruction operation result that the memory access level unit should currently obtain in each time cycle, including: If it is determined through the memory access stage unit that the memory access result of the memory access instruction does not exist in the current five-stage pipeline structure, the logical operation result in the memory access pipeline register is executed as the target instruction operation result; Through the memory access level unit, if it is determined that the memory access result of the memory access instruction exists in the current five-stage pipeline structure, and the logical operation result of the single-cycle instruction is stored in the memory access pipeline register, the memory access result of the memory access instruction is used as the target instruction operation result, and the execution level unit, the memory access level unit, the instruction fetch level unit and the pipeline registers matching each unit are blocked in the current time cycle; Among them, the execution level unit matches the execution memory access pipeline register, and the memory access level unit matches the memory access write-back pipeline register; If it is determined through the memory access level unit that a memory access result of a memory access instruction exists in the current five-stage pipeline structure, and a logical operation result of a multiplication or division instruction is stored in the memory access pipeline register, an identification number ID of the memory access instruction and an ID of the multiplication or division instruction are obtained; The memory access level unit determines the instruction that is first dispatched to the execution level unit among the memory access instruction and the multiplication and division logic instruction based on the ID of the memory access instruction, the ID of the multiplication and division instruction, and the queue information of the multi-cycle dispatch queue sent by the decoding level unit to the memory access level unit, and uses its calculation result as the target instruction calculation result.

7. The method according to claim 1, characterized in that Also includes: When a non-multiplication / division instruction exists in a logic operation unit of the execution stage unit, a source operand of the non-multiplication / division instruction is a bypass feedback signal, and a logic operation result of a multiplication / division instruction also exists in the execution stage unit within a current time cycle, the logic operation result of the non-multiplication / division instruction is stored in a register configured in the execution stage unit, and the logic operation result of the multiplication / division instruction is submitted to the execution memory access pipeline register; The bypass feedback signal includes a signal fed back from executing a memory access pipeline register, a memory access write-back pipeline register, and / or a general register file.

8. A five-stage pipeline data processing device, executed by a microprocessor having a five-stage pipeline structure, characterized in that: include: an instruction dispatch module, configured to determine, through the decoder-stage unit, in each time period, based on the instruction information of the first current instruction and the preceding instruction in the decoder-stage unit, whether the first current instruction meets the dispatch condition, and dispatch the first current instruction that meets the dispatch condition to the execution-stage unit; an instruction calculation module, configured to perform a logic operation on at least one second current instruction in the execution stage unit in each time cycle through the execution stage unit, obtain a logic operation result, determine a currently submitted target logic operation result from the at least one logic operation result, and submit the target logic operation result to the execution access pipeline register; The operation result memory access module is used to determine the target instruction operation result that the memory access level unit should currently obtain through the memory access level unit in each time cycle, and submit the obtained target instruction operation result to the memory access write-back pipeline register.

9. A five-stage pipeline structure, characterized in that: include: fetch-level unit, decode-level unit, execute-level unit, memory-access-level unit, and write-back-level unit; The instruction fetch unit is used to fetch instructions from memory; The decoding level unit, the execution level unit and the memory access level unit are used to execute the five-level pipeline data processing method according to any one of claims 1 to 7; The execution level unit is provided with a group of registers, which are used to latch the logic operation results of the non-multiplication and division instructions when the logic operation results of the non-multiplication and division instructions exist in the execution level unit and the bypass logic is enabled; The write-back stage unit is used to write the operation result back to the general register file; Among them, the five-stage pipeline structure also includes a general register file, which is used to store operation results. The general register file uses D flip-flops; The five-stage pipeline structure further includes a system status register stack, which is used to store the operation results of system instructions; The execution level unit is further used to read system instructions and perform system instruction operations, and the write-back level unit is further used to write the operation results of the system instructions back to the system status register stack.

10. An electronic device, characterized in that: The electronic device comprises: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the five-stage pipeline data processing method according to any one of claims 1 to 7 of the present invention.

11. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the five-stage pipeline data processing method according to any one of claims 1 to 7 when executed.

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