Bidirectional time delay circuit and electronic equipment
By using the current mirror module and the switching module to control the current of the current source in the bidirectional delay circuit, the preset delay of the capacitor reaches the flip threshold of the inverter, solving the circuit complexity and the number of current sources in the prior art The problem has achieved the streamlining of circuit design and the reduction of layout.
Patent Information
- Application Number
- CN202411172398.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-23
- Publication Date
- 2024-12-17
AI Technical Summary
The existing bidirectional delay circuit requires two current sources and at least one capacitor, which increases the complexity of the circuit and the requirements for active inputs. How to reduce the number of current sources has become an urgent problem.
By using a current source, a capacitor, inverter, current mirror module and switch module in a bidirectional delay circuit, the current provided by the current source passes through the current mirror module or switch module to the first end of the capacitor to achieve the pre-capacitor Suppose the delay reaches the inverter's flip threshold, thereby achieving flip of the output voltage.
The circuit design is reduced and the layout is reduced. The delay of rising and falling edge signals is achieved by only one current source and one capacitor, reducing circuit complexity and the requirements for active inputs.
Smart Images
Figure CN119154843A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present disclosure relate to the field of integrated circuit technology, and in particular to a bidirectional delay circuit and electronic equipment. Background Art
[0002] In the field of integrated circuits, it is usually necessary to perform bidirectional delay processing on signals, and the bidirectional delay is usually achieved by charging the capacitor with current, using a charging current source and a discharging current source, with one or two capacitors and several inverters.
[0003] However, two current sources and at least one capacitor will increase the complexity of the circuit and the requirements for active input. How to reduce the number of current sources has become a technical problem that needs to be solved urgently in bidirectional delay circuits. Summary of the invention
[0004] In view of this, the embodiments of the present disclosure provide a bidirectional delay circuit and an electronic device to solve or alleviate the above problems.
[0005] According to an embodiment of the present disclosure, a bidirectional delay circuit is provided, including: a current source, a capacitor, an inverter, a current mirror module and a switch module, wherein an input voltage passes through the inverter to an output voltage, a first end of the capacitor is connected to an input end of the inverter, and a second end of the capacitor is grounded; according to the opening and closing of the switch module and the current mirror module, the current provided by the current source is controlled to pass through the current mirror module or the switch module to the first end of the capacitor; when the input voltage is flipped, by controlling the opening and closing of the switch module and the current mirror module, the first end of the capacitor reaches the flip threshold of the inverter after a preset delay, thereby realizing the flip of the output voltage.
[0006] According to an embodiment of the present disclosure, an electronic device is provided, comprising the above-mentioned bidirectional delay circuit.
[0007] In the solution of the embodiment of the present disclosure, by turning on and off the switch module and the current mirror module, the first end of the capacitor can reach the flip threshold of the inverter after a preset delay. The bidirectional delay circuit can simultaneously delay the rising edge signal and the falling edge signal, and only includes a current source and a capacitor, that is, a time-limited bidirectional delay, thereby simplifying the circuit design and reducing the circuit layout. BRIEF DESCRIPTION OF THE DRAWINGS
[0008] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.
[0009] Figure 1 A circuit diagram of a bidirectional delay circuit according to an embodiment of the present disclosure;
[0010] Figure 2 for Figure 1 Signal waveforms of key nodes of bidirectional delay circuit;
[0011] Figure 3 A circuit diagram of a bidirectional delay circuit according to another embodiment of the present disclosure;
[0012] Figure 4 for Figure 3 Signal waveforms of key nodes in a bidirectional delay circuit. DETAILED DESCRIPTION
[0013] In order to enable those skilled in the art to better understand the technical solutions in the embodiments of the present disclosure, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all of the embodiments. All other embodiments obtained by ordinary technicians in the field based on the embodiments in the embodiments of the present disclosure should fall within the scope of protection of the embodiments of the present disclosure.
[0014] The specific implementation of the embodiment of the present disclosure is further explained below in conjunction with the accompanying drawings of the embodiment of the present disclosure.
[0015] In the design of integrated circuits, it is often necessary to perform bidirectional delay processing on signals. For example, when designing the under voltage lockout (UVLO) function of a power supply product, it is generally required to perform deburring processing on the entry or exit of the under voltage lockout function to achieve the circuit system's anti-interference ability against power supply voltage jitter. At this time, it is necessary to perform delay processing on the rising and falling edges of the output logic of the under voltage lockout module.
[0016] Generally, the delay is achieved by charging the capacitor with current. Based on this, the delay of the conventional rising edge and falling edge requires a charging current source and a discharging current source with one or two capacitors and several inverters. However, two current sources and at least one capacitor will increase the complexity of the circuit and the requirements for active input.
[0017] In order to at least partially overcome the above-mentioned disadvantages, see Figure 1The embodiment of the present disclosure provides a bidirectional delay circuit, including: a current source, a capacitor, an inverter, a current mirror module and a switch module, the input voltage passes through the inverter to the output voltage, the first end of the capacitor is connected to the input end of the inverter, and the second end of the capacitor is grounded. According to the opening and closing of the switch module and the current mirror module, the current provided by the current source is controlled to pass through the current mirror module or the switch module to the first end of the capacitor. When the input voltage is reversed, by controlling the opening and closing of the switch module and the current mirror module, the first end of the capacitor reaches the flip threshold of the inverter after a preset delay, thereby realizing the flip of the output voltage.
[0018] In the solution of the embodiment of the present disclosure, by turning on and off the switch module and the current mirror module, the first end of the capacitor can reach the flip threshold of the inverter after a preset delay. The embodiment of the present disclosure only includes one current source and one capacitor, that is, a time-limited bidirectional delay, thereby simplifying the circuit design and reducing the circuit layout.
[0019] In some specific implementations of the embodiments of the present disclosure, when the switch module is turned off, the current mirror module is turned on, and the current provided by the current source passes through the current mirror module to the first end of the capacitor. When the switch module is turned on, the current mirror module is turned off, and the current provided by the current source passes through the switch module to the first end of the capacitor.
[0020] In some specific implementations of the embodiments of the present disclosure, see Figure 1 The current mirror module includes: a first PMOS tube PMOS1, a second PMOS tube PMOS2, a third PMOS tube PMOS3, and a fourth PMOS tube PMOS4.
[0021] The third PMOS transistor PMOS3 and the fourth PMOS transistor PMOS4 are turned on, so that the current of the current source passes through the third PMOS transistor PMOS3, the first PMOS transistor PMOS1, the second PMOS transistor PMOS2, and the fourth PMOS transistor PMOS4 and is mirrored to the first end of the capacitor.
[0022] The disclosed embodiment realizes current source current mirror transmission through a current mirror module, simplifies circuit design, and the circuit layout area occupied by the PMOS tube is small, and the area of the circuit layout will not be increased.
[0023] In some specific implementations of the embodiments of the present disclosure, the gates of the third PMOS tube PMOS3 and the fourth PMOS tube PMOS4 are connected and connected to the switch module, the gates of the first PMOS tube PMOS1 and the second PMOS tube PMOS2 are connected and connected to the source of the third PMOS tube PMOS3, the sources of the first PMOS tube PMOS1 and the second PMOS tube PMOS2 are connected and connected to the operating voltage, the drain of the first PMOS tube PMOS1 is connected to the source of the third PMOS tube PMOS3, the drain of the second PMOS tube PMOS2 is connected to the source of the fourth PMOS tube PMOS4, the drain of the third PMOS tube PMOS3 is connected to the current source, the drain of the fourth PMOS tube PMOS4 is connected to the current source through the switch module, and the drain of the fourth PMOS tube PMOS4 is also connected to the first end of the capacitor.
[0024] The embodiment of the present disclosure uses the above circuit connection method to realize the opening and closing of the current mirror module and the switch module, reducing one current source without increasing the circuit layout area and simplifying the circuit design.
[0025] In some specific implementations of the embodiments of the present disclosure, the switch module is a first NMOS tube NMOS1, the gate of the first NMOS tube NMOS1 is respectively connected to the gates of the third PMOS tube PMOS3 and the fourth PMOS tube PMOS4, the drain of the first NMOS tube NMOS1 is respectively connected to the drain of the fourth PMOS tube PMOS4 and the first end of the capacitor, and the source of the first NMOS tube NMOS1 is connected to the current source.
[0026] The present disclosure adopts the first NMOS tube NMOS1 to implement the switch module, thereby utilizing the switch characteristics of NMOS and further avoiding the increase of the circuit layout area.
[0027] Specifically, see Figure 1 as well as Figure 2 When the input voltage VIN1 is at a low level, the first NMOS tube NMOS1 is turned off, the third PMOS tube PMOS3 and the fourth PMOS tube PMOS4 are turned on, and the current I1 of the current source passes through the third PMOS tube PMOS3, the first PMOS tube PMOS1, the second PMOS tube PMOS2, and the fourth PMOS tube PMOS4 to pull up the voltage VE at the first end of the capacitor C1, and the output voltage VOUT1 is a low voltage.
[0028] When the input voltage VIN1 flips from a low level to a high level, the first NMOS tube NMOS1 is turned on, the third PMOS tube PMOS3 and the fourth PMOS tube PMOS4 are turned off, and the current I1 of the current source discharges the capacitor C1 through the first NMOS tube NMOS1. After a rising preset delay Tdly_r, the voltage VE at the first end of the capacitor C1 drops to the flip threshold of the inverter INV4, and the output voltage VOUT1 flips from a low level to a high level.
[0029] When the input voltage VIN1 flips from a high level to a low level, the first NMOS tube NMOS1 is turned off, the third PMOS tube PMOS3 and the fourth PMOS tube PMOS4 are turned on, and the current I1 of the current source charges the capacitor C1 through the third PMOS tube PMOS3, the first PMOS tube PMOS1, the second PMOS tube PMOS2, and the fourth PMOS tube PMOS4. After a preset delay Tdly_f, the voltage VE at the first end of the capacitor C1 rises to the flip threshold of the inverter INV4, and the output voltage VOUT1 flips from a high level to a low level.
[0030] The preset rising delay Tdly_r is determined according to the flip threshold of the inverter, the capacitance value of the capacitor, the operating voltage, and the current of the current source.
[0031] Specifically, the preset rising delay Tdly_r=C1*(VDD-VTHINV4) / I1, wherein C1 is the capacitance value of the capacitor, VDD is the operating voltage, VTHINV4 is the flip threshold of the inverter, and I1 is the current of the current source.
[0032] The preset falling delay Tdly_f is determined according to the flip threshold of the inverter, the capacitance value, the width-to-length ratio of the first PMOS tube PMOS1 and the second PMOS tube PMOS2, and the current of the current source.
[0033] Specifically, the falling preset delay Tdly_f=C1*VTHINV4 / [(W / L)MP2 / (W / L)MP1*I1], wherein C1 is the capacitance value of the capacitor, VDD is the operating voltage, VTHINV4 is the flip threshold of the inverter, I1 is the current of the current source, (W / L)MP2 is the width-to-length ratio of the second PMOS tube PMOS2, and (W / L)MP1 is the width-to-length ratio of the first PMOS tube PMOS1.
[0034] In some specific implementations of the embodiments of the present disclosure, see Figure 3 The current mirror module includes: a second NMOS tube NMOS2, a third NMOS tube NMOS3, a fourth NMOS tube NMOS4, and a fifth NMOS tube NMOS5.
[0035] The second NMOS transistor NMOS2 and the third NMOS transistor NMOS3 are turned on, so that the current of the current source is mirrored to the first end of the capacitor through the second NMOS transistor NMOS2, the fourth NMOS transistor NMOS4, the fifth NMOS transistor NMOS5 and the third NMOS transistor NMOS3.
[0036] The disclosed embodiment realizes current source current mirror transmission through a current mirror module, simplifies circuit design, and the circuit layout area occupied by the NMOS tube is small, and the area of the circuit layout will not be increased.
[0037] In some specific implementations of the embodiments of the present disclosure, the gates of the second NMOS tube NMOS2 and the third NMOS tube NMOS3 are connected and connected to the switch module, the gates of the fourth NMOS tube NMOS4 and the fifth NMOS tube NMOS5 are connected and connected to the source of the second NMOS tube NMOS2, the sources of the fourth NMOS tube NMOS4 and the fifth NMOS tube NMOS5 are connected and grounded, the drain of the fourth NMOS tube NMOS4 is connected to the source of the second NMOS tube NMOS2, the drain of the fifth NMOS tube NMOS5 is connected to the source of the third NMOS tube NMOS3, the drain of the second NMOS tube NMOS2 is connected to the current source, the drain of the third NMOS tube NMOS3 is connected to the current source through the switch module, and the drain of the third NMOS tube NMOS3 is also connected to the first end of the capacitor.
[0038] The embodiment of the present disclosure uses the above circuit connection method to realize the opening and closing of the current mirror module and the switch module, reducing one current source without increasing the circuit layout area and simplifying the circuit design.
[0039] In some specific implementations of the embodiments of the present disclosure, the switch module is a fifth PMOS tube PMOS5, the gate of the fifth PMOS tube PMOS5 is respectively connected to the gates of the second NMOS tube NMOS2 and the third NMOS tube NMOS3, the drain of the fifth PMOS tube PMOS5 is respectively connected to the drain of the third NMOS tube NMOS3 and the first end of the capacitor, and the source of the fifth PMOS tube PMOS5 is connected to the current source.
[0040] The present disclosure adopts the fifth PMOS tube PMOS5 to implement the switch module, thereby utilizing the switch characteristics of PMOS and further avoiding the increase of the circuit layout area.
[0041] Specifically, see Figure 3 as well as Figure 4When the input voltage VIN2 is at a low level, the fifth PMOS tube PMOS5 is turned on, the second NMOS tube NMOS2 and the third NMOS tube NMOS3 are turned off, the current I1 of the current source passes through the fifth PMOS tube PMOS5 to pull up the voltage VF at the first end of the capacitor C2, and the output voltage VOUT2 is a low voltage.
[0042] When the input voltage VIN2 flips from a low level to a high level, the fifth PMOS tube PMOS5 is turned off, the second NMOS tube NMOS2 and the third NMOS tube NMOS3 are turned on, and the current I1 of the current source discharges the capacitor C2 through the second NMOS tube NMOS2, the fourth NMOS tube NMOS4, the fifth NMOS tube NMOS5, and the third NMOS tube NMOS3. After rising for a preset delay Tdly_r, the voltage VF at the first end of the capacitor C2 drops to the flip threshold of the inverter INV5, and the output voltage VOUT2 flips from a low level to a high level.
[0043] When the input voltage VIN2 flips from a high level to a low level, the fifth PMOS tube PMOS5 is turned on, the second NMOS tube NMOS2 and the third NMOS tube NMOS3 are turned off, and the current I1 of the current source charges the capacitor C2 through the fifth PMOS tube PMOS5. After a preset delay Tdly_f, the voltage VF at the first end of the capacitor C2 rises to the flip threshold of the inverter INV5, and the output voltage VOUT2 flips from a high level to a low level.
[0044] The preset rising delay Tdly_r is determined according to the flip threshold of the inverter, the capacitance value, the width-to-length ratio of the fourth NMOS tube NMOS4 and the fifth NMOS tube NMOS5, the operating voltage, and the current of the current source.
[0045] Specifically, Tdly_r=C2*(VDD-VTHINV5) / [(W / L)MN5 / (W / L)MN4*I2], wherein C2 is the capacitance value of the capacitor, VDD is the operating voltage, VTHINV5 is the flip threshold of the inverter, I2 is the current of the current source, (W / L)MP2 is the width-to-length ratio of the fourth NMOS tube NMOS4, and (W / L)MN5 is the width-to-length ratio of the fifth NMOS tube NMOS5.
[0046] The falling preset delay Tdly_f is determined according to the flip threshold of the inverter, the capacitance value, and the current of the current source.
[0047] Specifically, Tdly_f=C2*VTHINV5 / I2, where C2 is the capacitance value of the capacitor, VDD is the operating voltage, VTHINV5 is the flip threshold of the inverter, and I2 is the current of the current source.
[0048] An embodiment of the present disclosure also provides an electronic device, comprising any of the above-mentioned bidirectional delay circuits.
[0049] The expressions "first", "second", "first" or "second" used in various embodiments of the present disclosure may modify various components regardless of order and / or importance, but these expressions do not limit the corresponding components. The above expressions are only configured for the purpose of distinguishing an element from other elements. For example, a first user device and a second user device represent different user devices, although both are user devices. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present disclosure.
[0050] When one element (e.g., a first element) is referred to as being "(operably or communicatively) coupled" or "(operably or communicatively) coupled to" or "connected to" another element (e.g., a second element), it is understood that the one element is directly connected to the other element or the one element is indirectly connected to the other element via yet another element (e.g., a third element). Conversely, it is understood that when an element (e.g., a first element) is referred to as being "directly connected" or "directly coupled" to another element (the second element), no element (e.g., a third element) is interposed between the two.
[0051] The above description is only a preferred embodiment of the present disclosure and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present disclosure is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above invention concept. For example, the above features are replaced with the technical features with similar functions disclosed in the present disclosure (but not limited to) by each other.
Claims
1. A bidirectional delay circuit, comprising: A current source, a capacitor, an inverter, a current mirror module and a switch module, the input voltage passes through the inverter to the output voltage, the first end of the capacitor is connected to the input end of the inverter, and the second end of the capacitor is grounded, According to the opening and closing of the switch module and the current mirror module, control the current provided by the current source to pass through the current mirror module or the switch module to the first end of the capacitor; When the input voltage is reversed, the switch module and the current mirror module are controlled to be turned on and off so that the first end of the capacitor reaches the reverse threshold of the inverter after a preset delay, thereby realizing the reversal of the output voltage.
2. The bidirectional delay circuit according to claim 1, wherein: When the switch module is turned off, the current mirror module is turned on, and the current provided by the current source passes through the current mirror module to the first end of the capacitor; when the switch module is turned on, the current mirror module is turned off, and the current provided by the current source passes through the switch module to the first end of the capacitor.
3. The bidirectional delay circuit according to claim 2, wherein: The current mirror module includes: a first PMOS tube, a second PMOS tube, a third PMOS tube, and a fourth PMOS tube. The third PMOS tube and the fourth PMOS tube are turned on, so that the current of the current source passes through the third PMOS tube, the first PMOS tube, the second PMOS tube, and the fourth PMOS tube and is mirrored to the first end of the capacitor.
4. The bidirectional delay circuit according to claim 3, wherein: The gates of the third PMOS tube and the fourth PMOS tube are connected and connected to the switch module, the gates of the first PMOS tube and the second PMOS tube are connected and connected to the source of the third PMOS tube, the sources of the first PMOS tube and the second PMOS tube are connected and connected to the working voltage, the drain of the first PMOS tube is connected to the source of the third PMOS tube, the drain of the second PMOS tube is connected to the source of the fourth PMOS tube, the drain of the third PMOS tube is connected to the current source, the drain of the fourth PMOS tube is connected to the current source through the switch module, and the drain of the fourth PMOS tube is also connected to the first end of the capacitor.
5. The bidirectional delay circuit according to claim 1, wherein: The switch module is a first NMOS tube, a gate of the first NMOS tube is respectively connected to the gates of the third PMOS tube and the fourth PMOS tube, a drain of the first NMOS tube is respectively connected to the drain of the fourth PMOS tube and the first end of the capacitor, and a source of the first NMOS tube is connected to the current source.
6. The bidirectional delay circuit according to claim 5, wherein: When the input voltage is at a low level, the first NMOS tube is turned off, the third PMOS tube and the fourth PMOS tube are turned on, the current of the current source passes through the third PMOS tube, the first PMOS tube, the second PMOS tube, and the fourth PMOS tube to pull up the voltage of the first end of the capacitor, and the output voltage is a low voltage; When the input voltage flips from a low level to a high level, the first NMOS tube is turned on, the third PMOS tube and the fourth PMOS tube are turned off, the current of the current source discharges the capacitor through the first NMOS tube, and after a preset delay, the voltage at the first end of the capacitor drops to the flip threshold of the inverter, and the output voltage flips from a low level to a high level; When the input voltage flips from a high level to a low level, the first NMOS tube is turned off, the third PMOS tube and the fourth PMOS tube are turned on, and the current of the current source charges the capacitor through the third PMOS tube, the first PMOS tube, the second PMOS tube, and the fourth PMOS tube. After a preset delay in falling, the voltage at the first end of the capacitor rises to the flip threshold of the inverter, and the output voltage flips from a high level to a low level.
7. The method according to claim 5, wherein: The preset rising delay is determined according to the flipping threshold of the inverter, the capacitance value, the operating voltage, and the current of the current source; the preset falling delay is determined according to the flipping threshold of the inverter, the capacitance value, the width-to-length ratio of the first PMOS tube and the second PMOS tube, and the current of the current source.
8. The bidirectional delay circuit according to claim 1, wherein: The current mirror module includes: a second NMOS tube, a third NMOS tube, a fourth NMOS tube, and a fifth NMOS tube. The second NMOS tube and the third NMOS tube are turned on, so that the current of the current source passes through the second NMOS tube, the fourth NMOS tube, the fifth NMOS tube, and the third NMOS tube and is mirrored to the first end of the capacitor.
9. The bidirectional delay circuit according to claim 8, wherein: The gates of the second NMOS tube and the third NMOS tube are connected and connected to the switch module, the gates of the fourth NMOS tube and the fifth NMOS tube are connected and connected to the source of the second NMOS tube, the sources of the fourth NMOS tube and the fifth NMOS tube are connected and grounded, the drain of the fourth NMOS tube is connected to the source of the second NMOS tube, the drain of the fifth NMOS tube is connected to the source of the third NMOS tube, the drain of the second NMOS tube is connected to the current source, the drain of the third NMOS tube is connected to the current source through the switch module, and the drain of the third NMOS tube is also connected to the first end of the capacitor.
10. The bidirectional delay circuit according to claim 9, wherein: The switch module is a fifth PMOS tube, a gate of the fifth PMOS tube is respectively connected to the gates of the second NMOS tube and the third NMOS tube, a drain of the fifth PMOS tube is respectively connected to the drain of the third NMOS tube and the first end of the capacitor, and a source of the fifth PMOS tube is connected to the current source.
11. The bidirectional delay circuit according to claim 10, wherein: When the input voltage is at a low level, the fifth PMOS tube is turned on, the second NMOS tube and the third NMOS tube are turned off, the current of the current source passes through the fifth PMOS tube to pull up the voltage of the first end of the capacitor, and the output voltage is a low voltage; When the input voltage flips from a low level to a high level, the fifth PMOS tube is turned off, the second NMOS tube and the third NMOS tube are turned on, and the current of the current source discharges the capacitor through the second NMOS tube, the fourth NMOS tube, the fifth NMOS tube, and the third NMOS tube. After a preset delay in rising, the voltage at the first end of the capacitor drops to the flip threshold of the inverter, and the output voltage flips from a low level to a high level. When the input voltage flips from a high level to a low level, the fifth PMOS tube is turned on, the second NMOS tube and the third NMOS tube are turned off, the current of the current source charges the capacitor through the fifth PMOS tube, and after a preset delay, the voltage at the first end of the capacitor rises to the flip threshold of the inverter, and the output voltage flips from a high level to a low level.
12. The bidirectional delay circuit according to claim 11, wherein: The preset rising delay is determined according to the flipping threshold of the inverter, the capacitance value, the width-to-length ratio of the fourth NMOS tube and the fifth NMOS tube, the operating voltage, and the current of the current source; the preset falling delay is determined according to the flipping threshold of the inverter, the capacitance value, and the current of the current source.
13. An electronic device comprising the bidirectional delay circuit according to any one of claims 1 to 12.