Grid driving chip with multiplexing programmable trimming port

Abstract

The circuit comprises a low-side circuit and a high-side circuit. The low-side circuit comprises an input interface part, a low-side circuit monitoring and protecting part and an output interface part II; the low-side circuit monitoring and protecting part is formed by sequentially connecting a temperature sensing circuit with a port multiplexing circuit and a dead time control trimming circuit and then respectively connecting the temperature sensing circuit with a pulse generating circuit and a low-voltage locking and delay circuit; the port multiplexing circuit comprises a dead time control circuit, a latch module, a trimming array module, a trimming addressing module, a burnout control module and a multiplexing port protection circuit. Under the condition that chip ports are not increased, the output end is multiplexed as the programmable trimming port, the packaging cost is saved, and the precision of performance parameters and the product yield of the gate drive chip are improved.

Description

Technical Field

[0001] The invention relates to the field of integrated circuits, and in particular provides a gate driver chip with a multiplexed programmable trimming port. Background Art

[0002] In the field of integrated circuit product manufacturing, due to process deviations, there are often deviations between the design values ​​of chip parameters and the test values ​​of actual finished products, especially for some key parameters with high precision requirements. Therefore, it is necessary to adjust them according to the test values ​​of the chip so that the key parameters can meet the expected design requirements and improve the yield of the product. The more commonly used adjustment method is the wafer mid-test stage in the chip production process. According to the test results of this stage, the parameters that do not meet the requirements are adjusted to the required values ​​by laser burning or voltage fusing before entering the chip packaging stage. This method slows down the delivery of products. In addition, for terminal applications that require flexible configuration of chip parameters, this method obviously cannot meet customer needs in a timely manner. Summary of the invention

[0003] In order to solve the above problems, an object of the present invention is to provide a gate driver chip with a multiplexed programmable trimming port to improve the parameter accuracy and product yield of the gate driver chip.

[0004] To achieve the above-mentioned purpose, the technical scheme of the present invention is as follows: a gate driver chip with a multiplexed programmable trim port, comprising a low-side circuit and a high-side circuit; the high-side circuit shown comprises a bootstrap diode, a high-side circuit monitoring and protection part and an output interface part I; the bootstrap diode is connected to the voltage VB; the high-side circuit monitoring and protection part comprises a level shift circuit and a low-voltage lock; the output interface part I consists of an output logic, a PMOS driver tube P1, an NMOS driver tube N1, an output resistor XR1, an output resistor XR2 and an output port HO; one end of the low-voltage lock is connected to the voltage VB, and the other end is connected to the output logic; the level shift circuit is connected to the output logic; the output logic is connected to the gate of the PMOS driver tube P1 and the gate of the NMOS driver tube N1; the drain of the PMOS driver tube P1 is connected to the output resistor XR1 and then to the output port HO, and the source is connected to the voltage VB; the drain of the NMOS driver tube N1 is connected to the output resistor XR2 and then to the output port HO, and the source is connected to the voltage VS; the low-side circuit comprises an input interface part, a low-side circuit monitoring and protection part and an output Interface part II; the input interface part is composed of a high-side signal input port HIN and a low-side signal input port LIN connected to the corresponding filter circuit; the low-side circuit monitoring and protection part is composed of a temperature sensing circuit connected in sequence to a port multiplexing circuit and a dead time control adjustment circuit, and then connected to a pulse generating circuit, a low voltage lockout and a delay circuit respectively; the filter is connected to the dead time control adjustment circuit, and the low voltage lockout is connected to the voltage VCC; the pulse generating circuit is connected to the level shift circuit, and the bootstrap diode is connected to the voltage VCC; the output interface part II is composed of an output logic, a PMOS driver tube P2, an NMOS driver tube N2, an output resistor XR3, an output resistor XR4 and an output port LO; one end of the output logic is connected to the delay circuit, and the other end is connected to the gate of the PMOS driver tube P2 and the gate of the NMOS driver tube N2, the drain of the PMOS driver tube P2 is connected to the output resistor XR3 and then to the output port LO, and the source is connected to the voltage VCC; the drain of the NMOS driver tube N2 is connected to the output resistor XR4 and then to the output port LO, and the source is connected to the voltage VSS.

[0005] Furthermore, the port multiplexing circuit includes a dead time control circuit, a latch module, a trimming array module, a trimming addressing module, a burnout control module and a multiplexed port protection circuit; the dead time control circuit is used as a target circuit for programmable trimming; the trimming array module is connected to the dead time control circuit and is a burnout resistor array designed for the parameters that need to be trimmed in the dead time control circuit; one end of the latch module is connected to the temperature sensor output port VTS and the other end is connected to the temperature sensor, and a specific trimming signal is given according to the temperature sensor output port VTS, and the output of the temperature sensor is latched as a low level; the multiplexed port protection circuit connects the temperature sensor and the temperature sensor. The temperature sensing output port VTS is multiplexed as a programmable trimming port; one end of the trimming addressing module is connected to the temperature sensing output port VTS, and the other end is connected to the trimming array module, and the resistor that needs to be burned in the trimming array module is located according to the addressing signal input by the temperature sensing output port VTS; the burnout control module is respectively connected to the temperature sensing output port VTS, the trimming addressing module and the trimming array module, and the burnout resistor in the trimming array module is burned according to the resistor that needs to be burned determined by the trimming addressing module and the burnout signal input by the temperature sensing output port VTS.

[0006] Further, the multiplexed port protection circuit is composed of a voltage VCC, a diode D0, a resistor R0, a P-type field effect transistor MP0, MP1, MP2, MP3, MP4, MP5, MP6 and an N-type field effect transistor MN0, MN1, MN2, MN3; the P-type field effect transistor MP0 and the N-type field effect transistor MN0 are connected to form an inverter structure, the source of the P-type field effect transistor MP0 is connected to the voltage VCC, the gate and the gate of the N-type field effect transistor MN0 are connected to the output end of the temperature sensor circuit, the drain is connected to the drain of the N-type field effect transistor MN0, and the source of the N-type field effect transistor MN0 is connected to the ground signal The gate of the P-type field effect transistor MP1 is connected to the voltage VCC, the source is connected to the gate of the P-type field effect transistor MP5, the drain of the P-type field effect transistor MP4, and the drain of the N-type field effect transistor MN2, the substrate is connected to the cathode of the diode D0, and the drain is connected to the drain of the P-type field effect transistor MP6; the gate of the P-type field effect transistor MP2 is connected to the voltage VCC, the source is connected to the drain of the P-type field effect transistor MP6, the substrate is connected to the cathode of the diode D0, and the drain is connected to the drain of the N-type field effect transistor MN1; the gate of the N-type field effect transistor MN1 is connected to the voltage VCC, the source is connected to the ground signal The gate of the P-type field effect transistor MP3 is connected to the drain of the P-type field effect transistor MP2, the source is connected to the voltage VCC, the substrate is connected to the cathode of the diode D0, and the drain is connected to the source of the P-type field effect transistor MP4; the gate of the P-type field effect transistor MP4 is connected to the gate of the N-type field effect transistor MN0, the substrate is connected to the cathode of the diode D0, and the drain is connected to the drain of the N-type field effect transistor MN2; the gate of the N-type field effect transistor MN2 is connected to the gate of the P-type field effect transistor MP4, and the source is connected to the ground signal; the gate of the P-type field effect transistor MP5 is connected to the drain of the P-type field effect transistor MP4, and the source is connected to the ground signal. The gate of the P-type field effect transistor MP6 is connected to the power supply level VCC, the source and the substrate are connected to the cathode of the diode D0, and the drain is connected to the drain of the P-type field effect transistor MP6; the gate of the P-type field effect transistor MP6 is connected to the power supply level VCC, the source and the substrate are connected to the cathode of the diode D0; the anode of the diode D0 is connected to the power supply level VCC; the gate of the N-type field effect transistor MN3 is connected to the drain of the N-type field effect transistor MN0, and the source is connected to the ground signal; the first end of the resistor R0 is used as a temperature sensing output port VTS, connected to the drain of the P-type field effect transistor MP6, and the second end is connected to the drain of the N-type field effect transistor MN3.

[0007] The present invention aims at the limitations of the adjustment method of the gate driver chip wafer test link and provides a gate driver chip that can be adjusted in the chip finished product test link. The chip multiplexes the output end as a programmable adjustment port without increasing the chip port, which can save packaging costs and also improve the accuracy of the gate driver chip performance parameters and product yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 This is an internal block diagram of the gate drive chip of the present invention; Figure 2 It is a schematic block diagram of the port multiplexing circuit of the present invention. Implementation

[0009] The specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0010] like Figure 1 As shown: a gate driver chip with a multiplexed programmable trim port, including a low-side circuit and a high-side circuit; the high-side circuit shown includes a bootstrap diode, a high-side circuit monitoring and protection part and an output interface part I; the bootstrap diode is connected to the voltage VB; the high-side circuit monitoring and protection part includes a level shift circuit and a low-voltage lock; the output interface part I is composed of an output logic, a PMOS driver tube P1, an NMOS driver tube N1, an output resistor XR1, an output resistor XR2 and an output port HO; one end of the low-voltage lock is connected to the voltage VB, and the other end is connected to the output logic; the level shift circuit is connected to the output logic; the output logic is connected to the gate of the PMOS driver tube P1 and the gate of the NMOS driver tube N1; the drain of the PMOS driver tube P1 is connected to the output resistor XR1 and then to the output port HO, and the source is connected to the voltage VB; the drain of the NMOS driver tube N1 is connected to the output resistor XR2 and then to the output port HO, and the source is connected to the voltage VS; the low-side circuit includes an input interface part, a low-side circuit monitoring and protection part and an output interface part II; the The input interface part is composed of a high-side signal input port HIN and a low-side signal input port LIN connected to corresponding filter circuits; the low-side circuit monitoring and protection part is composed of a temperature sensor circuit connected in sequence to a port multiplexing circuit and a dead time control adjustment circuit, and then connected to a pulse generating circuit, a low voltage lockout and a delay circuit respectively; the filter is connected to the dead time control adjustment circuit, and the low voltage lockout is connected to the voltage VCC; the pulse generating circuit is connected to the level shift circuit, and the bootstrap diode is connected to the voltage VCC; the output interface part II is composed of an output logic, a PMOS driver tube P2, an NMOS driver tube N2, an output resistor XR3, an output resistor XR4 and an output port LO; one end of the output logic is connected to the delay circuit, and the other end is connected to the gate of the PMOS driver tube P2 and the gate of the NMOS driver tube N2, the drain of the PMOS driver tube P2 is connected to the output resistor XR3 and then to the output port LO, and the source is connected to the voltage VCC; the drain of the NMOS driver tube N2 is connected to the output resistor XR4 and then to the output port LO, and the source is connected to the voltage VSS.

[0011] like Figure 2As shown, the port multiplexing circuit includes a dead time control circuit, a latch module, a trimming array module, a trimming addressing module, a burnout control module and a multiplexed port protection circuit; the dead time control circuit is used as a target circuit for programmable trimming; the trimming array module is connected to the dead time control circuit and is a burnout resistor array designed for the parameters that need to be trimmed in the dead time control circuit; one end of the latch module is connected to the temperature sensor output port VTS and the other end is connected to the temperature sensor, and a specific trimming signal is given according to the temperature sensor output port VTS, and the output of the temperature sensor is latched as a low level; the multiplexed port protection circuit connects the temperature sensor and the temperature sensor. The temperature sensing output port VTS is multiplexed as a programmable trimming port; one end of the trimming addressing module is connected to the temperature sensing output port VTS, and the other end is connected to the trimming array module, and the resistor that needs to be burned in the trimming array module is located according to the addressing signal input from the temperature sensing output port VTS; the burnout control module is respectively connected to the temperature sensing output port VTS, the trimming addressing module and the trimming array module, and the burnout resistor in the trimming array module is burned according to the resistor that needs to be burned determined by the trimming addressing module and the burnout signal input from the temperature sensing output port VTS.

[0012] The multiplexed port protection circuit is composed of a voltage VCC, a diode D0, a resistor R0, a P-type field effect transistor MP0, MP1, MP2, MP3, MP4, MP5, MP6 and an N-type field effect transistor MN0, MN1, MN2, MN3; the P-type field effect transistor MP0 and the N-type field effect transistor MN0 are connected to form an inverter structure, the source of the P-type field effect transistor MP0 is connected to the voltage VCC, the gate and the gate of the N-type field effect transistor MN0 are connected to the output end of the temperature sensor circuit, the drain is connected to the drain of the N-type field effect transistor MN0, and the source of the N-type field effect transistor MN0 is connected to the ground signal The gate of the P-type field effect transistor MP1 is connected to the voltage VCC, the source is connected to the gate of the P-type field effect transistor MP5, the drain of the P-type field effect transistor MP4, and the drain of the N-type field effect transistor MN2, the substrate is connected to the cathode of the diode D0, and the drain is connected to the drain of the P-type field effect transistor MP6; the gate of the P-type field effect transistor MP2 is connected to the voltage VCC, the source is connected to the drain of the P-type field effect transistor MP6, the substrate is connected to the cathode of the diode D0, and the drain is connected to the drain of the N-type field effect transistor MN1; the gate of the N-type field effect transistor MN1 is connected to the voltage VCC, and the source is connected to the ground signal The gate of the P-type field effect transistor MP3 is connected to the drain of the P-type field effect transistor MP2, the source is connected to the voltage VCC, the substrate is connected to the cathode of the diode D0, and the drain is connected to the source of the P-type field effect transistor MP4; the gate of the P-type field effect transistor MP4 is connected to the gate of the N-type field effect transistor MN0, the substrate is connected to the cathode of the diode D0, and the drain is connected to the drain of the N-type field effect transistor MN2; the gate of the N-type field effect transistor MN2 is connected to the gate of the P-type field effect transistor MP4, and the source is connected to the ground signal; the gate of the P-type field effect transistor MP5 is connected to the drain of the P-type field effect transistor MP4, and the source is connected to the ground signal. The power supply level VCC is connected, the substrate is connected to the cathode of the diode D0, and the drain is connected to the drain of the P-type field effect transistor MP6; the gate of the P-type field effect transistor MP6 is connected to the power supply level VCC, and the source and substrate are connected to the cathode of the diode D0; the anode of the diode D0 is connected to the power supply level VCC; the gate of the N-type field effect transistor MN3 is connected to the drain of the N-type field effect transistor MN0, and the source is connected to the ground signal; the first end of the resistor R0 is used as a temperature sensing output port VTS, connected to the drain of the P-type field effect transistor MP6, and the second end is connected to the drain of the N-type field effect transistor MN3.

[0013] According to the parameter test results of the finished chip, the parameters that need to be adjusted are determined, and a programming addressing pulse higher than the voltage VCC is input to the temperature sensor output port VTS to address the parameter adjustment position, and determine the position and resistance combination of the resistor that needs to be burned out; then a high-voltage burnout signal that lasts for a period of time is input through the temperature sensor output port VTS to burn out the adjustment resistor determined by the addressing; the changes in the chip parameters that need to be adjusted are monitored in real time, and the adjustment is completed when it reaches the expected range.

[0014] Because the addressing signal and burnout signal input to the temperature sensor output port VTS are higher than the voltage VCC inside the chip, there is a potential risk to the chip, so the voltage VCC needs to be protected. The principle of the multiplexed port protection circuit is described in detail below: the P-type field effect transistor MP0 and the N-type field effect transistor MN0 are connected to form an inverter structure, whose input is the output of the temperature sensor, and its output is connected to the gate of the N-type field effect transistor MN3 to control its opening and closing; the output of the P-type field effect transistors MP1 and MP2 and the N-type field effect transistor MN1 branch controls the gate of the P-type field effect transistor MP5 and the gate of the P-type field effect transistor MP3. When the chip is in normal working condition, the gate level of the field effect transistor in this branch is VCC, so the P-type field effect transistors MP1 and MP2 are turned off, and the N-type field effect transistor MN1 is turned on, then the gate of the P-type field effect transistor MP5 is not affected by this branch. Control, the gate of P-type field effect transistor MP3 is low level, and P-type field effect transistor MP3 is turned on; under the high level condition of the trimming mode, the gate level of P-type field effect transistors MP5 and MP3 is VTS signal level, so P-type field effect transistors MP5 and MP3 are turned off; P-type field effect transistors MP3, MP4, and N-type field effect transistor MN2 branches control the opening and closing of output tube P-type field effect transistor MP5 under normal working state of the chip; under the high level condition of the trimming mode, the gate signal of P-type field effect transistor MP3 is high level, and P-type field effect transistor MP3 is turned off, the gates of P-type field effect transistor MP4 and N-type field effect transistor MN2 are low level, P-type field effect transistor MP4 is turned on, and N-type field effect transistor MN2 is turned off, so the gate level of P-type field effect transistor MP5 is VTS signal level, and P-type field effect transistor MP5 is turned off.

[0015] In summary, when the chip is in normal working state, the P-type field effect transistor MP6 is turned off, and the drain and substrate of the P-type field effect transistor MP5 are disconnected; the diode D0 is turned on, and the source and substrate of the P-type field effect transistor MP5 are connected together; the P-type field effect transistor MP1 is turned off, the P-type field effect transistor MP2 is turned off, and the N-type field effect transistor MN1 is turned on, and the gate of the P-type field effect transistor MP3 is pulled down, then the P-type field effect transistor MP4 and the N-type field effect transistor MN2 non-gate branch work normally, so the gate of the P-type field effect transistor MP5 is only controlled by the previous stage circuit.

[0016] When the chip is in the trimming mode and the temperature sensor output port VTS has a high level of the trimming pulse, the P-type field effect transistor MP6 is turned on to connect the drain and substrate of the P-type field effect transistor MP5 together; the diode D0 is turned off to separate the source and substrate of the P-type field effect transistor MP5; the P-type field effect transistor MP1 is turned on to pull the gate of the P-type field effect transistor MP5 to a high level; the P-type field effect transistor MP2 is turned on to pull the gate of the P-type field effect transistor MP3 high, so that the P-type field effect transistor MP3 is turned off, so that the P-type field effect transistor MP5 realizes the isolation of VCC and VTS, thereby realizing the multiplexing port protection.

[0017] The above is a specific description of the preferred implementation of the present invention, but the invention is not limited to the embodiments. Those skilled in the art may make various equivalent modifications or substitutions without violating the spirit of the present invention. These equivalent modifications or substitutions are all included in the scope defined by the claims of this application.

Claims

1. A gate driver chip with a multiplexed programmable trim port, characterized in that: It includes a low-side circuit and a high-side circuit; the high-side circuit shown includes a bootstrap diode, a high-side circuit monitoring and protection part and an output interface part I; The bootstrap diode is connected to a voltage VB; The high-side circuit monitoring and protection part includes a level shift circuit and a low-voltage lock; the output interface part I is composed of an output logic, a PMOS drive tube P1, an NMOS drive tube N1, an output resistor XR1, an output resistor XR2 and an output port HO; one end of the low-voltage lock is connected to the voltage VB, and the other end is connected to the output logic; the level shift circuit is connected to the output logic; the output logic is connected to the gate of the PMOS drive tube P1 and the gate of the NMOS drive tube N1; the drain of the PMOS drive tube P1 is connected to the output resistor XR1 and then connected to the output port HO, and the source is connected to the voltage VB; the drain of the NMOS drive tube N1 is connected to the output resistor XR2 and then connected to the output port HO, and the source is connected to the voltage VS; The low-side circuit includes an input interface part, a low-side circuit monitoring and protection part and an output interface part II; the input interface part is composed of a high-side signal input port HIN and a low-side signal input port LIN connected to corresponding filter circuits; the low-side circuit monitoring and protection part is composed of a temperature sensing circuit connected in sequence to a port multiplexing circuit and a dead time control adjustment circuit, and then connected to a pulse generating circuit, a low voltage lockout and a delay circuit respectively; the filter is connected to the dead time control adjustment circuit, and the low voltage lockout is connected to the voltage VCC; the pulse generating circuit is connected to the level shifting circuit, and the bootstrap circuit The gate of the PMOS driving tube P2 is connected to the voltage VCC; the output interface part II is composed of an output logic, a PMOS driving tube P2, an NMOS driving tube N2, an output resistor XR3, an output resistor XR4 and an output port LO; one end of the output logic is connected to the delay circuit, and the other end is connected to the gate of the PMOS driving tube P2 and the gate of the NMOS driving tube N2, the drain of the PMOS driving tube P2 is connected to the output resistor XR3 and then connected to the output port LO, and the source is connected to the voltage VCC; the drain of the NMOS driving tube N2 is connected to the output resistor XR4 and then connected to the output port LO, and the source is connected to the voltage VSS.

2. A gate driver chip with a multiplexed programmable trim port according to claim 1, characterized in that: The port multiplexing circuit includes a dead time control circuit, a latch module, a trimming array module, a trimming addressing module, a burnout control module and a multiplexed port protection circuit; the dead time control circuit is used as a target circuit for programmable trimming; the trimming array module is connected to the dead time control circuit and is a burnout resistor array designed for the parameters that need to be trimmed in the dead time control circuit; one end of the latch module is connected to the temperature sensor output port VTS and the other end is connected to the temperature sensor, a specific trimming signal is given according to the temperature sensor output port VTS, and the output of the temperature sensor is latched as a low level; the multiplexed port protection circuit connects the temperature sensor and the temperature sensor The temperature sensing output port VTS is multiplexed as a programmable trimming port; one end of the trimming addressing module is connected to the temperature sensing output port VTS, and the other end is connected to the trimming array module, and the resistor that needs to be burned in the trimming array module is located according to the addressing signal input from the temperature sensing output port VTS; the burnout control module is respectively connected to the temperature sensing output port VTS, the trimming addressing module and the trimming array module, and according to the resistor that needs to be burned determined by the trimming addressing module and the burnout signal input from the temperature sensing output port VTS, the burnout resistor in the trimming array module is burned.

3. The gate driver chip with multiplexed programmable trim ports according to claim 2, characterized in that: The multiplexed port protection circuit is composed of a voltage VCC, a diode D0, a resistor R0, a P-type field effect transistor MP0, MP1, MP2, MP3, MP4, MP5, MP6 and an N-type field effect transistor MN0, MN1, MN2, MN3; the P-type field effect transistor MP0 and the N-type field effect transistor MN0 are connected to form an inverter structure, the source of the P-type field effect transistor MP0 is connected to the voltage VCC, the gate and the gate of the N-type field effect transistor MN0 are connected to the output end of the temperature sensor circuit, the drain is connected to the drain of the N-type field effect transistor MN0, and the source of the N-type field effect transistor MN0 is connected to the ground signal The gate of the P-type field effect transistor MP1 is connected to the voltage VCC, the source is connected to the gate of the P-type field effect transistor MP5, the drain of the P-type field effect transistor MP4, and the drain of the N-type field effect transistor MN2, the substrate is connected to the cathode of the diode D0, and the drain is connected to the drain of the P-type field effect transistor MP6; the gate of the P-type field effect transistor MP2 is connected to the voltage VCC, the source is connected to the drain of the P-type field effect transistor MP6, the substrate is connected to the cathode of the diode D0, and the drain is connected to the drain of the N-type field effect transistor MN1; the gate of the N-type field effect transistor MN1 is connected to the voltage VCC, and the source is connected to the ground signal The gate of the P-type field effect transistor MP3 is connected to the drain of the P-type field effect transistor MP2, the source is connected to the voltage VCC, the substrate is connected to the cathode of the diode D0, and the drain is connected to the source of the P-type field effect transistor MP4; the gate of the P-type field effect transistor MP4 is connected to the gate of the N-type field effect transistor MN0, the substrate is connected to the cathode of the diode D0, and the drain is connected to the drain of the N-type field effect transistor MN2; the gate of the N-type field effect transistor MN2 is connected to the gate of the P-type field effect transistor MP4, and the source is connected to the ground signal; the gate of the P-type field effect transistor MP5 is connected to the drain of the P-type field effect transistor MP4, and the source is connected to the ground signal. The power supply level VCC is connected, the substrate is connected to the cathode of the diode D0, and the drain is connected to the drain of the P-type field effect transistor MP6; the gate of the P-type field effect transistor MP6 is connected to the power supply level VCC, and the source and substrate are connected to the cathode of the diode D0; the anode of the diode D0 is connected to the power supply level VCC; the gate of the N-type field effect transistor MN3 is connected to the drain of the N-type field effect transistor MN0, and the source is connected to the ground signal; the first end of the resistor R0 is used as a temperature sensing output port VTS, connected to the drain of the P-type field effect transistor MP6, and the second end is connected to the drain of the N-type field effect transistor MN3.

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