Gate driving circuit and method

Abstract

The invention provides a gate drive circuit and method, the gate drive circuit comprises a primary processing module and a secondary processing module, the secondary processing module detects the state of a power device and obtains at least two protection signals, the at least two protection signals are coded and then combined into a coded signal, and the coded signal is transmitted back to the primary processing module through a protection signal transmission channel. According to the gate drive circuit, multiple protection signals can be transmitted back to the primary processing module at the same time only through one protection signal transmission channel, the circuit is easy to implement, the area and cost of the gate drive circuit and the complexity of packaging and routing are reduced, signal back transmission is stable and reliable, and the technological process has universality.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and in particular to a gate driving circuit and method. Background Art

[0002] Gate drive circuits are commonly used in electronic products such as home appliances, industrial machines, and automotive products to drive power devices such as insulated-gate bipolar transistors (IGBTs).

[0003] The gate drive circuit includes a primary processing module and a secondary processing module. The primary processing module is connected to the low-voltage control unit, and the secondary processing module is connected to the power device. Usually, the secondary processing module detects the status of the power device in real time and obtains a series of protection signals. These protection signals need to be transmitted back to the primary processing module for processing, and then adjust the control signal output to the power device.

[0004] At present, each protection signal detected by the secondary processing module is transmitted back to the primary processing module through a separate protection signal transmission channel. Each protection signal transmission channel includes a transmitter, a receiver and a signal recognition unit. Multiple protection signals require multiple sets of transmitters, receivers and signal recognition units, which leads to a complex gate drive circuit structure, a large area, a high cost, and a high complexity of packaging and wiring. Summary of the invention

[0005] The object of the present invention is to provide a gate driving circuit and method to solve the problems of the existing gate driving circuit having a complex structure, a large area, a high cost, and a high complexity of packaging and wiring.

[0006] In order to achieve the above object, the present invention provides a gate drive circuit for driving a power device, comprising a primary processing module and a secondary processing module.

[0007] The secondary processing module detects the state of the power device and obtains at least two protection signals. The at least two protection signals are encoded and combined into one encoded signal and transmitted back to the primary processing module through a protection signal transmission channel.

[0008] Optionally, after receiving the coded signal, the primary processing module decodes the coded signal to obtain at least two decoded signals, which are used to characterize the corresponding protection signals, and identifies and processes the decoded signals to obtain at least two indication signals indicating the corresponding states of the power device.

[0009] Optionally, the protection signal includes a first protection signal and a second protection signal, and a priority of the first protection signal is higher than a priority of the second protection signal; and,

[0010] When the coded signal has a pulse width segment of the first pulse width, it indicates that the first protection signal is valid; when the coded signal has a pulse width segment of the second pulse width, it indicates that both the first protection signal and the second protection signal are invalid, and the power device works normally.

[0011] Optionally, the first pulse width is greater than the second pulse width.

[0012] Optionally, the protection signal further includes a plurality of third protection signals, the priority of the third protection signals is between the first protection signal and the second protection signal, and each of the third protection signals has a different priority; and,

[0013] When the coded signal has a pulse width segment of a corresponding third pulse width, it indicates that the first protection signal is invalid and the corresponding third protection signal is valid, and each of the third pulse widths has a different size.

[0014] Optionally, the first pulse width is greater than each of the third pulse widths, each of the third pulse widths is greater than the second pulse width, and the size of each of the third pulse widths is positively correlated with the priority of the corresponding third protection signal.

[0015] Optionally, the decoding signal includes a first decoding signal and a second decoding signal, the first decoding signal having a pulse width segment of the first pulse width when the first protection signal is valid, and the second decoding signal having a pulse width segment of the second pulse width when both the first protection signal and the second protection signal are invalid.

[0016] Optionally, the decoding signal includes a first decoding signal, a second decoding signal and several third decoding signals, the first decoding signal having a pulse width segment of the first pulse width when the first protection signal is valid, the third decoding signal having a pulse width segment of the corresponding third pulse width when the corresponding third protection signal is valid, and the second decoding signal having a pulse width segment of the second pulse width when the first protection signal, the second protection signal and the third protection signal are all invalid.

[0017] Optionally, the indication signal includes a first indication signal and a second indication signal;

[0018] The first indication signal is used to indicate that the corresponding state of the power device is abnormal when the first decoded signal has a pulse width segment of the first pulse width, until a reset signal is valid, indicating that the corresponding state of the power device returns to normal; and

[0019] The second indication signal is used to indicate that the power device is operating normally when the second decoded signal has a pulse width segment of the second pulse width, and to indicate that a corresponding state of the power device is abnormal at other times.

[0020] Optionally, the indication signal includes a first indication signal, a second indication signal and a plurality of third indication signals;

[0021] The first indication signal is used to indicate that the corresponding state of the power device is abnormal when the first decoded signal has a pulse width segment of the first pulse width, until a reset signal is valid, indicating that the corresponding state of the power device returns to normal;

[0022] The third indication signal is used to indicate that the corresponding state of the power device is abnormal within a predetermined time when the third pulse width segment of the third pulse width appears in the third decoded signal, and to indicate that the corresponding state of the power device returns to normal after the predetermined time; and

[0023] The second indication signal is used to indicate that the power device is operating normally when the second decoded signal has a pulse width segment of the second pulse width, and to indicate that a corresponding state of the power device is abnormal at other times.

[0024] Optionally, the indication signal includes a first indication signal and a fourth indication signal;

[0025] The first indication signal is used to indicate that the corresponding state of the power device is abnormal when the first decoded signal has a pulse width segment of the first pulse width, until a reset signal is valid, indicating that the corresponding state of the power device returns to normal; and

[0026] The fourth indication signal is used to indicate that the power device is working normally when the second decoding signal has a pulse width segment of the second pulse width, and to indicate that the corresponding state of the power device is abnormal at other times, and to indicate that the corresponding state of the power device is abnormal within a predetermined time when the third decoding signal has a pulse width segment of the third pulse width, and to indicate that the corresponding state of the power device returns to normal after the predetermined time until the second decoding signal has a pulse width segment of the second pulse width.

[0027] Optionally, when the reset signal flips from a first level value to a second level value, and a duration of the second level value is greater than a first predetermined value, the reset signal is determined to be valid.

[0028] Optionally, the protection signal includes an overcurrent / desaturation signal, an overvoltage signal, an overtemperature signal or an undervoltage signal.

[0029] Optionally, a high level is a valid state of the first protection signal, and a low level is an invalid state of the first protection signal; a low level is a valid state of the second protection signal, and a high level is an invalid state of the second protection signal.

[0030] Optionally, a high level is a valid state of the third protection signal, and a low level is an invalid state of the third protection signal.

[0031] Optionally, the secondary processing module includes a first signal processing unit, and the first signal processing unit includes:

[0032] a first pulse width locking circuit, receiving the first protection signal, and locking the pulse width of the first protection signal to the first pulse width, so as to output a first pulse width locking signal;

[0033] an encoding circuit, receiving the second protection signal, and outputting a second pulse width locking signal of the second pulse width when the second protection signal is invalid; and

[0034] A multiplexer group receives the first pulse width locking signal and the second pulse width locking signal, and outputs the first pulse width locking signal when the first pulse width locking signal is valid, and outputs the second pulse width locking signal when the first pulse width locking signal is invalid and the second pulse width locking signal is valid, and the multiplexer group outputs the encoded signal.

[0035] Optionally, the primary processing module includes a decoding unit, and the decoding unit includes:

[0036] a first pulse width selector, receiving the coded signal, and separating a portion of the coded signal having a pulse width greater than a second predetermined value, to output a first pulse width selection signal;

[0037] a second pulse width selector, receiving the coded signal, and separating a portion of the coded signal whose pulse width is greater than a third predetermined value, to output a second pulse width selection signal; and

[0038] a logic operation circuit, receiving the first pulse width selection signal and the second pulse width selection signal, and performing logic operation on the first pulse width selection signal and the second pulse width selection signal to obtain the first decoding signal and the second decoding signal;

[0039] The first pulse width is greater than the second predetermined value, and the second pulse width is greater than the third predetermined value and less than the second predetermined value.

[0040] Optionally, the first decoding signal is the same signal as the first pulse width selection signal, and the second decoding signal is a superimposed signal of the first pulse width selection signal and the second pulse width selection signal.

[0041] Optionally, the decoding unit further includes:

[0042] The first signal shaping circuit is used for shaping the coded signal and inputting it into the first pulse width selector and the second pulse width selector.

[0043] Optionally, the primary processing module further includes a second signal processing unit, and the second signal processing unit includes:

[0044] a second latch, wherein a reset terminal of the second latch receives the reset signal, a set terminal of the second latch receives the first decoding signal, and an output terminal of the second latch outputs the first indication signal; and

[0045] The timing circuit receives the second decoding signal and outputs the second indication signal.

[0046] Optionally, the second signal processing unit further includes:

[0047] a second buffer connected to the output end of the second latch and used for buffering and outputting the first indication signal;

[0048] a third buffer, connected to the output end of the timing circuit, and used for buffering and outputting the second indication signal;

[0049] a second signal shaping circuit, receiving the first decoding signal, and configured to shape the first decoding signal and input the signal into the second latch;

[0050] a third signal shaping circuit, receiving the reset signal, and configured to shape the reset signal and input it into the second latch; and

[0051] A fourth signal shaping circuit receives the second decoded signal and is used for shaping the second decoded signal and inputting the signal into the timing circuit.

[0052] Optionally, the secondary processing module includes a first signal processing unit, and the first signal processing unit includes:

[0053] a first pulse width locking circuit, receiving the first protection signal, and locking the pulse width of the first protection signal to the first pulse width, so as to output a first pulse width locking signal;

[0054] an encoding circuit, receiving the second protection signal, and outputting a second pulse width locking signal of the second pulse width when the second protection signal is invalid;

[0055] a plurality of second pulse width locking circuits, receiving the corresponding third protection signal, and locking the pulse width of the third protection signal to the corresponding third pulse width, so as to output a corresponding third pulse width locking signal; and,

[0056] a multiplexer group, receiving the first pulse width locking signal, the second pulse width locking signal and the third pulse width locking signal, and outputting the first pulse width locking signal when the first pulse width locking signal is valid,

[0057] When the first pulse width locking signal is invalid and the corresponding third pulse width locking signal is valid, the corresponding third pulse width locking signal is outputted,

[0058] When the first pulse width locking signal is invalid and at least two of the third pulse width locking signals are valid, the third pulse width locking signal corresponding to the third protection signal with the highest priority is output,

[0059] When the first pulse width locking signal and the third pulse width locking signal are invalid and the second pulse width locking signal is valid, the second pulse width locking signal is output, and the multiplexer group outputs the encoded signal.

[0060] Optionally, the primary processing module includes a decoding unit, and the decoding unit includes:

[0061] a first pulse width selector, receiving the coded signal, and separating a portion of the coded signal having a pulse width greater than a second predetermined value, to output a first pulse width selection signal;

[0062] a second pulse width selector, receiving the coded signal, and separating a portion of the coded signal having a pulse width greater than a third predetermined value, to output a second pulse width selection signal;

[0063] a plurality of third pulse width selectors, receiving the coded signal, and separating the portion of the coded signal whose pulse width is greater than the corresponding fourth predetermined value, so as to output corresponding third pulse width selection signals; and,

[0064] a logic operation circuit, receiving the first pulse width selection signal, the second pulse width selection signal and the third pulse width selection signal, and performing logic operation on the first pulse width selection signal, the second pulse width selection signal and the third pulse width selection signal to obtain the first decoding signal, the second decoding signal and the third decoding signal;

[0065] Among them, the first pulse width is greater than the second predetermined value, the second pulse width is greater than the fourth predetermined value and less than the third predetermined value, and the third pulse width is greater than the third predetermined value and less than the second predetermined value.

[0066] Optionally, the first decoding signal is the same signal as the first pulse width selection signal, the second decoding signal is the superposition signal of the first pulse width selection signal, the second pulse width selection signal and the third pulse width selection signal, and the third decoding signal is the signal obtained by inverting the first pulse width selection signal and multiplying it with the second pulse width selection signal and the third pulse width selection signal.

[0067] Optionally, the decoding unit further includes:

[0068] The first signal shaping circuit is used for shaping the coded signal and inputting it into the first pulse width selector, the second pulse width selector and each of the third pulse width selectors.

[0069] Optionally, the primary processing module further includes a second signal processing unit, and the second signal processing unit includes:

[0070] a second latch, wherein a reset terminal of the second latch receives the reset signal, a set terminal of the second latch receives the first decoding signal, and an output terminal of the second latch outputs the first indication signal;

[0071] A plurality of third pulse width locking circuits, respectively receiving the corresponding third decoding signals, locking the pulse width of the third decoding signals to the predetermined time, and outputting corresponding third indication signals;

[0072] a first AND gate, receiving the third indication signal and the second decoding signal, and outputting a combined signal; and

[0073] The timing circuit receives the combined signal and outputs the fourth indication signal.

[0074] Optionally, the second signal processing unit further includes:

[0075] a second buffer connected to the output end of the second latch and used for buffering and outputting the first indication signal;

[0076] a third buffer, connected to the output end of the timing circuit, and used for buffering and then outputting the fourth indication signal;

[0077] a second signal shaping circuit, receiving the first decoding signal, and configured to shape the first decoding signal and input the signal into the second latch;

[0078] a third signal shaping circuit, receiving the reset signal, and configured to shape the reset signal and input it into the second latch;

[0079] a fourth signal shaping circuit, receiving the second decoded signal, and configured to shape the second decoded signal and input the signal into the first AND gate; and

[0080] The fifth signal shaping circuit receives the third decoded signal and is used for shaping the third decoded signal and inputting the signal into the corresponding third pulse width locking circuit.

[0081] Optionally, the primary processing module further includes a second signal processing unit, and the second signal processing unit includes:

[0082] a second latch, wherein a reset terminal of the second latch receives the reset signal, a set terminal of the second latch receives the first decoding signal, and an output terminal of the second latch outputs the first indication signal;

[0083] a plurality of third pulse width locking circuits, which respectively receive the corresponding third decoded signals, lock the pulse width of the third decoded signals to the predetermined time, and output the third indication signal; and,

[0084] The timing circuit receives the second decoding signal and outputs the second indication signal.

[0085] Optionally, the second signal processing unit further includes:

[0086] a second buffer connected to the output end of the second latch and used for buffering and outputting the first indication signal;

[0087] a third buffer, connected to the output end of the timing circuit, and used for buffering and outputting the second indication signal;

[0088] a fourth buffer, connected to the output end of the third pulse width locking circuit, and used for buffering and then outputting the third indication signal;

[0089] a second signal shaping circuit, receiving the first decoding signal, and configured to shape the first decoding signal and input the signal into a second latch;

[0090] a third signal shaping circuit, receiving the reset signal, and configured to shape the reset signal and input it into the second latch;

[0091] a fourth signal shaping circuit, receiving the second decoded signal, and configured to shape the second decoded signal and input it into the timing circuit; and

[0092] The fifth signal shaping circuit receives the third decoded signal and is used for shaping the third decoded signal and inputting the signal into the corresponding third pulse width locking circuit.

[0093] Optionally, the first signal processing unit further includes:

[0094] At least one first buffer receives the encoded signal, and outputs the encoded signal after buffering it.

[0095] Optionally, the encoding circuit is an oscillator circuit.

[0096] Optionally, the primary processing module further includes at least two MOS tubes, the gate of the MOS tube receives the corresponding indication signal, the drain of the MOS tube outputs a corresponding transfer signal and transmits it back to the low-voltage control unit, and the source of the MOS tube is grounded.

[0097] Optionally, the primary processing module further includes a first logic circuit and a first transmitter connected in sequence, and the secondary processing module further includes a first receiver, a second logic circuit and a driving circuit connected in sequence;

[0098] The first logic circuit receives a PWM control signal, processes it, and then sends it to the first transmitter. The first transmitter sends the PWM control signal to the secondary processing module. The first receiver receives the PWM control signal sent by the first transmitter. The second logic circuit processes the PWM control signal and then inputs it into the drive circuit. The drive circuit outputs a drive signal to drive the power device.

[0099] Optionally, the primary processing module further includes:

[0100] An OR gate receives all the indication signals and outputs a first trigger signal, wherein the first trigger signal turns off the first logic circuit when any of the indication signals indicates that the state of the power device is abnormal.

[0101] Optionally, the coded signal also serves as a second trigger signal, and the second trigger signal turns off the second logic circuit when indicating that the state of the power device is abnormal.

[0102] Optionally, the primary processing module further includes a second receiver, and the secondary processing module further includes a second transmitter, the second receiver and the second transmitter constitute the protection signal transmission channel, and the coded signal is sent to the second receiver via the second transmitter.

[0103] Optionally, the primary processing module is a primary chip, the secondary processing module is a secondary chip, and the primary chip and the secondary chip are interconnected by wire bonding.

[0104] Optionally, the gate drive circuit is an isolated gate drive circuit.

[0105] Optionally, the isolated gate drive circuit includes a magnetic isolation gate drive circuit or a capacitive isolation gate drive circuit.

[0106] Optionally, the present invention also provides a gate driving method, which adopts the gate driving circuit.

[0107] The gate drive circuit and method provided by the present invention include a primary processing module and a secondary processing module. The secondary processing module detects the state of the power device and obtains at least two protection signals. The at least two protection signals are encoded and combined into one coded signal and transmitted back to the primary processing module through a protection signal transmission channel. The present invention only needs one protection signal transmission channel to simultaneously transmit multiple protection signals back to the primary processing module. The circuit is simple to implement, reducing the area, cost and packaging wiring complexity of the gate drive circuit. The signal transmission is stable and reliable, and the process is universal. BRIEF DESCRIPTION OF THE DRAWINGS

[0108] Figure 1 A circuit diagram of a gate driving circuit provided in Embodiment 1 of the present invention;

[0109] Figure 2 A structural block diagram of a first signal processing unit provided in Embodiment 1 of the present invention;

[0110] Figure 3 A circuit diagram of a first pulse width locking circuit provided in Embodiment 1 of the present invention;

[0111] Figure 4 A timing diagram of each signal provided in Embodiment 1 of the present invention;

[0112] Figure 5 A structural block diagram of a decoding unit provided in Embodiment 1 of the present invention;

[0113] Figure 6 A structural block diagram of a second signal processing unit provided in Embodiment 1 of the present invention;

[0114] Figure 7 A schematic diagram of the working mode of the gate drive circuit provided in the first embodiment of the present invention;

[0115] Figure 8 A schematic diagram of the structure of a gate drive circuit provided in Embodiment 2 of the present invention;

[0116] Fig. 9 A structural block diagram of a first signal processing unit provided in Embodiment 2 of the present invention;

[0117] Fig.10 A timing diagram of each signal provided in Embodiment 2 of the present invention;

[0118] Fig.11 A structural block diagram of a decoding unit provided in Embodiment 2 of the present invention;

[0119] Fig.12 A structural block diagram of a second signal processing unit provided in Embodiment 2 of the present invention;

[0120] Fig.13 A schematic diagram of a gate drive circuit operating mode provided in Embodiment 2 of the present invention;

[0121] Fig.14 A schematic diagram of the structure of a gate driving circuit provided in Embodiment 3 of the present invention;

[0122] Fig.15 A structural block diagram of a second signal processing unit provided in Embodiment 3 of the present invention;

[0123] Wherein, the accompanying drawings are marked as follows:

[0124] 10-primary processing module; 11-decoding unit; 111-first pulse width selector; 112-second pulse width selector; 113-logic operation circuit; 114-first signal shaping circuit; 115-third pulse width selector; 12-second signal processing unit; 121-second signal shaping circuit; 122-third signal shaping circuit; 123-fourth signal shaping circuit; 124-second latch; 125-timing circuit; 126-second buffer; 127-third buffer; 128-fifth signal shaping circuit; 129-third pulse width locking circuit; 130-fourth buffer; 128-fifth signal shaping circuit; 13-second receiving machine; 14-first logic circuit; 15-first transmitter; 20-secondary processing module; 21-overcurrent / de-saturation detection unit; 22-undervoltage detection unit; 23-first signal processing unit; 231-first pulse width locking circuit; 2311-first latch; 232-encoding circuit; 2313-filtering unit; 2312-delay unit; 2331-first multiplexer; 2332-second multiplexer; 234, 235-first buffer; 236-second pulse width locking circuit; 24-second transmitter; 25-first receiver; 26-second logic circuit; 27-driving circuit; 28-overvoltage detection unit; 30-low voltage control unit;

[0125] MP-power device; VP-power supply voltage; R0-resistance; Pro1-first protection signal; Pro2-second protection signal; Pro3-third protection signal; t1-first pulse width; t2-second pulse width; t3-third pulse width; OUT_L2-encoding signal; NO1-first inverter; NO2-second inverter; NO3-third inverter; NO41, NO42-fourth inverter; Shut_p-first trigger signal; Shut_s-second trigger signal; OUT_A-first pulse width selection signal; OUT_B-second pulse width selection signal; OUT_C-third pulse width selection signal; RST-reset signal; Y OC- first decoded signal; Y UV - The second decoded signal; Y OV - third decoding signal; M1- first MOS tube; M2- second MOS tube; M3- third MOS tube; F_G- first indication signal; R_G- second indication signal; N_G- third indication signal; K_G- fourth indication signal; FLT- first transfer signal; RDY- second transfer signal; RDB- third transfer signal; AND1- first AND gate; OR- OR gate; DTov- scheduled time. DETAILED DESCRIPTION

[0126] The specific implementation of the present invention will be described in more detail below in conjunction with the schematic diagram. The advantages and features of the present invention will become clearer based on the following description. It should be noted that the drawings are all in a very simplified form and are not in exact proportions, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.

[0127] Embodiment 1

[0128] Figure 1 1 is a circuit diagram of a gate drive circuit provided in this embodiment. Figure 1 As shown, the gate drive circuit is used to drive a power device MP, which includes a primary processing module 10 and a secondary processing module 20. The primary processing module 10 is connected to the low voltage control unit 30, so as to exchange information with the low voltage control unit 30. The secondary processing module 20 is connected to the power device MP, so as to be responsible for efficiently driving the power device MP, and at the same time collecting and detecting the state of the power device MP, such as detecting the power supply state (normal, overvoltage, undervoltage) of the power device MP and the conduction state (overcurrent or desaturation) of the power device MP, and obtaining at least two protection signals. Wherein, the power device MP can be a MOS tube or an IGBT tube, the drain / collector of the power device MP receives the power supply voltage VP, the source / emitter is connected to the first end of the resistor R0, and the second end of the resistor R0 is grounded.

[0129] The gate drive circuit has a control signal transmission channel, which at least includes a first transmitter 15 and a first receiver 25. The first transmitter 15 is located in the primary processing module 10, and the first receiver 25 is located in the secondary processing module 20. The primary processing module 10 also includes a first logic circuit 14, and the secondary processing module 20 also includes a second logic circuit 26 and a drive circuit 27. The PWM control signal sent by the low-voltage control unit 30 is sent to the first transmitter 15 after being shaped, filtered, etc. by the first logic circuit 14, and the first transmitter 15 sends the PWM control signal to the secondary processing module 20. The first receiver 25 receives the PWM control signal sent by the first transmitter 15, and sends the PWM control signal to the second logic circuit 26. The second logic circuit 26 shapes, filters and performs timing processing on the PWM control signal and then sends it to the drive circuit 27. The drive circuit 27 outputs a drive signal to drive the power device MP to control the on and off of the power device MP. The drive signal has a drive capability and a power rail suitable for the switch control of the power device MP.

[0130] The gate drive circuit also has a protection signal transmission channel, and the secondary processing module 20 encodes at least two of the protection signals detected into a coded signal OUT_L2 and transmits it back to the primary processing module 10 through the protection signal transmission channel. In this way, only one protection signal transmission channel is needed to simultaneously transmit multiple protection signals back to the primary processing module 10, the circuit is simple to implement, the area, cost and packaging wiring complexity of the gate drive circuit are reduced, and the signal transmission is stable and reliable, and the process is universal.

[0131] Specifically, the protection signal transmission channel includes a second transmitter 24 and a second receiver 13, wherein the second transmitter 24 is located in the secondary processing module 20, and the second receiver 13 is located in the primary processing module 10. The secondary processing module 20 detects the corresponding state of the power device MP and obtains the corresponding protection signal. After the protection signal is effectively encoded, a coded signal OUT_L2 is formed and sent to the second transmitter 24. The second transmitter 24 sends the coded signal OUT_L2 to the second receiver 13, and the primary processing module 10 decodes the coded signal OUT_L2 to obtain at least two decoded signals, which can be used to indicate whether the corresponding protection signal is valid. The primary processing module 10 also identifies and processes the decoded signal to output at least two indication signals indicating the state of the power device MP, and processes the indication signal into a corresponding transmission signal. The transmission signal is then transmitted back to the low voltage control unit 30, and the low voltage control unit 30 triggers the corresponding protection according to the transmission signal and makes the next response action.

[0132] It is understandable that in certain specific fields (such as medical equipment, automotive regulations, etc.), the operating voltage of the power device MP can reach hundreds of thousands of volts, while the operating voltage of the low-voltage control unit 30 is only a few volts. The voltage difference between the low-voltage side and the high-voltage side is huge. In order to prevent the staff from getting an electric shock on the low-voltage side of the human-computer interaction or to avoid the high-voltage side from causing damage to the low-voltage side device, the gate drive circuit can be an isolated gate drive circuit, and the isolated gate drive circuit can be, for example, a magnetic isolation gate drive circuit or a capacitive isolation gate drive circuit. At this time, the first transmitter 15, the second transmitter 24, the first receiver 25 and the second receiver 13 all have high-voltage isolation elements (the high-voltage isolation elements can also be arranged outside the first transmitter 15, the second transmitter 24, the first receiver 25 and the second receiver 13), and the high-voltage isolation element can be, for example, a high-voltage flat capacitor or a micro transformer, so that there is an electrical isolation layer between the primary processing module 10 and the secondary processing module 20, effectively blocking the current path between the primary processing module 10 and the secondary processing module 20, and then achieving electrical isolation of signal safe transmission.

[0133] Please continue reading Figure 1The secondary processing module 20 includes a state detection unit. In this embodiment, the state detection unit includes an overcurrent / de-saturation detection unit 21 and an undervoltage detection unit 22. The overcurrent / de-saturation detection unit 21 can detect the overcurrent / de-saturation state of the power device MP, thereby obtaining an overcurrent / de-saturation signal, and the overcurrent / de-saturation signal can indicate whether the power device MP is overcurrent / de-saturated; the undervoltage detection unit 22 can detect the undervoltage state of the power device MP, thereby obtaining an undervoltage signal, and the undervoltage signal can indicate whether the source / emitter of the power device MP is undervoltage.

[0134] It is understandable that if Figure 1 As shown, the terminal voltage on the first end of the resistor R0 can be input into the overcurrent / de-saturation detection unit 21, and the overcurrent / de-saturation detection unit 21 can obtain an overcurrent signal according to the terminal voltage on the first end of the resistor R0. If the desaturation detection method is used, the voltage between the drain-source / collector-emitter of the power device MP can be input into the overcurrent / de-saturation detection unit 21 to obtain a desaturation signal. It should be noted that desaturation is the abbreviation of the abnormal working state of the power device exiting the saturation region. A normal power device is in the saturation region, and its conduction voltage drop is very low. If it exits the saturation region, the drain-source voltage drop becomes larger, and a very large current flows at the same time, which is a state with extremely high risk, and has the same meaning as overcurrent of the power device.

[0135] It should be understood that the state detection unit is not limited to only including the overcurrent / desaturation detection unit 21 and the undervoltage detection unit 22, but can also include an overtemperature detection unit and / or an overvoltage detection unit. At this time, the protection signal includes not only the overcurrent / desaturation signal and the undervoltage signal, but also includes protection signals such as the overvoltage signal and the overtemperature signal.

[0136] It should be noted that in actual applications, the degree of danger when the power device MP is abnormal is usually different. It is generally considered that the overcurrent of the power device MP is the most dangerous state, followed by overvoltage or overtemperature of the power device MP, and then undervoltage of the power device MP. Therefore, the protection signal can be configured with a priority according to the degree of danger. For example, if the protection signal detected by the state detection unit includes an overcurrent / desaturation signal and an undervoltage signal, the priority of the overcurrent / desaturation signal is higher than that of the undervoltage signal; if the protection signal detected by the state detection unit includes an overcurrent / desaturation signal, an overvoltage signal and an undervoltage signal, the priority of the overcurrent / desaturation signal is higher than that of the overvoltage signal, and the priority of the overvoltage signal is higher than that of the undervoltage signal; if the protection signal detected by the state detection unit includes an overcurrent / desaturation signal, an overvoltage signal, an overtemperature signal and an undervoltage signal, the priority of the overcurrent / desaturation signal is higher than that of the overvoltage signal and the overtemperature signal, and the priority of the overvoltage signal and the overtemperature signal is higher than that of the undervoltage signal, and there is also a priority between the overvoltage signal and the overtemperature signal, and the priority of the overvoltage signal and the overtemperature signal can be set according to the state that the user wants to prioritize protection.

[0137] For ease of description, in this embodiment, the protection signal is divided into a first protection signal Pro1 and a second protection signal Pro2. The priority of the first protection signal Pro1 is higher than the priority of the second protection signal Pro2. Therefore, in this embodiment, the first protection signal Pro1 is an overcurrent / desaturation signal, and the second protection signal Pro2 is an undervoltage signal. When the first protection signal Pro1 is valid, it indicates that the power device MP has an overcurrent / desaturation, and when the second protection signal Pro2 is valid, it indicates that the power device MP has an undervoltage.

[0138] The coding signal OUT_L2 uses different pulse widths to characterize whether the first protection signal Pro1 and the second protection signal Pro2 are valid. Specifically, when the coding signal OUT_L2 has a pulse width segment of the first pulse width t1, it indicates that the first protection signal Pro1 is valid, and when the coding signal OUT_L2 has a pulse width segment of the second pulse width t2, it indicates that both the first protection signal Pro1 and the second protection signal Pro2 are invalid, and the power device MP works normally. In addition, in order to facilitate subsequent decoding, the first pulse width t1 needs to be greater than the second pulse width t2.

[0139] like Figure 1As shown, in this embodiment, the secondary processing module 20 also includes a first signal processing unit 23, which is connected to each of the state detection units and the second transmitter 24. The first signal processing unit 23 receives the protection signal, encodes the protection signal, combines it into one coded signal OUT_L2, and transmits it to the second transmitter 24.

[0140] Specifically, Figure 2 FIG. 2 is a structural block diagram of the first signal processing unit 23 provided in this embodiment. Figure 2 As shown, in this embodiment, the first signal processing unit 23 includes a first pulse width locking circuit 231, an encoding circuit 232 and a multiplexer group. The first pulse width locking circuit 231 is connected to the overcurrent / de-saturation detection unit 21 to receive the first protection signal Pro1, and locks the pulse width of the first protection signal Pro1 to the first pulse width t1 to output a first pulse width locking signal. The encoding circuit 232 is connected to the undervoltage detection unit 22 to receive the second protection signal Pro2, and outputs a second pulse width locking signal when the second protection signal Pro2 is invalid, and the pulse width of the second pulse width locking signal is the second pulse width t2. The multiplexer group connects the first pulse width locking circuit 231 and the encoding circuit 232 to receive the first pulse width locking signal and the second pulse width locking signal, and outputs the first pulse width locking signal when the first pulse width locking signal is valid, and outputs the second pulse width locking signal when the first pulse width locking signal is invalid and the second pulse width locking signal is valid, and the multiplexer group finally outputs the encoding signal OUT_L2.

[0141] Figure 3 FIG. 2 is a circuit diagram of the first pulse width locking circuit 231 provided in this embodiment. Figure 3As shown, the first pulse width locking circuit 231 includes a first latch 2311 (RS latch in this embodiment), a first inverter NO1, a second inverter NO2, a third inverter NO3, a filtering unit 2313, a delay unit 2312 and a pair of fourth inverters, namely a fourth inverter NO41 and a fourth inverter NO42. Among them, the input end of the first inverter NO1 can receive the first protection signal Pro1, the output end of the first inverter NO1 is connected to the input end of the filtering unit 2313, the output end of the filtering unit 2313 is connected to the input end of the fourth inverter NO41, the output end of the fourth inverter NO41 is connected to the input end of the fourth inverter NO42, the output end of the fourth inverter NO42 is connected to the set end of the first latch 2311, the output end of the first latch 2311 is connected to the input end of the second inverter NO2, the output end of the second inverter NO2 is connected to the input end of the delay unit 2312 and the input end of the third inverter NO3, the output end of the delay unit 2312 is connected to the reset end of the first latch 2311, and the output end of the third inverter NO3 outputs the first pulse width locking signal, and the pulse width of the first pulse width locking signal is set by setting the delay time of the delay unit 2312.

[0142] For example, the first protection signal Pro1 is effective at a high level. When the power device MP has an overcurrent / de-saturation, the first protection signal Pro1 generates a high level pulse. After passing through the first inverter NO1 and the filter unit 2313, the driving capability is improved through the fourth inverters NO41 and NO42 and sent to the set end of the first latch 2311, so that the output signal of the first latch 2311 is high level. The inverted signal of the output signal of the first latch 2311 is fed back to the reset end of the first latch 2311 through the delay unit 2312. By setting the delay time of the delay unit 2312, the high level time of the output end of the first latch 2311 can be set, so that the pulse width of the first pulse width locking signal is set to the first pulse width t1. In this embodiment, the set end of the first latch 2311 is a low level trigger set, and the reset end of the first latch 2311 is a low level trigger reset.

[0143] It can be understood that the fourth inverters NO41 and NO42 can improve the driving capability of the first protection signal Pro1, so that the first protection signal Pro1 can drive the output signal of the first latch 2311 to flip. In some embodiments, the fourth inverters NO41 and NO42 can be omitted. In some embodiments, at least two pairs of the fourth inverters can also be set.

[0144] It can be understood that the filtering unit 2313 is used to filter out noise in the first protection signal Pro1 and improve the signal-to-noise ratio of the first protection signal Pro1. In some embodiments, the filtering unit 2313 can also be omitted.

[0145] In this embodiment, the first signal processing unit 23 also includes two first buffers connected in series, namely, a first buffer 234 and a first buffer 235. The first buffer 234 and the first buffer 235 are connected in series and connected to the output end of the multiplexer group to receive the coded signal OUT_L2, and output the coded signal OUT_L2 after buffering, thereby improving the driving ability of the coded signal OUT_L2. Further, the coded signal OUT_L2 output by the first buffer 234 is also input into the second logic circuit 26 as the second trigger signal Shut_s. When the second trigger signal Shut_s indicates that the state of the power device MP is abnormal (the pulse width segment of the second pulse width t2 does not appear), the second logic circuit 26 is turned off. In this way, before the low-voltage control unit 30 makes an effective protection action, the second trigger signal Shut_s can shut down the second logic circuit 26 in advance to ensure the safety of the subsequent circuit.

[0146] In some embodiments, one or both of the first buffer 234 and the first buffer 235 may be omitted.

[0147] In some embodiments, the encoding circuit 232 can be, for example, an oscillator circuit, which directly outputs a periodic pulse signal, namely, the second pulse width locking signal, when the second protection signal Pro2 is invalid; when the second protection signal Pro2 is valid, the oscillator circuit does not work.

[0148] In this embodiment, the multiplexer group includes a first multiplexer 2331, and the first multiplexer 2331 has a channel 1 and a channel 0, wherein the channel 1 receives the first pulse width locking signal, and the channel 0 receives the second pulse width locking signal. The first pulse width locking signal is effective to indicate that the first protection signal Pro1 is effective, and the effective first protection signal Pro1 indicates that the power device MP is overcurrent / de-saturated, and the second pulse width locking signal is effective to indicate that the second protection signal Pro2 is invalid, and the invalid second protection signal Pro2 indicates that the power device MP is not undervoltage.

[0149] For example, in the present disclosure, a high level is a valid state of the first protection signal Pro1, and a low level is an invalid state of the first protection signal Pro1; a low level is a valid state of the second protection signal Pro2, and a high level is an invalid state of the second protection signal Pro2; a high level is a valid state of the first pulse width locking signal, and a low level is an invalid state of the first pulse width locking signal; a periodic pulse is a valid state of the second pulse width locking signal, and a low level is an invalid state of the second pulse width locking signal.

[0150] When the first pulse width locking signal is valid, the first multiplexer 2331 selects to shield the input of channel 0 and outputs the first pulse width locking signal input of channel 1; when the first pulse width locking signal is invalid but the second pulse width locking signal is valid, the first multiplexer 2331 selects to output the second pulse width locking signal input of channel 0, and when both the first pulse width locking signal and the second pulse width locking signal are invalid, the first multiplexer 2331 selects to output the first pulse width locking signal input of channel 1 (actually outputs a low level), and the first multiplexer 2331 finally outputs the encoded signal OUT_L2.

[0151] Figure 4 This is a timing diagram of each signal provided in this embodiment. Figure 4 As shown, the first protection signal Pro1 is effective at a high level, and the second protection signal Pro2 is effective at a low level. In combination with actual conditions, when the power device MP has an overcurrent / de-saturation, the first protection signal Pro1 is at a high level, and the first pulse width locking signal has a high level pulse of the first pulse width t1. At this time, the first pulse width locking signal is effective, the first multiplexer 2331 outputs the first pulse width locking signal, and the encoding signal OUT_L2 has a pulse width segment of the first pulse width t1. When the power device MP has an undervoltage, the second protection signal Pro2 is at a low level, the encoding circuit 232 does not work, the second pulse width locking signal is invalid, and the encoding signal OUT_L2 is at a low level (assuming that the power device MP has not had an overcurrent / de-saturation). When the power device MP is not under-voltage, the second protection signal Pro2 is at a high level, the encoding circuit 232 starts working and outputs the second pulse width locking signal, the second pulse width locking signal generates a high-level pulse of the second pulse width t2, at this time the second pulse width locking signal is valid, the first multiplexer 2331 outputs the second pulse width locking signal, and the encoding signal OUT_L2 generates a pulse width segment of the second pulse width t2 (here it is assumed that the power device MP is not overcurrent / desaturated).

[0152] Please continue reading Figure 1In this embodiment, the primary processing module 10 includes a decoding unit 11 and a second signal processing unit 12. After receiving the coded signal OUT_L2 transmitted by the second receiver 13, the decoding unit 11 decodes the coded signal OUT_L2 to obtain the decoded signal; the second signal processing unit 12 is used to identify and process the decoded signal to obtain the indication signal.

[0153] In this embodiment, the decoded signal includes a first decoded signal Y OC and the second decoded signal Y UV , the first decoded signal Y OC When the first protection signal Pro1 is valid, the second decoding signal Y UV When both the first protection signal Pro1 and the second protection signal Pro2 are invalid, the second pulse width t2 is provided. UV is the same pulse width signal as the encoding signal OUT_L2. At this time, the second decoding signal Y UV When the first protection signal Pro1 is valid, the pulse width section has the first pulse width t1.

[0154] Figure 5 FIG. 1 is a structural block diagram of the decoding unit 11 provided in this embodiment. Figure 5 As shown, the decoding unit 11 includes a first signal shaping circuit 114 , a first pulse width selector 111 , a second pulse width selector 112 and a logic operation circuit 113 .

[0155] The first signal shaping circuit 114 is connected to the second receiver 13, and is used to receive the coded signal OUT_L2, and is used to shape the coded signal OUT_L2 and filter out noise. The first pulse width selector 111 and the second pulse width selector 112 are both connected to the first signal shaping circuit 114, so as to receive the shaped coded signal OUT_L2, and filter the coded signal OUT_L2, so as to respectively select a section of a predetermined pulse width range in the coded signal OUT_L2, and respectively output the first pulse width selection signal OUT_A and the second pulse width selection signal OUT_B. Among them, the first pulse width selector 111 is used to separate the part of the pulse width of the encoded signal OUT_L2 that is greater than the second predetermined value D2 to output the first pulse width selection signal OUT_A, and the second pulse width selector 112 is used to separate the part of the pulse width of the encoded signal OUT_L2 that is greater than the third predetermined value D1 to output the second pulse width selection signal OUT_B, the first pulse width t1 is greater than the second predetermined value D2, and the second pulse width t2 is greater than the third predetermined value D1 and less than the second predetermined value D2.

[0156] Specifically, the pulse width range selected by the first pulse width selector 111 and the second pulse width selector 112 can be designed according to the first pulse width t1 and the second pulse width t2. As the pulse width of the coded signal OUT_L2 is different (PW represents the pulse width of the coded signal OUT_L2), the characteristics of the output first pulse width selection signal OUT_A and the second pulse width selection signal OUT_B are shown in the following table:

[0157] Out_L2 Out_A Out_B The state of the power device MP 0≤PW<D1 0 0 Undervoltage D1≤PW<D2 0 Out_L2 normal PW≥D2 Out_L2 Out_L2 Overcurrent / Desaturation

[0158] It can be seen that the first pulse width selection signal OUT_A only has the part of the pulse width of the coding signal OUT_L2 that is greater than the second predetermined value, and the second pulse width selection signal OUT_B only has the part of the pulse width of the coding signal OUT_L2 that is greater than the third predetermined value. The first pulse width selection signal OUT_A and the second pulse width selection signal OUT_B can combine the three states of the power device MP (normal, overcurrent / desaturation, undervoltage).

[0159] Further, the logic operation circuit 113 receives the first pulse width selection signal OUT_A and the second pulse width selection signal OUT_B, and performs logic operation on the first pulse width selection signal OUT_A and the second pulse width selection signal OUT_B, thereby obtaining the first decoding signal Y OC and the second decoded signal Y UV .

[0160] In this embodiment, the first decoded signal YOC is the same signal as the first pulse width selection signal OUT_A, and can be used to indicate whether the first protection signal Pro1 is valid, that is, Y OC = Out_A, when Y OC = Out_L2 (a pulse width section having the first pulse width t1), it indicates that the first protection signal Pro1 is valid and the power device MP has an overcurrent / de-saturation; the second decoding signal Y UV It is the superposition signal of the first pulse width selection signal OUT_A and the second pulse width selection signal OUT_B, which can be used to indicate whether the second protection signal Pro2 is valid, that is, Y UV =Out_A+Out_B, when Y UV =0, indicating that the second protection signal Pro2 is valid, the power device MP is under-voltage. UV =Out_L2 (a pulse width section having the second pulse width t2), it indicates that both the first protection signal Pro1 and the second protection signal Pro2 are invalid, and the power device MP is normal.

[0161] Of course, the logic operation circuit 113 can also perform other logic calculations on the first pulse width selection signal OUT_A and the second pulse width selection signal OUT_B, as long as the first decoding signal Y OC and the second decoded signal Y UV The logic operation circuit 113 can be designed according to the above logic, and a specific circuit diagram is not given here.

[0162] In this embodiment, the indication signal includes a first indication signal F_G and a second indication signal R_G. The first indication signal F_G is used to OC When the pulse width segment of the first pulse width t1 appears, it indicates that the corresponding state of the power device MP is abnormal (in this embodiment, it indicates that the power device MP has an overcurrent / de-saturation), until a reset signal RST is valid, indicating that the corresponding state of the power device MP returns to normal; and the second indication signal R_G is used to UV When the pulse width segment of the second pulse width t2 appears, it indicates that the power device MP is operating normally, and at other times it indicates that the corresponding state of the power device MP is abnormal (in this embodiment, it indicates that undervoltage and overcurrent / desaturation occur in the power device MP).

[0163] Figure 6 : is a structural block diagram of the second signal processing unit 12 of this embodiment. Figure 6As shown, the second signal processing unit 12 includes a second signal shaping circuit 121, a third signal shaping circuit 122, a fourth signal shaping circuit 123, a second latch 124 and a timing circuit 125. The second signal shaping circuit 121 is connected to the logic operation circuit 113 and is used to receive the first decoding signal Y OC , and the first decoded signal Y OC The third signal shaping circuit 122 is connected to the low voltage control unit 30, and is used to receive the reset signal RST sent by the low voltage control unit 30, and to shape the reset signal RST to filter out noise; the set end and the reset end of the second latch 124 are respectively connected to the output ends of the second signal shaping circuit 121 and the third signal shaping circuit 122, so as to respectively receive the shaped first decoding signal Y OC and the reset signal RST, and outputs the first indication signal F_G. The fourth signal shaping circuit 123 is connected to the logic operation circuit 113 and is used to receive the second decoding signal Y UV , and the second decoded signal Y UV The timing circuit 125 is connected to the fourth signal shaping circuit 123 to receive the shaped second decoded signal Y UV , and outputs the second indication signal R_G.

[0164] In this embodiment, the reset signal RST is determined to be valid only when the reset signal RST flips from a first level value to a second level value and the duration of the second level value is greater than a first predetermined value.

[0165] Combination Figure 1 and 4 As shown, the reset signal RST is effective at a low level. When the first decoding signal Y OC When a rising edge signal appears, the second latch 124 is triggered to be set, and the first indication signal F_G of a high level is output, indicating that the first protection signal Pro1 is valid, and the power device MP has an overcurrent / de-saturation. The reset end of the second latch 124 receives the reset signal RST. After the overcurrent / de-saturation abnormal protection is triggered, whether the output end of the second latch 124 is reset is determined by whether the reset signal RST is valid. When the reset signal RST flips from a high level to a low level and the duration of the low level is greater than the first predetermined value, the reset signal RST is determined to be valid. At this time, the second latch 124 outputs the first indication signal F_G of a low level.

[0166] Furthermore, the timing circuit 125 can be configured to generate a signal when the second decoding signal Y UVWhen the duration of the low level of the second decoding signal YUV exceeds the internally preset width, the second indication signal R_G of high level is output, indicating that the second protection signal Pro2 is valid and the power device MP is under-voltage; when the duration of the low level of the second decoding signal YUV is less than the internally preset width, the second indication signal R_G of low level is output, indicating that the second protection signal Pro2 is invalid and the power device MP is working normally.

[0167] Please continue reading Figure 6 The second signal processing unit 12 further includes a second buffer 126 and a third buffer 127. The second buffer 126 is connected to the output end of the second latch 124 to receive the first indication signal F_G, and outputs the first indication signal F_G after buffering, thereby improving the driving ability of the first indication signal F_G. The third buffer 127 is connected to the output end of the timing circuit 125 to receive the second indication signal R_G, and outputs the second indication signal R_G after buffering, thereby improving the driving ability of the second indication signal R_G.

[0168] It should be noted that, in this embodiment, the primary processing module 10 further includes two MOS transistors, namely, a first MOS transistor M1 and a second MOS transistor M2. The gate of the first MOS transistor M1 receives the first indication signal F_G, which is used to control the on / off of the first MOS transistor M1. The drain of the first MOS transistor M1 outputs the first transfer signal FLT and transmits it back to the low-voltage control unit 30. The source of the first MOS transistor M1 is grounded. When the first indication signal F_G is at a high level, the first MOS transistor M1 is turned on, and the first transfer signal FLT is at a low level, indicating that the power device MP has an overcurrent / de-saturation. The gate of the second MOS transistor M2 receives the second indication signal R_G, which is used to control the on / off of the second MOS transistor M2. The drain of the second MOS transistor M2 outputs the second transfer signal RDY and transmits it back to the low-voltage control unit 30. The source of the second MOS transistor M2 is grounded. When the second indication signal R_G is at a high level, the second MOS transistor M2 is turned on, and the second transfer signal RDY is at a low level, indicating that an undervoltage occurs in the power device MP.

[0169] Further, the primary processing module 10 further includes an OR gate OR, the OR gate OR receives the first indication signal F_G and the second indication signal R_G, and outputs a first trigger signal Shut_p, the first trigger signal Shut_p is input into the first logic circuit 14, and when any of the indication signals indicates that the state of the power device MP is abnormal (the first indication signal F_G and / or the second indication signal R_G is at a high level), the first trigger signal Shut_p turns off the first logic circuit 14. In this way, before the low-voltage control unit 30 makes an effective protection action, the first trigger signal Shut_p can turn off the first logic circuit 14 in advance to ensure the safety of the subsequent circuit.

[0170] The following will be combined Figure 1 and Figure 4 The waveforms of the signals in the P1 phase are described in detail: At the initial moment of the P1 phase (before the T1 moment), the power device MP does not experience overcurrent / de-saturation and undervoltage. At this time, the first protection signal Pro1 is at a low level (invalid), the second protection signal Pro2 is at a high level (invalid), and the first decoding signal Y OC is low level, the second decoding signal Y UV The pulse width section of the second pulse width t2 appears. At this time, both the first transfer signal FLT and the second transfer signal RDY are at high level, indicating that the power device MP works normally.

[0171] At time T1 of phase P1, the power device MP is under-voltage. At this time, the first protection signal Pro1 is at a low level (invalid), the second protection signal Pro2 is at a low level (valid), and the first decoding signal Y OC is low level, the second decoding signal Y UV is also low level, timing the second decoding signal Y UV After the duration of the low level exceeds the internal preset width, a high level second indication signal R_G is generated to control the second transfer signal RDY to be pulled down to a low level, indicating that the power device MP has an undervoltage, and the second decoding signal Y UV The low level will continue until the power supply of the power device MP returns to normal (T5 moment). At T5 moment, the second protection signal Pro2 is flipped to a high level, and the second decoding signal Y UV A pulse width section of the second pulse width t2 appears.

[0172] At time T2 of the P1 phase, the power device MP has an overcurrent / de-saturation, at which time the first protection signal Pro1 is high (valid), the second protection signal Pro2 is low (valid), and the first decoding signal YOC When the pulse width segment of the first pulse width t1 appears, a high-level first indication signal F_G is generated to control the first transfer signal FLT to be pulled down to a low level, and the low level continues until the rising edge of the reset signal RST arrives (at time T4), and the first transfer signal FLT flips to a high level.

[0173] It is particularly pointed out that at time T6, the first transfer signal FLT maintains a low level while the rising edge of the reset signal RST arrives, but the duration of the reset signal RST is less than the first predetermined value, and the first transfer signal FLT cannot be flipped. The first transfer signal FLT still maintains a low level, which can improve the anti-interference performance of the circuit.

[0174] It should be noted that Figure 4 In the embodiment, the first transfer signal FLT and the second transfer signal RDY have a certain delay compared with the encoding signal OUT_L2, but this does not affect the implementation of the present invention.

[0175] Figure 7 FIG. 1 is a schematic diagram of the working mode of the gate drive circuit in this embodiment. Figure 7 As shown, the gate drive circuit mainly includes three modes: off-state mode, normal working mode and protection mode. When the power device MP is not powered normally (undervoltage), the gate drive circuit is in the off-state mode, at which time the second transfer signal RDY is at a low level and the first transfer signal FLT is at a high level. When the power supply of the power device MP returns to normal, the gate drive circuit enters the normal working mode from the off-state mode, and the first transfer signal FLT and the second transfer signal RDY are both at a high level; when overcurrent / de-saturation or undervoltage occurs during the normal working mode, the gate drive circuit enters the protection mode, and the first transfer signal FLT and / or the second transfer signal RDY are at a low level, until the effective reset signal is received or the power supply returns to normal, the gate drive circuit can enter the normal working mode from the protection mode. In addition, when the power device MP is not powered normally (undervoltage), the gate drive circuit is in the off mode. If a large current causes undervoltage or the overcurrent sampling terminal is fully biased, causing circuit damage, this state is an abnormal circuit state and will also cause the second transfer signal RDY / the first transfer signal FLT to be low and cannot be restored.

[0176] It should be noted that, in this embodiment, the primary processing module 10 is a primary chip, the secondary processing module 20 is a secondary chip, and the primary chip and the secondary chip are interconnected by wire bonding. The secondary chip has 4 pins, namely, a VCC pin, an OUT pin, a Desat / CSC pin, and a GND2 pin, wherein the VCC pin is used to receive a power supply voltage, the OUT pin is used to output a driving signal to the power device MP, the Desat / CSC pin is used to receive a terminal voltage on the first end of the resistor R0, and the GND2 pin is used for grounding. The primary chip has 6 pins, namely VDD pin, PWM pin, RST pin, RDY pin, FLT pin and GND1 pin, wherein the VDD pin is used to receive the power supply voltage, the PWM pin is used to receive the PWM control signal output by the low-voltage control unit 30, the RST pin is used to receive the reset signal RST output by the low-voltage control unit 30, the RDY pin is used to output the second transfer signal RDY to the low-voltage control unit 30, the FLT pin is used to output the first transfer signal FLT to the low-voltage control unit 30, and the GND1 pin is used for grounding.

[0177] Correspondingly, this embodiment also provides a gate driving method, which adopts the above-mentioned gate driving circuit.

[0178] Embodiment 2

[0179] Figure 8 Schematic diagram of the structure of the gate drive circuit provided in this embodiment. Figure 8 As shown, the difference from the first embodiment is that, in this embodiment, the protection signal also includes a third protection signal Pro3, and the priority of the third protection signal Pro3 is between the first protection signal Pro1 and the second protection signal Pro2. In this embodiment, the state detection unit also includes an overvoltage detection unit 28, and the overvoltage detection unit 28 is used to detect whether the power device MP is overvoltage and output an overvoltage signal, and the overvoltage signal is the third protection signal Pro3. Further, when the encoded signal OUT_L2 has a pulse width segment of the third pulse width t3, it indicates that the first protection signal Pro1 is invalid and the third protection signal Pro3 is valid. In addition, in order to facilitate subsequent decoding, the first pulse width t1 needs to be greater than the third pulse width t3, and the third pulse width t3 needs to be greater than the second pulse width t2.

[0180] It should be understood that the third protection signal Pro3 is not limited to having only one, and the third protection signal Pro3 may also have more than two. For example, the third protection signal Pro3 may be an overvoltage signal and an overtemperature signal. When there are more than two third protection signals Pro3, each of the third protection signals Pro3 has a different priority, and each of the third protection signals Pro3 corresponds to a different third pulse width t3, and the size of each third pulse width t3 is positively correlated with the priority of the corresponding third protection signal Pro3. When the coded signal OUT_L2 has a pulse width segment of the corresponding third pulse width t3, it indicates that the first protection signal Pro1 is invalid and the corresponding third protection signal Pro3 is valid.

[0181] Fig. 9 FIG. 2 is a structural block diagram of the first signal processing unit 23 provided in this embodiment. Fig. 9 As shown, in this embodiment, the first signal processing unit 23 includes a first pulse width locking circuit 231, a second pulse width locking circuit 236, an encoding circuit 232 and a multiplexer group. Among them, the first pulse width locking circuit 231 is connected to the overcurrent / de-saturation detection unit 21 to receive the first protection signal Pro1, and locks the pulse width of the first protection signal Pro1 to the first pulse width t1, so as to output a first pulse width locking signal. The second pulse width locking circuit 236 is connected to the overvoltage detection unit 28 to receive the third protection signal Pro3, and locks the pulse width of the third protection signal Pro3 to the third pulse width t3, so as to output a third pulse width locking signal. The encoding circuit 232 is connected to the undervoltage detection unit 22 to receive the second protection signal Pro2, and outputs a second pulse width locking signal when the second protection signal Pro2 is invalid, and the pulse width of the second pulse width locking signal is the second pulse width t2. The multiplexer group connects the first pulse width locking circuit 231, the second pulse width locking circuit 236 and the encoding circuit 232 to receive the first pulse width locking signal, the second pulse width locking signal and the third pulse width locking signal, and outputs the first pulse width locking signal when the first pulse width locking signal is valid, outputs the third pulse width locking signal when the first pulse width locking signal is invalid and the third pulse width locking signal is valid, and outputs the second pulse width locking signal when both the first pulse width locking signal and the third pulse width locking signal are invalid and the second pulse width locking signal is valid. The multiplexer group finally outputs the encoding signal OUT_L2.

[0182] It should be noted that when there are more than two third protection signals Pro3, there are also more than two second pulse width locking circuits 236. Each second pulse width locking circuit 236 receives the corresponding third protection signal Pro3, and locks the pulse width of the corresponding third protection signal Pro3 to the corresponding third pulse width t3, so as to output the corresponding third pulse width locking signal. At this time, when the first pulse width locking signal is invalid and at least two third pulse width locking signals are valid, the multiplexer group outputs the third pulse width locking signal corresponding to the third protection signal Pro3 with the highest priority.

[0183] The third pulse width locking signal is effective, indicating that the third protection signal Pro3 is effective, and the effective third protection signal Pro3 indicates that the power device MP is over-voltage. For example, in the present disclosure, a high level is an effective third protection signal Pro3, and a low level is an invalid third protection signal Pro3.

[0184] In this embodiment, the specific circuit structures of the first pulse width locking circuit 231 and the second pulse width locking circuit 236 can be as follows: Figure 3 As shown, Figure 3 When the first inverter NO1 receives the first protection signal Pro1, the third inverter NO3 outputs the first pulse width locking signal, and when the first inverter NO1 receives the corresponding third protection signal Pro3, the third inverter NO3 outputs the corresponding third pulse width locking signal. The pulse widths of the first pulse width locking signal and the corresponding third pulse width locking signal are set by setting the delay time of the corresponding delay unit 2312.

[0185] In this embodiment, the first signal processing unit 23 further includes two first buffers connected in series, namely, a first buffer 234 and a first buffer 235. The first buffer 234 and the first buffer 235 are connected in series and connected to the output end of the multiplexer group to receive the coded signal OUT_L2, and output the coded signal OUT_L2 after buffering, thereby improving the driving ability of the coded signal OUT_L2. Further, the coded signal OUT_L2 output by the first buffer 234 is also input into the second logic circuit 26 as the second trigger signal Shut_s. When the second trigger signal Shut_s indicates that the state of the power device MP is abnormal (the pulse width segment of the second pulse width t2 does not appear in the coded signal OUT_L2), the second logic circuit 26 is turned off. In this way, before the low voltage control unit 30 makes an effective protection action, the second trigger signal Shut_s can turn off the second logic circuit 26 in advance to ensure the safety of the subsequent circuit.

[0186] In some embodiments, one or both of the first buffer 234 and the first buffer 235 may be omitted.

[0187] In some embodiments, the encoding circuit 232 can be, for example, an oscillator circuit, which directly outputs a periodic pulse signal, namely, the second pulse width locking signal, when the second protection signal Pro2 is invalid; when the second protection signal Pro2 is valid, the oscillator circuit does not work.

[0188] Please continue reading Fig. 9 In this embodiment, the multiplexer group includes a first multiplexer 2331 and a second multiplexer 2332, and the first multiplexer 2331 and the second multiplexer 2332 both have channel 1 and channel 0. Channel 1 of the first multiplexer 2331 receives the first pulse width locking signal, and channel 0 receives the output signal of the second multiplexer 2332. Channel 1 of the second multiplexer 2332 receives the third pulse width locking signal, and channel 0 receives the second pulse width locking signal. When the third pulse width locking signal is valid, the second multiplexer 2332 selects to shield the input of channel 0 and outputs the third pulse width locking signal input by channel 1; when the third pulse width locking signal is invalid and the second pulse width locking signal is valid, the second multiplexer 2332 outputs the second pulse width locking signal input by channel 0; when both the third pulse width locking signal and the second pulse width locking signal are invalid, the second multiplexer 2332 outputs the third pulse width locking signal input by channel 1 (actually outputs a low level). When the first pulse width locking signal is valid, the first multiplexer 2331 selects to shield the input of channel 0 and outputs the first pulse width locking signal inputted by channel 1; when the first pulse width locking signal is invalid and the input signal of channel 0 is valid, the first multiplexer 2331 outputs the input signal of channel 0; when both the first pulse width locking signal and the input signal of channel 0 are invalid, the first multiplexer 2331 outputs the first pulse width locking signal inputted by channel 1 (actually outputs a low level). The first multiplexer 2331 finally outputs the coded signal OUT_L2.

[0189] It should be understood that when there are at least two third pulse width locking signals, the number of multiplexers can be increased, and different third pulse width locking signals can be input into channel 1 of the second multiplexer 2332 according to different priorities, thereby achieving the purpose of the present invention.

[0190] Fig.10 This is a timing diagram of each signal provided in this embodiment. Fig.10As shown, the first protection signal Pro1 and the third protection signal Pro3 are effective at high level, and the second protection signal Pro2 is effective at low level. In combination with actual conditions, when the power device MP has overcurrent / de-saturation, the first protection signal Pro1 is at a high level, the first pulse width locking signal generates a high level pulse of the first pulse width t1, at this time the first pulse width locking signal is effective, the multiplexer group outputs the first pulse width locking signal, and the encoding signal OUT_L2 generates a pulse width segment of the first pulse width t1. When the power device MP has an overvoltage, the third protection signal Pro3 is at a high level, the third pulse width locking signal generates a high level pulse of the third pulse width t3, at this time the third pulse width locking signal is effective, the multiplexer group outputs the third pulse width locking signal, and the encoding signal OUT_L2 generates a pulse width segment of the third pulse width t3 (assuming that the power device MP has not had overcurrent / de-saturation). When the power device MP is under-voltage, the second protection signal Pro2 is at a low level, the encoding circuit 232 does not work, the second pulse width locking signal is invalid, and the encoding signal OUT_L2 is at a low level (assuming that the power device MP does not have overcurrent / de-saturation). When the power device MP is not under-voltage, the second protection signal Pro2 is at a high level, the encoding circuit 232 starts working and outputs the second pulse width locking signal, and the second pulse width locking signal generates a high level pulse of the second pulse width t2. At this time, the second pulse width locking signal is valid, the multiplexer group outputs the second pulse width locking signal, and the encoding signal OUT_L2 generates a pulse width segment of the second pulse width t2 (assuming that the power device MP does not have overcurrent / de-saturation and overvoltage).

[0191] Furthermore, in this embodiment, the decoded signal also includes a third decoded signal Y OV Among them, the first decoded signal Y OC When the first protection signal Pro1 is valid, the pulse width segment has the first pulse width t1, and the third decoding signal Y OV When the corresponding third protection signal Pro3 is valid, the second decoding signal Y has a pulse width segment with the corresponding third pulse width t3. UV The pulse width segment has the second pulse width t2 when the first protection signal Pro1, the second protection signal Pro2 and the third protection signal Pro3 are all invalid.

[0192] Fig.11 FIG. 1 is a structural block diagram of the decoding unit 11 provided in this embodiment. Fig.11 As shown, in this embodiment, the decoding unit 11 includes a first signal shaping circuit 114 , a first pulse width selector 111 , a second pulse width selector 112 , a third pulse width selector 115 and a logic operation circuit 113 .

[0193] The first signal shaping circuit 114 is connected to the second receiver 13, and is used to receive the coded signal OUT_L2, and is used to shape the coded signal OUT_L2 and filter out noise. The first pulse width selector 111, the second pulse width selector 112 and the third pulse width selector 115 are all connected to the first signal shaping circuit 114, so as to receive the shaped coded signal OUT_L2, and filter the coded signal OUT_L2, so as to respectively select a section of a predetermined pulse width range in the coded signal OUT_L2, and respectively output the first pulse width selection signal OUT_A, the second pulse width selection signal OUT_B and the third pulse width selection signal OUT_C. The first pulse width selector 111 is used to separate the portion of the pulse width of the coded signal OUT_L2 greater than the second predetermined value D5 to output the first pulse width selection signal OUT_A; the second pulse width selector 112 is used to separate the portion of the pulse width of the coded signal OUT_L2 greater than the third predetermined value D4 to output the second pulse width selection signal OUT_B; the third pulse width selector 115 is used to separate the portion of the pulse width of the coded signal OUT_L2 greater than the fourth predetermined value D3 to output the third pulse width selection signal OUT_C. The first pulse width t1 is greater than the second predetermined value D5, the second pulse width t2 is greater than the fourth predetermined value D3 and less than the third predetermined value D4, and the third pulse width t3 is greater than the third predetermined value D4 and less than the second predetermined value D5.

[0194] Specifically, the pulse width ranges selected by the first pulse width selector 111, the second pulse width selector 112 and the third pulse width selector 115 can be designed according to the first pulse width t1, the second pulse width t2 and the third pulse width t3. With the different pulse widths of the coded signal OUT_L2 (PW represents the pulse width of the coded signal OUT_L2), the characteristics of the output first pulse width selection signal OUT_A and the second pulse width selection signal OUT_B are shown in the following table:

[0195]

[0196] It can be seen that the first pulse width selection signal OUT_A only has the part of the pulse width of the coding signal OUT_L2 that is greater than the second predetermined value D5, the second pulse width selection signal OUT_B only has the part of the pulse width of the coding signal OUT_L2 that is greater than the third predetermined value D4, and the third pulse width selection signal OUT_C ​​only has the part of the pulse width of the coding signal OUT_L2 that is greater than the fourth predetermined value D3. The first pulse width selection signal OUT_A, the second pulse width selection signal OUT_B and the third pulse width selection signal OUT_C ​​can combine four states of the power device MP (normal, overcurrent / desaturation, overvoltage, undervoltage).

[0197] Further, the logic operation circuit 113 receives the first pulse width selection signal OUT_A, the second pulse width selection signal OUT_B and the third pulse width selection signal OUT_C, and performs logic calculation on the first pulse width selection signal OUT_A, the second pulse width selection signal OUT_B and the third pulse width selection signal OUT_C, thereby obtaining the first decoding signal Y OC , the second decoded signal Y UV and the third decoded signal Y OV .

[0198] In this embodiment, the first decoded signal Y OC The signal which is the same as the first pulse width selection signal OUT_A can be used to indicate whether the first protection signal Pro1 is valid, that is, Y OC = Out_A, when Y OC = Out_L2 (having the pulse width section of the first pulse width t1), it indicates that the first protection signal Pro1 is valid and the power device MP has an overcurrent / de-saturation. UV It is the superposition signal of the first pulse width selection signal OUT_A, the second pulse width selection signal OUT_B and the third pulse width selection signal OUT_C, which can be used to indicate whether the second protection signal Pro2 is valid, that is, Y UV =Out_A+Out_B+Out_C, when Y UV =0, indicating that the second protection signal Pro2 is valid, the power device MP is under-voltage. UV = Out_L2 (having the second pulse width t2), it indicates that the power device MP is normal. OV The signal obtained by negating the first pulse width selection signal OUT_A and multiplying the second pulse width selection signal OUT_B and the third pulse width selection signal OUT_C ​​can be used to indicate whether the third protection signal Pro3 is valid, that is, When YOV =Out_L2 (a pulse width section having the third pulse width t3), it indicates that the third protection signal Pro3 is valid and an overvoltage occurs in the power device MP.

[0199] Of course, the logic operation circuit 113 can also perform other logic calculations on the first pulse width selection signal OUT_A, the second pulse width selection signal OUT_B and the third pulse width selection signal OUT_C, as long as the first decoding signal Y OC , the second decoded signal Y UV and the third decoded signal Y OV The logic operation circuit 113 can be designed according to the above logic, and a specific circuit diagram is not given here.

[0200] It can be understood that when the third protection signal Pro3 increases, the number of the third pulse width selectors 115 can be increased accordingly, and the corresponding pulse width range selected by the third pulse width selectors 115 can be set accordingly to obtain the corresponding third pulse width selection signal OUT_C, thereby combining more states of the power device MP. Afterwards, the logic operation circuit 113 can calculate the first pulse width selection signal OUT_A, the second pulse width selection signal OUT_B and the plurality of third pulse width selection signals OUT_C, thereby obtaining the corresponding third decoding signal Y OV .

[0201] In this embodiment, the indication signal includes a first indication signal F_G and a fourth indication signal K_G. The first indication signal F_G is used to OC When the pulse width segment of the first pulse width t1 appears, it indicates that the corresponding state of the power device MP is abnormal (the power device MP has overcurrent / de-saturation), until the reset signal RST is valid, indicating that the corresponding state of the power device MP returns to normal. The fourth indication signal K_G is used to UV When the pulse width segment of the second pulse width t2 appears, it indicates that the power device MP is working normally, and at other times it indicates that the corresponding state of the power device MP is abnormal (the power device MP has an undervoltage), and in the third decoding signal Y OVWhen the pulse width segment of the third pulse width t3 appears, it indicates that the corresponding state of the power device MP is abnormal (the power device MP has an overvoltage) within a predetermined time DTov, and after the predetermined time DTov until the second decoded signal YUV appears the pulse width segment of the second pulse width t2, it indicates that the corresponding state of the power device MP returns to normal. That is, the first indication signal F_G can indicate whether the power device MP is overcurrent / de-saturated, and the fourth indication signal K_G can indicate whether the power supply of the power device MP is normal.

[0202] Fig.12 FIG. 4 is a structural block diagram of the second signal processing unit of this embodiment. Fig.12 As shown, the second signal processing unit includes a second signal shaping circuit 121, a third signal shaping circuit 122, a fourth signal shaping circuit 123, a fifth signal shaping circuit 128, a first AND gate AND1, a third pulse width locking circuit 129, a second latch 124 and a timing circuit 125. The second signal shaping circuit 121 is connected to the logic operation circuit 113 and is used to receive the first decoding signal Y OC , and the first decoded signal Y OC The third signal shaping circuit 122 is connected to the low voltage control unit 30, and is used to receive the reset signal RST sent by the low voltage control unit 30, and to shape the reset signal RST to filter out noise. The set end and reset end of the second latch 124 are respectively connected to the output ends of the first signal shaping circuit 114 and the second signal shaping circuit 121, so as to respectively receive the shaped first decoding signal Y OC and the reset signal RST, and outputs the first indication signal F_G. The fourth signal shaping circuit 123 is connected to the logic operation circuit 113, and processes the second decoding signal Y UV The fifth signal shaping circuit 128 is connected to the logic operation circuit 113 and processes the third decoded signal Y OV The third pulse width locking circuit 129 receives the third decoded signal Y OV , and the third decoded signal Y OV The pulse width of the first AND gate AND1 is locked to the predetermined time DTov, and a third indication signal is output, wherein the third indication signal is a low level signal with a predetermined time DTov. The first AND gate AND1 receives the second decoded signal Y after shaping UV The timing circuit 125 is connected to the first AND gate AND1, and is used to receive the combined signal, and after the timing reaches a set time, the combined signal is inverted and output as the fourth indication signal K_G.

[0203] In this embodiment, the reset signal RST is determined to be valid only when the reset signal RST flips from a first level value to a second level value and the duration of the second level value is greater than a first predetermined value.

[0204] In this embodiment, the specific circuit structure of the third pulse width locking circuit 129 can be as follows: Figure 3 As shown, Figure 3 When the first inverter NO1 receives the third decoding signal Y OV When , the third inverter NO3 outputs the third indication signal. The pulse width of the third indication signal is set by setting the delay time of the corresponding delay unit 2312 (ie, setting the size of the predetermined time DTov).

[0205] Similar to the first embodiment, the reset signal RST is effective at a low level. OC When a rising edge signal appears, the second latch 124 is triggered to be set, and the first indication signal F_G of a high level is output, indicating that the first protection signal Pro1 is valid, and the power device MP has an overcurrent / de-saturation. The reset end of the second latch 124 receives the reset signal RST. After the overcurrent / de-saturation abnormal protection is triggered, whether the output end of the second latch 124 is reset is determined by whether the reset signal RST is valid. When the reset signal RST flips from a high level to a low level and the duration of the low level is greater than the first predetermined value, the reset signal RST is determined to be valid. At this time, the second latch 124 outputs the first indication signal F_G of a low level.

[0206] Furthermore, the timing circuit 125 can output the high-level fourth indication signal K_G to indicate that the second protection signal Pro2 is valid and the power device MP is under-voltage after the duration of the low level of the combined signal exceeds the internally preset width, and output the high-level fourth indication signal K_G to indicate that the third protection signal Pro3 is valid and the power device MP is over-voltage after the duration of the high level of the combined signal exceeds the internally preset width; when the duration of the low level of the combined signal is less than the internally preset width, the fourth indication signal K_G to indicate that the second protection signal Pro2 and the third protection signal Pro3 are invalid and the power device MP is working normally.

[0207] Please continue reading Fig.12The second signal processing unit further includes a second buffer 126 and a third buffer 127. The second buffer 126 is connected to the output end of the second latch 124 to receive the first indication signal F_G, and outputs the first indication signal F_G after buffering, thereby improving the driving capability of the first indication signal F_G. The third buffer 127 is connected to the output end of the timing circuit 125 to receive the fourth indication signal K_G, and outputs the fourth indication signal K_G after buffering, thereby improving the driving capability of the fourth indication signal K_G.

[0208] It should be noted that, in this embodiment, the primary processing module 10 further includes two MOS transistors, namely, a first MOS transistor M1 and a second MOS transistor M2. The gate of the first MOS transistor M1 receives the first indication signal F_G, which is used to control the on / off of the first MOS transistor M1. The drain of the first MOS transistor M1 outputs the first transfer signal FLT and transmits it back to the low-voltage control unit 30. The source of the first MOS transistor M1 is grounded. When the first indication signal F_G is at a high level, the first MOS transistor M1 is turned on, and the first transfer signal FLT is at a low level, indicating that the power device MP has an overcurrent / de-saturation. The gate of the second MOS transistor M2 receives the fourth indication signal K_G, which is used to control the on / off of the second MOS transistor M2. The drain of the second MOS transistor M2 outputs the second transfer signal RDY and transmits it back to the low-voltage control unit 30. The source of the second MOS transistor M2 is grounded. When the fourth indication signal K_G is at a high level, the second MOS transistor M2 is turned on, and the second transfer signal RDY is at a low level, indicating that undervoltage or overvoltage occurs in the power device MP.

[0209] Further, the primary processing module 10 further includes an OR gate OR, the OR gate OR receives the first indication signal F_G and the fourth indication signal K_G, and outputs a first trigger signal Shut_p, the first trigger signal Shut_p is input into the first logic circuit 14, and when any of the indication signals indicates that the state of the power device MP is abnormal (the first indication signal F_G and / or the fourth indication signal K_G is at a high level), the first trigger signal Shut_p turns off the first logic circuit 14. In this way, before the low-voltage control unit 30 makes an effective protection action, the first trigger signal Shut_p can turn off the first logic circuit 14 in advance to ensure the safety of the subsequent circuit.

[0210] The following will be combined Figure 8 and Fig.10The waveforms of the signals in the P2 phase are described in detail: At the initial moment of the P2 phase (moment T1), the power device MP is over-voltaged. At this time, the first protection signal Pro1 is at a low level (invalid), the second protection signal Pro2 is at a high level (invalid), the third protection signal Pro3 is at a high level (valid), and the third decoding signal Y OV The pulse width segment of the third pulse width t3 appears. At this time, the first transfer signal FLT is at a high level, and the second transfer signal RDY turns to a low level, indicating that the power device MP is over-voltage. The low level of the second transfer signal RDY will continue for the predetermined time DTov (until time T5). At time T5, the second decoding signal Y UV When the second pulse width t2 appears, the second transfer signal RDY turns to a high level, indicating that the power supply of the power device MP has returned to normal. At the middle moment of the P2 phase (T2), the power device MP has an overcurrent / de-saturation, at which time the first protection signal Pro1 turns to a high level (valid), and the first decoding signal Y OC When the pulse width segment of the first pulse width t1 appears, the first transfer signal FLT turns to a low level, and the low level continues until the rising edge of the reset signal RST arrives (at time T4), and the first transfer signal FLT turns to a high level. Among them, at time T3, although the second protection signal Pro2 turns from a high level to a low level, the duration of the low level of the second protection signal Pro2 is very short, so it will not affect the operation of the encoding circuit, and avoid the occurrence of malfunction caused by the level fluctuation of the second protection signal Pro2 due to circuit interference.

[0211] It is particularly noted that at time T6, the low level of the second transfer signal RDY has lasted for the predetermined time DTov, but at time T6, the second decoding signal Y UV The second transfer signal RDY will continue to be at a low level until the second decoding signal Y UV The pulse width segment of the second pulse width t2 appears (at time T7) and then flips to a high level, indicating that the power supply of the power device MP has returned to normal.

[0212] In summary, when the low level pulse width of the second transfer signal RDY is less than the predetermined time DTov, it indicates that the power device MP has an undervoltage. When the low level pulse width of the second transfer signal RDY is greater than or equal to the predetermined time DTov, it indicates that the power device MP has an undervoltage or overvoltage.

[0213] It should be noted that Fig.10In the embodiment, the first transfer signal FLT and the second transfer signal RDY have a certain delay compared with the encoding signal OUT_L2, but this does not affect the implementation of the present invention.

[0214] Fig.13 FIG. 1 is a schematic diagram of the working mode of the gate drive circuit in this embodiment. Fig.13 As shown, the gate drive circuit mainly includes three modes: off-state mode, normal working mode and protection mode. When the power device MP is not powered normally (undervoltage or overvoltage), the gate drive circuit is in the off-state mode, at which time the second transfer signal RDY is at a low level and the first transfer signal FLT is at a high level. When the power supply of the power device MP returns to normal, the gate drive circuit enters the normal working mode from the off-state mode, and the first transfer signal FLT and the second transfer signal RDY are both at a high level; when overcurrent / de-saturation, overvoltage or undervoltage occurs during the normal working mode, the gate drive circuit enters the protection mode, and the first transfer signal FLT and / or the second transfer signal RDY are at a low level, until the effective reset signal RST is received or the power supply returns to normal, the gate drive circuit can enter the normal working mode from the protection mode. In addition, when the power device MP is not powered normally (undervoltage), the gate drive circuit is in the off mode. If a large current causes undervoltage or the overcurrent sampling terminal is fully biased, causing circuit damage, this state is an abnormal circuit state and will also cause the second transfer signal RDY / the first transfer signal FLT to be output low and cannot be recovered.

[0215] Embodiment 3

[0216] Fig.14 Schematic diagram of the structure of the gate drive circuit provided in this embodiment. Fig.14 As shown, the difference from the second embodiment is that in this embodiment, the indication signal includes a first indication signal F_G, a second indication signal R_G and a third indication signal N_G. The first indication signal F_G is used to OC When the pulse width segment of the first pulse width t1 appears, it indicates that the corresponding state of the power device MP is abnormal (in this embodiment, it indicates that the power device MP has an overcurrent / de-saturation), until the reset signal RST is valid, indicating that the corresponding state of the power device MP has returned to normal. The third indication signal N_G is used to OVWhen the pulse width segment of the third pulse width t3 appears, it indicates that the corresponding state of the power device MP is abnormal (in this embodiment, it indicates that the power device MP has an overvoltage) within the predetermined time, and indicates that the corresponding state of the power device MP returns to normal after the predetermined time; the second indication signal R_G is used to UV When the pulse width segment of the second pulse width t2 appears, it indicates that the power device MP is working normally, and at other times it indicates that the corresponding state of the power device MP is abnormal (in this embodiment, it indicates that the power device MP is under-voltage). That is, the first indication signal F_G can indicate whether the power device MP is over-current / de-saturated, the second indication signal R_G can indicate whether the power device MP is under-voltage, and the third indication signal N_G can indicate whether the power device MP is over-voltage.

[0217] Fig.15 FIG. 4 is a structural block diagram of the second signal processing unit of this embodiment. Fig.15 As shown, the second signal processing unit includes a second signal shaping circuit 121, a third signal shaping circuit 122, a fourth signal shaping circuit 123, a fifth signal shaping circuit 128, a third pulse width locking circuit 129, a second latch 124 and a timing circuit 125. The second signal shaping circuit 121 is connected to the logic operation circuit 113 and is used to receive the first decoding signal Y OC , and the first decoded signal Y OC The third signal shaping circuit 122 is connected to the low voltage control unit 30, and is used to receive the reset signal RST sent by the low voltage control unit 30, and to shape the reset signal RST to filter out noise. The set end and reset end of the second latch 124 are respectively connected to the output ends of the first signal shaping circuit 114 and the second signal shaping circuit 121, so as to respectively receive the shaped first decoding signal Y OC and the reset signal RST, and outputs the first indication signal F_G. The fourth signal shaping circuit 123 is connected to the timing circuit 125, and processes the second decoding signal Y UV The timing circuit 125 receives the second decoded signal Y after shaping. UV , and outputs the second indication signal R_G. The fifth signal shaping circuit 128 is connected to the logic operation circuit 113, and processes the third decoding signal Y OV The third pulse width locking circuit 129 receives the third decoding signal Y OV , and the third decoded signal Y OVThe pulse width is locked to the predetermined time, and the third indication signal N_G is output.

[0218] In this embodiment, the reset signal RST is determined to be valid only when the reset signal RST flips from a first level value to a second level value and the duration of the second level value is greater than a first predetermined value.

[0219] Furthermore, the timing circuit 125 can be configured to generate a signal when the second decoding signal Y UV After the duration of the low level exceeds the internally preset width, the second indication signal R_G of high level is output, indicating that the second protection signal Pro2 is valid and the power device MP is under-voltage.

[0220] Please continue reading Fig.15 , the second signal processing unit 12 further includes a second buffer 126, a third buffer 127 and a fourth buffer 130. The second buffer 126 is connected to the output end of the second latch 124 to receive the first indication signal F_G, and outputs the first indication signal F_G after buffering, thereby improving the driving ability of the first indication signal F_G. The third buffer 127 is connected to the output end of the timing circuit 125 to receive the second indication signal R_G, and outputs the second indication signal R_G after buffering, thereby improving the driving ability of the second indication signal R_G. The fourth buffer 130 is connected to the output end of the third pulse width locking circuit 129 to receive the third indication signal N_G, and outputs the third indication signal N_G after buffering, thereby improving the driving ability of the third indication signal N_G.

[0221] It should be noted that, in this embodiment, the primary processing module 10 includes three MOS transistors, namely, a first MOS transistor M1, a second MOS transistor M2, and a third MOS transistor M3. The gate of the first MOS transistor M1 receives the first indication signal F_G, which is used to control the on and off of the first MOS transistor M1. The drain of the first MOS transistor M1 outputs the first transfer signal FLT and transmits it back to the low-voltage control unit 30. The source of the first MOS transistor M1 is grounded. When the first indication signal F_G is at a high level, the first MOS transistor M1 is turned on, and the first transfer signal FLT is at a low level, indicating that the power device MP has an overcurrent / de-saturation. The gate of the second MOS transistor M2 receives the second indication signal R_G, which is used to control the on and off of the second MOS transistor M2. The drain of the second MOS transistor M2 outputs the second transfer signal RDY and transmits it back to the low-voltage control unit 30. The source of the second MOS transistor M2 is grounded. When the second indication signal R_G is at a high level, the second MOS transistor M2 is turned on, and the second transfer signal RDY is at a low level, indicating that the power device MP is under-voltage. The gate of the third MOS transistor M3 receives the third indication signal N_G, and the third indication signal N_G is used to control the on and off of the third MOS transistor M3. The drain of the third MOS transistor M3 outputs the third transfer signal RDB and transmits it back to the low-voltage control unit 30, and the source of the third MOS transistor M3 is grounded. When the third indication signal N_G is at a high level, the third MOS transistor M3 is turned on, and the third transfer signal RDB is at a low level, indicating that the power device MP is over-voltage.

[0222] Further, the primary processing module 10 further includes an OR gate OR, the OR gate OR receives the first indication signal F_G, the second indication signal R_G and the third indication signal N_G, and outputs a first trigger signal Shut_p, the first trigger signal Shut_p is input into the first logic circuit 14, and when any of the indication signals indicates that the state of the power device MP is abnormal (at least one of the first indication signal F_G, the second indication signal R_G and the third indication signal N_G is at a high level), the first trigger signal Shut_p turns off the first logic circuit 14. In this way, before the low voltage control unit 30 makes an effective protection action, the first trigger signal Shut_p can turn off the first logic circuit 14 in advance to ensure the safety of the subsequent circuit.

[0223] In summary, the gate drive circuit and method provided in the embodiment of the present invention include a primary processing module and a secondary processing module, wherein the secondary processing module detects the state of the power device and obtains at least two protection signals, and the at least two protection signals are encoded and combined into one coded signal and transmitted back to the primary processing module through a protection signal transmission channel. The present invention only needs one protection signal transmission channel to simultaneously transmit multiple protection signals back to the primary processing module, the circuit is simple to implement, and the area, cost and packaging wiring complexity of the gate drive circuit are reduced, and the signal transmission is stable and reliable, and the process has universal applicability.

[0224] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referred to each other. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0225] It should also be noted that, although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

[0226] It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are merely used to distinguish between the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0227] It should also be recognized that the terms described herein are only used to describe specific embodiments and are not intended to limit the scope of the invention. It should be noted that the singular forms "a" and "an" used herein and in the appended claims include plural references unless the context clearly indicates otherwise. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices, and may include secondary steps and secondary devices. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or", rather than a logical "exclusive or", unless the context clearly indicates otherwise. In addition, the implementation of the method and / or device in the embodiments of the present invention may include performing the selected task manually, automatically, or in combination.

Claims

1. A gate drive circuit for driving a power device, characterized in that: It includes a primary processing module and a secondary processing module. The secondary processing module detects the state of the power device and obtains at least two protection signals. The at least two protection signals are encoded and combined into one encoded signal and transmitted back to the primary processing module through a protection signal transmission channel.

2. The gate driving circuit according to claim 1, wherein: After receiving the coded signal, the primary processing module decodes the coded signal to obtain at least two decoded signals, which are used to characterize the corresponding protection signals, and identifies and processes the decoded signals to obtain at least two indication signals indicating the corresponding states of the power device.

3. The gate driving circuit according to claim 2, characterized in that: The protection signal includes a first protection signal and a second protection signal, the priority of the first protection signal is higher than the priority of the second protection signal; and, When the coded signal has a pulse width segment of the first pulse width, it indicates that the first protection signal is valid; when the coded signal has a pulse width segment of the second pulse width, it indicates that both the first protection signal and the second protection signal are invalid, and the power device works normally.

4. The gate driving circuit according to claim 3, characterized in that: The first pulse width is greater than the second pulse width.

5. The gate driving circuit according to claim 3, characterized in that: The protection signal further includes a plurality of third protection signals, the priority of the third protection signals is between the first protection signal and the second protection signal, and the priority of each of the third protection signals is different; as well as, When the coded signal has a pulse width segment of a corresponding third pulse width, it indicates that the first protection signal is invalid and the corresponding third protection signal is valid, and each of the third pulse widths has a different size.

6. The gate driving circuit according to claim 5, characterized in that: The first pulse width is greater than each of the third pulse widths, each of the third pulse widths is greater than the second pulse width, and the size of each of the third pulse widths is positively correlated with the priority of the corresponding third protection signal.

7. The gate driving circuit according to claim 3, characterized in that: The decoding signal includes a first decoding signal and a second decoding signal, wherein the first decoding signal has a pulse width segment of the first pulse width when the first protection signal is valid, and the second decoding signal has a pulse width segment of the second pulse width when both the first protection signal and the second protection signal are invalid.

8. The gate driving circuit according to claim 5, characterized in that: The decoding signal includes a first decoding signal, a second decoding signal and several third decoding signals, the first decoding signal has a pulse width segment of the first pulse width when the first protection signal is valid, the third decoding signal has a pulse width segment of the corresponding third pulse width when the corresponding third protection signal is valid, and the second decoding signal has a pulse width segment of the second pulse width when the first protection signal, the second protection signal and the third protection signal are all invalid.

9. The gate driving circuit according to claim 7, characterized in that: The indication signal includes a first indication signal and a second indication signal; The first indication signal is used to indicate that the corresponding state of the power device is abnormal when the first decoded signal has a pulse width segment of the first pulse width, until a reset signal is valid, indicating that the corresponding state of the power device returns to normal; and The second indication signal is used to indicate that the power device is operating normally when the second decoded signal has a pulse width segment of the second pulse width, and to indicate that a corresponding state of the power device is abnormal at other times.

10. The gate driving circuit according to claim 8, characterized in that: The indication signal includes a first indication signal, a second indication signal and a plurality of third indication signals; The first indication signal is used to indicate that the corresponding state of the power device is abnormal when the first decoded signal has a pulse width segment of the first pulse width, until a reset signal is valid, indicating that the corresponding state of the power device returns to normal; The third indication signal is used to indicate that the corresponding state of the power device is abnormal within a predetermined time when the third pulse width segment of the third pulse width appears in the third decoded signal, and to indicate that the corresponding state of the power device returns to normal after the predetermined time; and The second indication signal is used to indicate that the power device is operating normally when the second decoded signal has a pulse width segment of the second pulse width, and to indicate that a corresponding state of the power device is abnormal at other times.

11. The gate driving circuit according to claim 8, characterized in that: The indication signal includes a first indication signal and a fourth indication signal; The first indication signal is used to indicate that the corresponding state of the power device is abnormal when the first decoded signal has a pulse width segment of the first pulse width, until a reset signal is valid, indicating that the corresponding state of the power device returns to normal; and The fourth indication signal is used to indicate that the power device is working normally when the second decoding signal has a pulse width segment of the second pulse width, and to indicate that the corresponding state of the power device is abnormal at other times, and to indicate that the corresponding state of the power device is abnormal within a predetermined time when the third decoding signal has a pulse width segment of the third pulse width, and to indicate that the corresponding state of the power device returns to normal after the predetermined time until the second decoding signal has a pulse width segment of the second pulse width.

12. The gate drive circuit according to any one of claims 9 to 11, characterized in that: When the reset signal flips from a first level value to a second level value, and the duration of the second level value is greater than a first predetermined value, the reset signal is determined to be valid.

13. The gate drive circuit according to any one of claims 1 to 11, characterized in that: The protection signal includes an overcurrent / de-saturation signal, an overvoltage signal, an overtemperature signal or an undervoltage signal.

14. The gate driving circuit according to claim 3, characterized in that: A high level is a valid state of the first protection signal, and a low level is an invalid state of the first protection signal; a low level is a valid state of the second protection signal, and a high level is an invalid state of the second protection signal.

15. The gate driving circuit according to claim 5, characterized in that: The high level is the valid state of the third protection signal, and the low level is the invalid state of the third protection signal.

16. The gate driving circuit according to claim 3, characterized in that: The secondary processing module comprises a first signal processing unit, wherein the first signal processing unit comprises: a first pulse width locking circuit, receiving the first protection signal, and locking the pulse width of the first protection signal to the first pulse width, so as to output a first pulse width locking signal; an encoding circuit, receiving the second protection signal, and outputting a second pulse width locking signal of the second pulse width when the second protection signal is invalid; and A multiplexer group receives the first pulse width locking signal and the second pulse width locking signal, and outputs the first pulse width locking signal when the first pulse width locking signal is valid, and outputs the second pulse width locking signal when the first pulse width locking signal is invalid and the second pulse width locking signal is valid, and the multiplexer group outputs the encoded signal.

17. The gate driving circuit according to claim 7, wherein: The primary processing module includes a decoding unit, and the decoding unit includes: a first pulse width selector, receiving the coded signal, and separating a portion of the coded signal having a pulse width greater than a second predetermined value, to output a first pulse width selection signal; a second pulse width selector, receiving the coded signal, and separating a portion of the coded signal whose pulse width is greater than a third predetermined value, to output a second pulse width selection signal; and a logic operation circuit, receiving the first pulse width selection signal and the second pulse width selection signal, and performing logic operation on the first pulse width selection signal and the second pulse width selection signal to obtain the first decoding signal and the second decoding signal; The first pulse width is greater than the second predetermined value, and the second pulse width is greater than the third predetermined value and less than the second predetermined value.

18. The gate driving circuit according to claim 17, wherein: The first decoded signal is the same signal as the first pulse width selection signal, and the second decoded signal is a superimposed signal of the first pulse width selection signal and the second pulse width selection signal.

19. The gate driving circuit according to claim 17, wherein: The decoding unit also includes: The first signal shaping circuit is used for shaping the coded signal and inputting it into the first pulse width selector and the second pulse width selector.

20. The gate driving circuit according to claim 9, characterized in that: The primary processing module further includes a second signal processing unit, wherein the second signal processing unit includes: a second latch, wherein a reset terminal of the second latch receives the reset signal, a set terminal of the second latch receives the first decoding signal, and an output terminal of the second latch outputs the first indication signal; and The timing circuit receives the second decoding signal and outputs the second indication signal.

21. The gate driving circuit according to claim 20, characterized in that: The second signal processing unit further includes: a second buffer connected to the output end of the second latch and used for buffering and outputting the first indication signal; a third buffer, connected to the output end of the timing circuit, and used for buffering and outputting the second indication signal; a second signal shaping circuit, receiving the first decoding signal, and configured to shape the first decoding signal and input the signal into the second latch; a third signal shaping circuit, receiving the reset signal, and configured to shape the reset signal and input it into the second latch; and A fourth signal shaping circuit receives the second decoded signal and is used for shaping the second decoded signal and inputting the signal into the timing circuit.

22. The gate driving circuit according to claim 5, characterized in that: The secondary processing module comprises a first signal processing unit, wherein the first signal processing unit comprises: a first pulse width locking circuit, receiving the first protection signal, and locking the pulse width of the first protection signal to the first pulse width, so as to output a first pulse width locking signal; an encoding circuit, receiving the second protection signal, and outputting a second pulse width locking signal of the second pulse width when the second protection signal is invalid; a plurality of second pulse width locking circuits, receiving the corresponding third protection signal, and locking the pulse width of the third protection signal to the corresponding third pulse width, so as to output a corresponding third pulse width locking signal; and, a multiplexer group, receiving the first pulse width locking signal, the second pulse width locking signal and the third pulse width locking signal, and outputting the first pulse width locking signal when the first pulse width locking signal is valid, When the first pulse width locking signal is invalid and the corresponding third pulse width locking signal is valid, the corresponding third pulse width locking signal is outputted, When the first pulse width locking signal is invalid and at least two of the third pulse width locking signals are valid, the third pulse width locking signal corresponding to the third protection signal with the highest priority is output, When the first pulse width locking signal and the third pulse width locking signal are invalid and the second pulse width locking signal is valid, the second pulse width locking signal is output, and the multiplexer group outputs the encoded signal.

23. The gate driving circuit according to claim 8, characterized in that: The primary processing module includes a decoding unit, and the decoding unit includes: a first pulse width selector, receiving the coded signal, and separating a portion of the coded signal having a pulse width greater than a second predetermined value, to output a first pulse width selection signal; a second pulse width selector, receiving the coded signal, and separating a portion of the coded signal having a pulse width greater than a third predetermined value, to output a second pulse width selection signal; a plurality of third pulse width selectors, receiving the coded signal, and separating the portion of the coded signal whose pulse width is greater than the corresponding fourth predetermined value, so as to output corresponding third pulse width selection signals; and, a logic operation circuit, receiving the first pulse width selection signal, the second pulse width selection signal and the third pulse width selection signal, and performing logic operation on the first pulse width selection signal, the second pulse width selection signal and the third pulse width selection signal to obtain the first decoding signal, the second decoding signal and the third decoding signal; Among them, the first pulse width is greater than the second predetermined value, the second pulse width is greater than the fourth predetermined value and less than the third predetermined value, and the third pulse width is greater than the third predetermined value and less than the second predetermined value.

24. The gate driving circuit according to claim 23, characterized in that: The first decoding signal is the same signal as the first pulse width selection signal, the second decoding signal is the superposition signal of the first pulse width selection signal, the second pulse width selection signal and the third pulse width selection signal, and the third decoding signal is the signal obtained by negating the first pulse width selection signal and multiplying the second pulse width selection signal and the third pulse width selection signal.

25. The gate driving circuit according to claim 23, characterized in that: The decoding unit also includes: The first signal shaping circuit is used for shaping the coded signal and inputting it into the first pulse width selector, the second pulse width selector and each of the third pulse width selectors.

26. The gate driving circuit according to claim 11, wherein: The primary processing module further includes a second signal processing unit, wherein the second signal processing unit includes: a second latch, wherein a reset terminal of the second latch receives the reset signal, a set terminal of the second latch receives the first decoding signal, and an output terminal of the second latch outputs the first indication signal; A plurality of third pulse width locking circuits, respectively receiving the corresponding third decoding signals, locking the pulse width of the third decoding signals to the predetermined time, and outputting corresponding third indication signals; a first AND gate, receiving the third indication signal and the second decoding signal, and outputting a combined signal; and The timing circuit receives the combined signal and outputs the fourth indication signal.

27. The gate driving circuit according to claim 26, characterized in that: The second signal processing unit further includes: a second buffer connected to the output end of the second latch and used for buffering and outputting the first indication signal; a third buffer, connected to the output end of the timing circuit, and used for buffering and then outputting the fourth indication signal; a second signal shaping circuit, receiving the first decoding signal, and configured to shape the first decoding signal and input the signal into the second latch; a third signal shaping circuit, receiving the reset signal, and configured to shape the reset signal and input it into the second latch; a fourth signal shaping circuit, receiving the second decoded signal, and configured to shape the second decoded signal and input the signal into the first AND gate; and The fifth signal shaping circuit receives the third decoded signal and is used for shaping the third decoded signal and inputting the signal into the corresponding third pulse width locking circuit.

28. The gate driving circuit according to claim 10, characterized in that: The primary processing module further includes a second signal processing unit, wherein the second signal processing unit includes: a second latch, wherein a reset terminal of the second latch receives the reset signal, a set terminal of the second latch receives the first decoding signal, and an output terminal of the second latch outputs the first indication signal; a plurality of third pulse width locking circuits, which respectively receive the corresponding third decoded signals, lock the pulse width of the third decoded signals to the predetermined time, and output the third indication signal; and, The timing circuit receives the second decoding signal and outputs the second indication signal.

29. The gate driving circuit according to claim 28, characterized in that: The second signal processing unit further includes: a second buffer connected to the output end of the second latch and used for buffering and outputting the first indication signal; a third buffer, connected to the output end of the timing circuit, and used for buffering and outputting the second indication signal; a fourth buffer, connected to the output end of the third pulse width locking circuit, and used for buffering and then outputting the third indication signal; a second signal shaping circuit, receiving the first decoding signal, and configured to shape the first decoding signal and input the signal into a second latch; a third signal shaping circuit, receiving the reset signal, and configured to shape the reset signal and input it into the second latch; a fourth signal shaping circuit, receiving the second decoded signal, and configured to shape the second decoded signal and input it into the timing circuit; and The fifth signal shaping circuit receives the third decoded signal and is used for shaping the third decoded signal and inputting the signal into the corresponding third pulse width locking circuit.

30. The gate driving circuit according to claim 16 or 22, characterized in that: The first signal processing unit further includes: At least one first buffer receives the encoded signal, and outputs the encoded signal after buffering it.

31. The gate driving circuit according to claim 16 or 22, characterized in that: The encoding circuit is an oscillator circuit.

32. The gate driving circuit according to claim 2, characterized in that: The primary processing module further includes at least two MOS tubes, the gates of the MOS tubes receive the corresponding indication signals, the drains of the MOS tubes output corresponding transmission signals and transmit them back to the low-voltage control unit, and the sources of the MOS tubes are grounded.

33. The gate driving circuit according to claim 2, characterized in that: The primary processing module further comprises a first logic circuit and a first transmitter connected in sequence, and the secondary processing module further comprises a first receiver, a second logic circuit and a driving circuit connected in sequence; The first logic circuit receives a PWM control signal, processes it, and then sends it to the first transmitter. The first transmitter sends the PWM control signal to the secondary processing module. The first receiver receives the PWM control signal sent by the first transmitter. The second logic circuit processes the PWM control signal and then inputs it into the drive circuit. The drive circuit outputs a drive signal to drive the power device.

34. The gate driving circuit according to claim 33, characterized in that: The primary processing module also includes: An OR gate receives all the indication signals and outputs a first trigger signal, wherein the first trigger signal turns off the first logic circuit when any of the indication signals indicates that the state of the power device is abnormal.

35. The gate driving circuit according to claim 33, characterized in that: The coded signal also serves as a second trigger signal, and the second trigger signal turns off the second logic circuit when indicating that the state of the power device is abnormal.

36. The gate driving circuit according to claim 1, wherein: The primary processing module further includes a second receiver, and the secondary processing module further includes a second transmitter. The second receiver and the second transmitter constitute the protection signal transmission channel, and the coded signal is sent to the second receiver via the second transmitter.

37. The gate driving circuit according to claim 1, characterized in that: The primary processing module is a primary chip, the secondary processing module is a secondary chip, and the primary chip and the secondary chip are interconnected by wire bonding.

38. The gate driving circuit according to claim 37, characterized in that: The gate driving circuit is an isolated gate driving circuit.

39. The gate driving circuit according to claim 38, characterized in that: The isolated gate driving circuit includes a magnetic isolation gate driving circuit or a capacitive isolation gate driving circuit.

40. A gate driving method, characterized in that: A gate drive circuit as claimed in any one of claims 1 to 39 is used.

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