Parasitic capacitance testing method
By forming doped regions and metal structures as electrodes on the substrate structure of a MOSFET, the parasitic capacitance between the doped regions is measured, solving the problem that the parasitic capacitance between the terminals inside the MOSFET cannot be measured in the prior art, and realizing accurate electrical analysis and process adjustment of semiconductor devices.
Patent Information
- Application Number
- CN202411565401.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-04
- Publication Date
- 2025-01-10
AI Technical Summary
Existing parasitic capacitance testing methods cannot test the parasitic capacitance between the internal terminals of a MOSFET, resulting in insufficient precision in semiconductor device performance tuning.
A parasitic capacitance testing method is provided, which measures the parasitic capacitance between doped regions by forming doped regions and metal structures on the substrate structure of a MOSFET, respectively, and connecting AC signals and DC bias signals.
It enables precise measurement of local parasitic capacitance in semiconductor devices, supports accurate analysis of device electrical properties and adjustment of process parameters, and simplifies the testing process.
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Figure CN119291441A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the field of semiconductor testing, and in particular to a parasitic capacitance testing method. Background Art
[0002] As the size of integrated circuit devices continues to shrink, parasitic capacitance has an increasingly greater impact on semiconductor devices, especially affecting the speed and power consumption of RF switching circuits. In integrated circuits, especially MOSFET tubes (Metal-Oxide-SemiconductorField-EffectTransistor, MOSFET), parasitic capacitance is inevitable. They are the capacitance formed between different areas of the internal structure of MOSFET. These capacitances have a significant impact on the high-frequency performance of MOSFET and must be considered when designing high-frequency circuits. It is generally believed that capacitance exists between any two of the four terminals of MOSFET, and the capacitance value is determined by the bias condition of MOSFET.
[0003] However, the existing parasitic capacitance test method can only test the parasitic capacitance of the MOSFET as a whole, but cannot test the parasitic capacitance between the internal terminals of the MOSFET, which is not conducive to more detailed adjustment of the performance of the semiconductor device.
[0004] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention
[0005] In view of the shortcomings of the prior art described above, an object of the present invention is to provide a parasitic capacitance testing method for solving the problem that the parasitic capacitance testing method in the prior art can only test the parasitic capacitance of the MOSFET as a whole, but cannot test the parasitic capacitance between the internal terminals of the MOSFET, which is not conducive to more detailed adjustment of the performance of the semiconductor device.
[0006] To achieve the above-mentioned object and other related objects, the present invention provides a parasitic capacitance testing method for testing the local parasitic capacitance of a semiconductor device, comprising:
[0007] The parasitic capacitance test method is implemented based on a parasitic capacitance test structure, which includes: a substrate structure, which includes a substrate, a buried oxide layer and an epitaxial layer from bottom to top; a first doped region and a second doped region, both of which are formed at least on the upper surface of the epitaxial layer; wherein the first doped region and the second doped region have opposite doping types, and the first doped region and the second doped region are electrically isolated; a first metal structure, which is formed on the first doped region; and a second metal structure, which is formed on the second doped region;
[0008] The parasitic capacitance testing method at least comprises:
[0009] S1, leading out the first doped region through the first metal structure and serving as a first electrode, and leading out the second doped region through the second metal structure and serving as a second electrode;
[0010] S2. Connect the same AC signal to the first electrode and the second electrode, and connect a preset DC bias signal to any one of the first electrode and the second electrode, and test to obtain the parasitic capacitance between the first doped region and the second doped region.
[0011] Optionally, the second doping region includes a first ion implantation region and a second ion implantation region, the first ion implantation region is formed between the first doping region and the second ion implantation region, and the doping concentration of the first ion implantation region is less than the doping concentration of the second ion implantation region; wherein the second metal structure is formed on the second ion implantation region.
[0012] Optionally, an upper surface of the first doped region and an upper surface of the second doped region are electrically isolated by a first blocking structure, wherein the first blocking structure is formed on the first ion implantation region.
[0013] Optionally, the wafer is divided into a device area and a test area, the test area is located outside the device area, the parasitic capacitance test structure is formed in the test area, and is prepared synchronously with the semiconductor device formed in the device area, wherein the parasitic capacitance test structure is electrically isolated from the semiconductor device by an isolation structure.
[0014] Optionally, when the first doped region is N-type doped and the second doped region is P-type doped, the DC bias signal is connected to the second electrode; when the first doped region is P-type doped and the second doped region is N-type doped, the DC bias signal is connected to the first electrode.
[0015] To achieve the above-mentioned object and other related objects, the present invention provides a parasitic capacitance testing method for testing the local parasitic capacitance of a semiconductor device, comprising:
[0016] The parasitic capacitance test method is implemented based on a parasitic capacitance test structure, wherein the parasitic capacitance test structure comprises: a substrate structure, which comprises a substrate, a buried oxide layer and an epitaxial layer in order from bottom to top; a third doped region, which is at least formed on the upper surface of the epitaxial layer; a gate structure, which is formed on the upper surface or inside of the epitaxial layer; the third doped region and the gate structure are electrically isolated; a third metal structure, which is formed on the third doped region; and a fourth metal structure, which is formed on the gate structure.
[0017] The parasitic capacitance testing method at least comprises:
[0018] S1, leading out the third doped region through a third metal structure and serving as a third electrode, and leading out the gate structure through a fourth metal structure and serving as a fourth electrode;
[0019] S2. Connecting the same AC signal to the third electrode and the fourth electrode, and connecting a preset DC bias signal to the fourth electrode, to test and obtain the parasitic capacitance between the third doped region and the gate structure.
[0020] Optionally, the parasitic capacitance test structure further includes a fourth doped region and a fifth metal structure;
[0021] The fourth doped region is formed at least on the upper surface of the epitaxial layer on the side of the gate structure away from the third doped region, and the fifth metal structure is formed on the fourth doped region and short-circuited with the third metal structure, wherein the fourth doped region is electrically isolated from the gate structure, and the fourth doped region has the same doping type as the third doped region.
[0022] Optionally, the third doped region is electrically isolated from the gate structure by a second blocking structure, wherein the second blocking structure includes a gate oxide layer and a first gate spacer.
[0023] Optionally, the fourth doped region is electrically isolated from the gate structure by a third blocking structure, wherein the third blocking structure includes the gate oxide layer and a second gate spacer.
[0024] Optionally, the wafer is divided into a device area and a test area, the test area is located outside the device area, the parasitic capacitance test structure is formed in the test area, and is prepared synchronously with the semiconductor device formed in the device area, wherein the parasitic capacitance test structure is electrically isolated from the semiconductor device by an isolation structure.
[0025] As described above, the parasitic capacitance testing method of the present invention has the following beneficial effects:
[0026] The present invention can measure each local capacitance of a semiconductor device, and compared with testing the entire semiconductor device, it can accurately analyze the electrical properties of the device and even adjust the process parameters for manufacturing. At the same time, the method of the present invention is simple and has a simple structure. It can directly detect the parasitic capacitance between the first doped region and the second doped region without introducing other interferences, and has a good application prospect. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] Figure 1 Shown is a structural schematic diagram of a MOSFET tube.
[0028] Figure 2 Shown is a structural schematic diagram of a parasitic capacitance testing structure of the present invention.
[0029] Figure 3 Display as Figure 2 Schematic diagram of the parasitic capacitance test structure prepared in the wafer area.
[0030] Figure 4 It is a schematic diagram showing the steps of a parasitic capacitance testing method of the present invention.
[0031] Figure 5 Shown is a structural schematic diagram of another parasitic capacitance testing structure of the present invention.
[0032] Figure 6 Display as Figure 5 Schematic diagram of the parasitic capacitance test structure prepared in the wafer area.
[0033] Figure 7 It is a schematic diagram showing the steps of another parasitic capacitance testing method of the present invention.
[0034] Component number description
[0035] 1 MOSFET
[0036] 10 Substrate
[0037] 11 Buried Oxide Layer
[0038] 12 Active layer
[0039] 121 Source region
[0040] 122 Body Area
[0041] 123 Drain region
[0042] 124 Shallow Trench Isolation Structure
[0043] 131 Gate oxide insulating layer
[0044] 132 Gate sidewall
[0045] 133 Gate Structure
[0046] 134 Sidewall deposition structure
[0047] 14 Contact hole
[0048] 15 Metal Structure
[0049] 2 Parasitic capacitance test structure
[0050] 21 Substrate structure
[0051] 211 Substrate
[0052] 212 buried oxygen layer
[0053] 213 Epitaxial layer
[0054] 2131 First doping region
[0055] 2132 Second doping region
[0056] 2132a Second ion implantation area
[0057] 2132b First ion implantation area
[0058] 2133 Isolation Structure
[0059] 22. First blocking structure
[0060] 23 First Metal Structure
[0061] 231 First contact hole
[0062] 232 first metal lead structure
[0063] 24 Second Metal Structure
[0064] 241 Second contact hole
[0065] 242 second metal lead structure
[0066] 3 Wafer
[0067] 30 Semiconductor devices
[0068] 31 Device Area
[0069] 32 Test Area
[0070] 4 Parasitic capacitance test structure
[0071] 41 Substrate structure
[0072] 411 Substrate
[0073] 412 buried oxide layer
[0074] 413 Epitaxial layer
[0075] 4131 Third doping region
[0076] 4132 Fourth doping region
[0077] 4133 Body Area
[0078] 4134 Isolation Structure
[0079] 42 Gate structure
[0080] 43 Third Metal Structure
[0081] 431 Third contact hole
[0082] 432 Third metal lead structure
[0083] 44 Fourth Metal Structure
[0084] 441 Fourth contact hole
[0085] 442 fourth metal lead structure
[0086] 45 Second blocking structure
[0087] 451 Gate Oxide Layer
[0088] 452 First gate sidewall
[0089] 453 First Sedimentary Structure
[0090] 46 Fifth Metal Structure
[0091] 461 Fifth contact hole
[0092] 462 Fifth Metal Lead Structure
[0093] 47 Third blocking structure
[0094] 471 Second gate sidewall
[0095] 472 Second deposition structure DETAILED DESCRIPTION
[0096] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0097] See also Figure 1 to Figure 7It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0098] like Figure 1 The device structure of a MOSFET tube 1 shown in the figure includes: a substrate 10; a buried oxide layer 11 grown on the substrate 10; an active layer 12 grown on the buried oxide layer 11, serving as an active region of the MOSFET tube 1; silicon dioxide (SiO2) grown on the surface of the active layer 12, serving as a gate oxide insulating layer 131 between a subsequent gate structure 133 and the substrate 10; a gate structure 133 is formed on the surface of the gate oxide insulating layer 131 by deposition, photolithography, etching, etc.; and a gate structure 133 is formed on both sides of the gate structure 133 by deposition, photolithography, etching, etc. The process forms a gate sidewall 132 and a sidewall deposition structure 134; ion implantation is performed in the active area not covered by the gate structure 133, the gate sidewall 132 and the sidewall deposition structure 134 to form a source region 121 and a drain region 123; the position covered by the gate structure 133 is used as the body region 122; in order to further electrically lead out the MOSFET tube 1, contact holes 14 are provided perpendicular to the surfaces of the gate structure 133, the source region 121 and the drain region 123, and a metal structure 15 is correspondingly provided at the other end of each contact hole 14. Among them, a shallow trench isolation structure 124 is provided in the active layer 12 close to the source region 121 and the drain region 123 and away from the gate structure 133.
[0099] The manufacturing process of MOSFET tube 1 on silicon wafer is called front-end process, and the process of connecting these manufactured MOSFET tubes 1 through metal layer and performing subsequent manufacturing is called back-end process. When the components (such as MOSFET tube 1) of the wafer are electrically tested by a probe station, for example, in the parasitic capacitance test, each contact hole 14 and each metal structure 15 need to be tested as a whole for parasitic capacitance, and the obtained result is not only the parasitic capacitance of the component front-end process ( Figure 1 In the figure, the first capacitor C1 to the sixth capacitor C6) also include the parasitic capacitors of the back-end process ( Figure 1 In the figure, the seventh capacitor C7 to the tenth capacitor C10). Generally, the parasitic capacitance generated by the metal interconnection in the back-end process can be measured by the de-embedded structure. Therefore, the device parasitic capacitance of the MOSFET tube 1, that is, the parasitic capacitance of the front-end process can be obtained by overall testing.
[0100] Generally speaking, when the MOSFET tube 1 is in the off state, the parasitic capacitance can be divided into: the parasitic capacitance of the area covered by the gate structure 133 and the source region 121 (first capacitance C1); the parasitic capacitance of the area covered by the gate structure 133 and the drain region 123 (second capacitance C2); the sidewall capacitance between the gate structure 133 and the gate sidewall 132 of the source region 121 and the sidewall deposition structure 134 (third capacitance C3); the sidewall capacitance between the gate structure 133 and the gate sidewall 132 of the drain region 123 and the sidewall deposition structure 134 (fourth capacitance C4); the junction capacitance between the source region 121 and the substrate 122 (fifth capacitance C5); the junction capacitance between the drain region 123 and the substrate 122 (sixth capacitance C6). However, the above measurement method is for measuring all the parasitic capacitances of the front-end process, and cannot be used for measuring local parasitic capacitances (parasitic capacitances of each part), which also makes it difficult to regulate the electrical performance of the device in a more detailed manner. For example, in order to achieve a certain process manufacturing effect, it is necessary to adjust and increase the junction capacitance (fifth capacitor C5 and sixth capacitor C6) between the source region 121 or the drain region 123 and the substrate 122, and the above measurement method cannot provide help. Therefore, it is necessary to provide a new parasitic capacitance test method that can measure the local capacitance of the semiconductor device, so as to facilitate the subsequent accurate analysis of the device electrical properties and even further adjustment of the device process, so as to manufacture a device that better meets the requirements.
[0101] Embodiment 1
[0102] like Figure 2 As shown, this embodiment provides a parasitic capacitance test structure 2 for testing the local parasitic capacitance of a semiconductor device. The parasitic capacitance test structure 2 of this embodiment includes:
[0103] The substrate structure 21 includes a substrate 211 , a buried oxide layer 212 and an epitaxial layer 213 from bottom to top. The substrate structure 21 is a SOI (Silicon-On-Insulator) substrate. In this embodiment, the substrate 211 and the epitaxial layer 213 are both doped with P type.
[0104] like Figure 2 As shown, the parasitic capacitance test structure 2 includes a first doped region 2131 and a second doped region 2132, both of which are formed at least on the upper surface of the epitaxial layer 213. The doping types of the first doped region 2131 and the second doped region 2132 are opposite, and the first doped region 2131 and the second doped region 2132 are respectively obtained on the surface of the epitaxial layer 213 by ion implantation, and the parasitic capacitance between the first doped region 2131 and the second doped region 2132 is measured based on the subsequent parasitic capacitance test method.
[0105] Specifically, the first doping region 2131 is set to be N-type doped, and the second doping region 232 is set to be P-type doped; the first doping region 2131 can also be set to be P-type doped, and the second doping region 2132 can be set to be N-type doped. The specific doping type is not limited to this embodiment.
[0106] In this embodiment, the first doped region 2131 and the second doped region 2132 are independent, and a PN junction is formed at the contact position due to the doping process. By testing these two regions, the junction capacitance Ca of the PN junction can be obtained. In this embodiment, the first doped region 2131 is set as the source, and the first doped region 2131 can also be set as the drain according to the actual device needs to be tested.
[0107] like Figure 3 As shown, the parasitic capacitance test structure 2 further includes a first metal structure 23 formed on the first doped region 2131 and serving as a first electrode T1 ; and a second metal structure 24 formed on the second doped region 2132 and serving as a second electrode T2 .
[0108] Specifically, a test signal (at least one of an AC signal and a biased DC signal) is loaded onto the first doped region 2131 through the first metal structure 23, so that the first doped region 2131 as a whole is regarded as the first plate of the capacitor; a test signal is loaded onto the second doped region 2132 through the second metal structure 24, so that the second doped region 2132 as a whole is regarded as the second plate of the capacitor.
[0109] As an example, in this embodiment, the second doping region includes a first ion implantation region 2132a and a second ion implantation region 2132b, the first ion implantation region 2132a is formed between the first doping region 2131 and the second ion implantation region 2132b, and the doping concentration of the first ion implantation region 2132a is less than the doping concentration of the second ion implantation region 2132b; wherein the second metal structure 24 is formed on the second ion implantation region 2132b. In this embodiment, the two parts of the second doping region 2132 have different ion implantation concentrations, but the ion implantation type is the same, and can be regarded as one in testing.
[0110] In this embodiment, the first metal structure 23 and the second metal structure 24 are both formed by metal processing. The first metal structure includes a first contact hole 231 and a first metal lead structure 232; the second metal structure 24 includes a second contact hole 241 and a second metal lead structure 242. In this embodiment, each contact hole is obtained by depositing metals such as titanium, cobalt, tungsten, etc. on the surface of the first doped region 2131 and the second doped region 2132 by physical vapor deposition (PVD) or chemical vapor deposition (CVD) and annealing. The contact hole can ensure that the electrical signal can be transmitted between the semiconductor device and the metal interconnection layer. After the contact hole is formed, each metal lead structure is formed by depositing a barrier layer thereon and depositing metals such as aluminum or copper again. In order to meet the transmission requirements, the metal interconnection will be provided with multiple layers, and the connection methods of each layer may be different based on design requirements. The metal lead structure in this embodiment is only a schematic structure of the connection between the first metal interconnection layer and the contact hole, and the subsequent multi-layer structure of the metal interconnection is not limited to this embodiment.
[0111] It should be noted that since the first metal structure 23 and the second metal structure 24 need to introduce the test signal to the two plates of the capacitor respectively, the first metal structure 23 and the second metal structure 24 also need to be electrically isolated, that is, the first metal structure 23 and the second metal structure 24 are not connected.
[0112] It should be further explained that, since the parasitic capacitance test structure 2 provided in this embodiment has less metal introduced based on the back-end process (contact hole manufacturing and metal interconnection manufacturing processes), the parasitic capacitance between the first metal structure 23 and the second metal structure 24 is negligible relative to the parasitic capacitance (junction capacitance Ca) between the first doped region 2131 and the second doped region 2132 being tested.
[0113] like Figure 2 As shown, the first doped region 2131 and the second doped region 2131 are electrically isolated from each other.
[0114] Specifically, in the present embodiment, the upper surface of the first doped region 2131 and the upper surface of the second doped region 2131 are electrically isolated by the first blocking structure 22 , wherein the first blocking structure 22 is formed on the first ion implantation region 2132 a .
[0115] In this embodiment, the electrical isolation between the first doped region 2131 and the second doped region 2131 includes an electrical isolation region formed by the PN junction itself (eg, Figure 2The first doping region 2132 is provided with a first blocking structure 22 on the surface of the second doping region 2132 near the first doping region 2131. In the present embodiment, the first blocking structure 22 is provided with a silicon nitride blocking layer. The silicon nitride blocking layer is mainly used to isolate the electrical signal on the upper surface of the epitaxial layer 213, so as to avoid the problem that the subsequent input test signal only flows on the surface of the epitaxial layer 213 when it is introduced through the first metal structure 23 and the second metal structure 24, and cannot be introduced into the first doping region 2131 and the second doping region 2132, resulting in the junction capacitance Ca cannot be detected.
[0116] like Figure 2 and Figure 3 As shown, in the parasitic capacitance test structure 2 of the present embodiment, the wafer 3 is divided into a device area 31 and a test area 32, wherein the test area 32 is located at the periphery of the device area 31, the parasitic capacitance test structure 2 is formed in the test area 32, and is prepared synchronously with the semiconductor device formed in the device area 31, wherein the parasitic capacitance test structure 2 is electrically isolated from the semiconductor device 30 by the isolation structure 2133.
[0117] Specifically, the parasitic capacitance test structure 2 of this embodiment further includes an isolation structure 2133 disposed at both ends of the integrated structure after the first doped region 2131 and the second doped region 2132 are regarded as an integrated structure. In this embodiment, it is a shallow trench isolation, which is used to reduce leakage current between components and improve the isolation of the device.
[0118] It should be noted that the parasitic capacitance test structure 2 is prepared synchronously with the semiconductor device 30, including: the preparation conditions such as materials, structures, doping concentrations, and manufacturing processes are completely identical and the processes are synchronized. By synchronously preparing the parasitic capacitance test structure 2 and the semiconductor device 30, it can be ensured that the parasitic capacitance test structure 2 is consistent with the actual device in terms of materials and processes, thereby making the test results more reliable.
[0119] Based on the above parasitic capacitance test structure 2, as Figure 4 A parasitic capacitance testing method provided in the embodiment shown includes:
[0120] S1 , the first doped region 2131 is led out through the first metal structure 23 and serves as the first electrode T1 , and the second doped region 2132 is led out through the second metal structure 24 and serves as the second electrode T2 .
[0121] Specifically, it is assumed that the doping types of the first doping region 2131 and the second doping region 2132 are opposite, and at this time, there is a junction capacitance formed by a PN junction between the first doping region 2131 and the second doping region 2132. When the test signal is loaded on the first doping region and the second doping region respectively through the first metal structure 23 and the second metal structure 24, it is regarded as loading the test signal on the two plates of the capacitor, and the junction capacitance Ca in this embodiment is obtained by testing.
[0122] S2, connecting the same AC signal to the first electrode T1 and the second electrode T2, and connecting a preset DC bias signal to any one of the first electrode T1 and the second electrode T2, and testing to obtain the parasitic capacitance between the first doped region 2131 and the second doped region 2132.
[0123] Specifically, the frequency of the AC signal is set to 10kHz to 10MHz, such as 100kHZ, 500kHZ, 5MHZ, etc. In this embodiment, the frequency of the AC signal is set to 1MHZ.
[0124] Specifically, when the first doped region is N-type doped and the second doped region is P-type doped, the DC bias signal is connected to the second electrode T2; when the first doped region is P-type doped and the second doped region is N-type doped, the DC bias signal is connected to the first electrode T1. When testing parasitic capacitance, the direction of the bias signal loaded should be reverse bias (the direction of current is from P-type doping to N-type doping). This is because under reverse bias conditions, the barrier capacitance (also called depletion layer capacitance) of the PN junction is the main source of capacitance, and the diffusion capacitance plays a major role in forward bias due to the large forward current. When reverse biased, a very small reverse saturation current flows through the PN junction, and at this time the diffusion capacitance is very small, and the main capacitance effect comes from the barrier capacitance. Therefore, in order to measure the parasitic capacitance-voltage (CV) characteristic, it is usually required to apply a reverse bias. Similarly, it can also be set to test the parasitic capacitance-voltage (CV) characteristic under different biases, and then obtain corresponding test results, which is not limited to the present embodiment.
[0125] In this embodiment, the capacitance value of the parasitic capacitor is different under different DC biases. Therefore, in actual use, a preset DC bias signal can be set and the corresponding parasitic capacitor can be measured based on the needs of the subsequent device use environment.
[0126] Specifically, in order to facilitate the subsequent adjustment of semiconductor devices on the wafer, the parasitic capacitance test method also includes step S3; performing step S2 multiple times under each DC bias to obtain parasitic capacitances of different DC biases, and normalizing each parasitic capacitance to obtain parasitic capacitance per unit area; and calculating the parasitic capacitance of the semiconductor device based on the parasitic capacitance per unit area. Specifically, the parasitic capacitance of the structure formed based on the same process under the same bias is only regarded as a certain change due to the size. Therefore, in order to make the parasitic capacitance test method and parasitic capacitance test structure provided in this embodiment applicable to components on the same wafer or even different wafers, it is normalized to obtain the parasitic capacitance per unit area. The parasitic capacitance per unit area can be used in subsequent use to obtain the parasitic capacitance of components designed with different sizes by calculating, which is convenient for industrial measurement, manufacturing and adjustment of components.
[0127] It should be noted that in the test method of this embodiment, the substrate is not connected to any potential. Therefore, the parasitic capacitance test method of this embodiment is equivalent to directly detecting the parasitic capacitance between the first doped region 2131 and the second doped region 2132, and no other interference is introduced. The parasitic capacitance test method of this embodiment is simple, the test structure is simple, and it has good application prospects.
[0128] Embodiment 2
[0129] like Figure 5 As shown, the embodiment provides another parasitic capacitance test structure 4 for testing the local parasitic capacitance of a semiconductor device. The parasitic capacitance test structure 4 of this embodiment includes a substrate structure 41. The substrate structure 41 includes a substrate 411, a buried oxide layer 412, and an epitaxial layer 413. The specific positions are set with reference to the substrate structure 41 in the first embodiment, and will not be described one by one here.
[0130] like Figure 5 As shown, the parasitic capacitance test structure 4 of this embodiment includes a third doped region 4131 formed at least on the upper surface of the epitaxial layer 413. In this embodiment, the first doped region 4131 is set to be N-type doped, and can also be set to be P-type doped as needed.
[0131] like Figure 5 As shown, the parasitic capacitance test structure 4 further includes a gate structure 42 formed on the upper surface or inside of the epitaxial layer 413 .
[0132] Specifically, as a first example, Figure 5 As shown, the gate structure 42 is configured as a planar gate structure, that is, the gate structure 42 is configured on the top (upper surface) of the epitaxial layer 413 .
[0133] like Figure 5As shown, the parasitic capacitance test structure 4 of this embodiment further includes a third metal structure 43 formed on the third doped region 4131 and serving as a third electrode T3 ; and a fourth metal structure 44 formed on the gate structure 42 and serving as a fourth electrode T4 .
[0134] Specifically, in the present embodiment, the third doped region 4131 and the gate structure 42 are respectively regarded as two plates of a capacitor through the third metal structure 43 and the fourth metal structure 44 for electrical measurement. At this time, the parasitic capacitance measured includes the covering capacitance of the gate structure 42 covering the third doped region 4131 (the covering capacitance Cb or Cc of the projection of the gate structure 42 covering the source or drain part) and the side wall capacitance between the third doped region 4131 and the side of the gate structure 42 (the side wall capacitance Cd or Cd of the gate structure 42 and the source or drain part).
[0135] Furthermore, if Figure 4 As shown, a second blocking structure 45 for electrical isolation is further disposed between the third metal structure 43 and the fourth metal structure 44 .
[0136] In this embodiment, the third doped region 4131 is set as a source or a drain, and the second blocking structure 45 includes a gate oxide layer 451 and a first gate spacer 452. In this embodiment, the second blocking structure 45 also includes a first deposition structure 453 that is not removed during the spacer deposition.
[0137] As a second example (not shown in the figure), the gate structure can also be set as a trench gate structure, that is, the gate is constructed in a trench inside the silicon wafer to form a channel perpendicular to the surface of the silicon wafer. At this time, the second blocking structure is correspondingly adjusted to the part where the gate structure inside the substrate is isolated from the source or drain, and the other parts of the parasitic capacitance test structure 4 are adjusted accordingly, and the corresponding local parasitic capacitance can still be measured.
[0138] It should be noted that the third metal structure 43 of this embodiment includes a third contact hole 431 and a third metal lead structure 432; the fourth metal structure 44 includes a fourth contact hole 441 and a fourth metal lead structure 442. The configuration and preparation method thereof refer to the first embodiment and will not be described in detail here.
[0139] like Figure 5 As shown, the parasitic capacitance test structure 4 further includes a fourth doped region 4132 and a fifth metal structure 46 disposed on the epitaxial layer 413 .
[0140] Specifically, the fourth doped region 4132 is formed on the epitaxial layer surface of the gate structure 42 away from the third doped region 4131, and the fifth metal structure 46 is formed on the fourth doped region 4132 and short-circuited with the third metal structure 43, wherein the fourth doped region 4132 is electrically isolated from the gate structure 42, and the fourth doped region 4132 has the same doping type as the third doped region 4131. The fourth doped region 4132 and the third doped region 4131 are respectively disposed on both sides of the gate structure (gate structure 42).
[0141] In this embodiment, they are respectively arranged on both sides of the substrate portion (i.e., the body region 4133) covered by the gate structure 42; the fourth doped region 4132 has the same doping type as the third doped region 4131, and in this embodiment, both are N-type doping, and the body region 4133 is set to P-type doping.
[0142] As an example, the fourth doped region 4132 is electrically isolated from the gate structure 4131 by the third blocking structure 47, wherein the third blocking structure 47 between the fourth doped region 4132 and the gate structure 42 (including the gate oxide layer 451 and the second gate sidewall 471 shared with the second blocking structure 45, and also including the second deposition structure 472 not removed during the sidewall deposition); the fifth metal structure 46 disposed on the fourth doped region 4132 is short-circuited with the third metal structure 43, and both serve as the third electrode T3. The fifth metal structure 46 includes a fifth contact hole 461 and a fifth metal lead structure 462, and its arrangement and preparation method refer to the arrangement of the third metal structure 43 and the fourth metal structure 44, and will not be repeated here.
[0143] In this embodiment, the setting, test principle, and test method of the fourth doped region 4132 are the same as those of the third doped region 4131, and will not be described one by one here. In this embodiment, the third doped region 4132 and the fourth doped region 4131 are ion-implanted synchronously and used as the source and drain respectively, and measured by the third electrode T3 and the fourth electrode T4, which is equivalent to measuring the capacitance between the gate and the source (the gate-source covering part and the gate-source sidewall) and the capacitance between the gate and the drain (the gate-drain covering part and the gate-drain sidewall), that is: the gate structure covers the third doped region 4131 covering capacitance Cb (the projection of the gate structure 42 covers the source capacitance), the third doped region 4131 and the side wall capacitance Cd of the gate structure 42 (the side wall capacitance of the gate structure 42 and the source part), the gate structure 42 covers the fourth doped region 4142 covering capacitance Cc (the projection of the gate structure 42 covers the drain capacitance), and the fourth doped region 4142 and the side wall capacitance Ce of the gate structure 42 (the side wall capacitance of the gate structure and the drain part).
[0144] like Figure 5 and Figure 6 In the parasitic capacitance test structure 4 of the present embodiment, the wafer 3 is divided into a device area 31 and a test area 32, wherein the test area 31 is located outside the device area 32, the parasitic capacitance test structure 4 is formed in the test area 32, and is prepared synchronously with the semiconductor device 30 formed in the device area 31, wherein the parasitic capacitance test structure 4 is electrically isolated from the semiconductor device 30 by an isolation structure 4134.
[0145] like Figure 7 As shown, this embodiment also provides a parasitic capacitance testing method, which is implemented based on the above parasitic capacitance testing structure 4 and includes:
[0146] S1. Lead out the third doped region 4131 through the third metal structure 43 and use it as the third electrode T3. Also, lead out the gate structure 42 through the fourth metal structure 44 and use it as the fourth electrode T4.
[0147] S2, the third electrode T3 and the fourth electrode T4 are connected to the same AC signal, and a preset DC bias signal is connected to the fourth electrode T4, and the parasitic capacitance between the third doped region 4131 and the gate structure 42 is obtained by testing.
[0148] It should be noted that the parasitic capacitance test method of this embodiment can be set up accordingly with reference to the first embodiment, and will not be described one by one here. At the same time, the parasitic capacitance test method of this embodiment is not limited to the parasitic capacitance test structure 4 provided in this embodiment. It can be based on the actual wafer components to be measured as a reference, design a corresponding parasitic capacitance test structure and use the parasitic capacitance test method provided in this embodiment for measurement. The specific principles will not be described one by one here.
[0149] It should be further explained that the parasitic capacitance test methods of embodiment one and embodiment two can be applied independently or used together. For example, since the parasitic capacitance of the front-end process of the MOS tube can be measured in full, for the same MOS tube, the parasitic capacitance test structure of embodiment one can be set based on the same parameters, all parasitic capacitances of the front-end process are tested, and the local parasitic capacitance obtained by the test of embodiment one is directly subtracted to obtain the local parasitic capacitance of the remaining unmeasured parts (such as the parasitic capacitance between the gate and the source and the parasitic capacitance between the gate and the drain). Similarly, all parasitic capacitances of the front-end process can be measured, and the local parasitic capacitance obtained by the test of embodiment two is subtracted to obtain the local parasitic capacitance of the remaining untested parts. However, it is preferably set to the same MOS tube, and the parasitic capacitance test structure of embodiment one and embodiment two with the same parameters is set, and the multiple parasitic capacitances obtained by the parasitic capacitance test method are measured to reduce the test error as much as possible, thereby avoiding the measurement error caused by other factors affecting the parasitic capacitance measurement that may exist in the components themselves.
[0150] Based on the parasitic capacitance test method of the first embodiment and the second embodiment, the overall parasitic capacitance can be split and precisely measured to obtain the local parasitic capacitance of the semiconductor, so as to accurately analyze the shortcomings of the device and facilitate subsequent adjustments, which is conducive to promoting industrial precision analysis. For example, in order to achieve the effect of a certain process manufacturing, it is necessary to adjust the junction capacitance between the source / drain and the substrate and increase it. Then, based on the parasitic capacitance test method of the first embodiment and the second embodiment, it can be measured and adjusted to further meet the needs of more precise adjustment of semiconductor devices. At the same time, in this process, the parasitic capacitance changes between the gate and the drain can also be measured synchronously to obtain the best device manufacturing parameters through comprehensive analysis.
[0151] The present invention provides a parasitic capacitance test method, which is implemented based on a parasitic capacitance test structure. The parasitic capacitance test structure includes: a first doped region and a second doped region, which are formed on an epitaxial layer; wherein the first doped region and the second doped region are electrically isolated; a first metal structure, which is formed on the first doped region and serves as a first electrode; and a second metal structure, which is formed on the second doped region and serves as a second electrode. The parasitic capacitance test method connects the first electrode and the second electrode to the same AC signal, and connects a preset DC bias signal to any of the first electrode and the second electrode, and tests to obtain the parasitic capacitance between the first doped region or the second doped region and the substrate. The present invention can measure the local capacitances of semiconductor devices, can accurately analyze the electrical properties of the device, and can even adjust the process parameters for manufacturing.
[0152] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A parasitic capacitance testing method for testing the local parasitic capacitance of a semiconductor device, characterized in that: The parasitic capacitance test method is implemented based on a parasitic capacitance test structure, which includes: a substrate structure, which includes a substrate, a buried oxide layer and an epitaxial layer from bottom to top; a first doped region and a second doped region, both of which are at least formed on the upper surface of the epitaxial layer; wherein the first doped region and the second doped region have opposite doping types, and the first doped region and the second doped region are electrically isolated; a first metal structure, which is formed on the first doped region; and a second metal structure, which is formed on the second doped region; The parasitic capacitance testing method at least comprises: S1, leading out the first doped region through the first metal structure and serving as a first electrode, and leading out the second doped region through the second metal structure and serving as a second electrode; S2. Connect the same AC signal to the first electrode and the second electrode, and connect a preset DC bias signal to any one of the first electrode and the second electrode, and test to obtain the parasitic capacitance between the first doped region and the second doped region.
2. The parasitic capacitance testing method according to claim 1, characterized in that: The second doping region includes a first ion implantation region and a second ion implantation region, the first ion implantation region is formed between the first doping region and the second ion implantation region, and the doping concentration of the first ion implantation region is less than the doping concentration of the second ion implantation region; wherein the second metal structure is formed on the second ion implantation region.
3. The parasitic capacitance testing method according to claim 2, characterized in that: An upper surface of the first doped region and an upper surface of the second doped region are electrically isolated from each other by a first blocking structure, wherein the first blocking structure is formed on the first ion implantation region.
4. The parasitic capacitance testing method according to claim 1, characterized in that: The wafer is divided into a device area and a test area, wherein the test area is located outside the device area, the parasitic capacitance test structure is formed in the test area, and is prepared synchronously with the semiconductor device formed in the device area, wherein the parasitic capacitance test structure is electrically isolated from the semiconductor device by an isolation structure.
5. The parasitic capacitance testing method according to claim 1, characterized in that: When the first doped region is N-type doped and the second doped region is P-type doped, the DC bias signal is connected to the second electrode; when the first doped region is P-type doped and the second doped region is N-type doped, the DC bias signal is connected to the first electrode.
6. A parasitic capacitance testing method for testing the local parasitic capacitance of a semiconductor device, characterized in that: The parasitic capacitance test method is implemented based on a parasitic capacitance test structure, wherein the parasitic capacitance test structure comprises: a substrate structure, which comprises a substrate, a buried oxide layer and an epitaxial layer in order from bottom to top; a third doped region, which is at least formed on the upper surface of the epitaxial layer; a gate structure, which is formed on the upper surface or inside of the epitaxial layer; the third doped region and the gate structure are electrically isolated; a third metal structure, which is formed on the third doped region; and a fourth metal structure, which is formed on the gate structure. The parasitic capacitance testing method at least comprises: S1, leading out the third doped region through a third metal structure and serving as a third electrode, and leading out the gate structure through a fourth metal structure and serving as a fourth electrode; S2. Connecting the same AC signal to the third electrode and the fourth electrode, and connecting a preset DC bias signal to the fourth electrode, to test and obtain the parasitic capacitance between the third doped region and the gate structure.
7. The parasitic capacitance testing method according to claim 6, characterized in that: The parasitic capacitance test structure further includes a fourth doped region and a fifth metal structure; The fourth doped region is formed at least on the upper surface of the epitaxial layer on the side of the gate structure away from the third doped region, and the fifth metal structure is formed on the fourth doped region and short-circuited with the third metal structure, wherein the fourth doped region is electrically isolated from the gate structure, and the fourth doped region has the same doping type as the third doped region.
8. The parasitic capacitance testing method according to claim 7, characterized in that: The third doped region is electrically isolated from the gate structure by a second blocking structure, wherein the second blocking structure includes a gate oxide layer and a first gate sidewall.
9. The parasitic capacitance testing method according to claim 8, characterized in that: The fourth doped region is electrically isolated from the gate structure by a third blocking structure, wherein the third blocking structure includes the gate oxide layer and a second gate sidewall.
10. The parasitic capacitance testing method according to claim 6, characterized in that: The wafer is divided into a device area and a test area, wherein the test area is located outside the device area, the parasitic capacitance test structure is formed in the test area, and is prepared synchronously with the semiconductor device formed in the device area, wherein the parasitic capacitance test structure is electrically isolated from the semiconductor device by an isolation structure.