Semiconductor device and manufacturing method thereof, power module, power conversion circuit, and vehicle

Abstract

The invention discloses a semiconductor device, a power module, a power conversion circuit, and a vehicle. The semiconductor device comprises a semiconductor body which comprises a first surface and a second surface which are oppositely arranged; the semiconductor body further comprises a well region and a first region; the first surface is also provided with a first groove and a second groove; the voltage-withstanding layer is located in the second groove, and the voltage-withstanding layer covers the first bottom and the second side wall of the first groove; the gate structure is located in the first groove; the insulation resistance of the voltage-withstanding layer is greater than that of the insulating layer of the gate structure, and the voltage-withstanding layer is used for reducing a peak electric field at the bottom of the gate structure; the source electrode is located on the first surface. According to the technical scheme provided by the embodiment of the invention, the specific on-resistance of the semiconductor device and the peak electric field at the bottom of the gate structure are reduced, and the electrical performance of the semiconductor device is further improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle. Background Art

[0002] Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) of third-generation wide-bandgap semiconductors such as silicon carbide or gallium nitride has the characteristics of large critical breakdown electric field strength, high thermal conductivity, large bandgap width and high electron saturation drift velocity, making third-generation wide-bandgap semiconductor materials such as silicon carbide or gallium nitride a research hotspot for power semiconductor devices, and silicon carbide devices are given high expectations in high-power applications such as high-speed railways, hybrid vehicles, and intelligent high-voltage direct current transmission.

[0003] Currently, MOSFET semiconductor devices including trench gate structures cannot simultaneously reduce the specific on-resistance and the peak electric field at the bottom of the gate structure, resulting in relatively poor electrical performance of the semiconductor devices. Summary of the invention

[0004] The present invention provides a semiconductor device, a power module, a power conversion circuit and a vehicle, so as to reduce the specific on-resistance and the peak electric field at the bottom of the gate structure, thereby improving the electrical performance of the semiconductor device.

[0005] According to a first aspect of the present invention, there is provided a semiconductor device, comprising:

[0006] A semiconductor body, comprising a first surface and a second surface arranged opposite to each other; the semiconductor body further comprising a well region and a first area; the first area is arranged on the first surface, and the well region is arranged on a side of the first area away from the first surface; the first surface is further provided with a first trench and a second trench, the first trench is arranged on the first surface, the second trench is connected to the first trench, and the second trench is located between the first trench and the second surface; the conductivity type of the first area is the same as and opposite to the conductivity type of the well region; the first trench comprises a first sidewall and a second sidewall arranged opposite to each other; the second trench comprises a third sidewall and a fourth sidewall arranged opposite to each other; the direction of the first sidewall pointing to the second sidewall is parallel to the direction of the third sidewall pointing to the fourth sidewall;

[0007] A voltage-resistant layer, located in the second groove, and the voltage-resistant layer covers a surface where the second groove and the first groove meet and the second side wall;

[0008] A gate structure is located in the first trench; the gate structure includes an insulating layer and a gate electrode, the insulating layer is used to insulate and space the gate electrode and the semiconductor body, the insulation resistance of the voltage-resistant layer is greater than the insulation resistance of the insulating layer, and the voltage-resistant layer is used to reduce the peak electric field at the bottom of the gate structure;

[0009] A source electrode, located on the first surface;

[0010] The drain is located on the second surface.

[0011] According to a second aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising:

[0012] A semiconductor body is provided, comprising a first surface and a second surface arranged opposite to each other; the semiconductor body further comprises a well region and a first area; the first area is arranged on the first surface, and the well region is arranged on a side of the first area away from the first surface;

[0013] forming a first groove on the first surface, wherein the first groove comprises a first sidewall and a second sidewall disposed opposite to each other;

[0014] A second groove is formed in the first groove, wherein the second groove is connected to the first groove, and the second groove is located between the first groove and the second surface; the second groove includes a third sidewall and a fourth sidewall that are oppositely arranged; and the direction from the first sidewall to the second sidewall is parallel to the direction from the third sidewall to the fourth sidewall;

[0015] forming a voltage-resistant layer in the second groove and the first groove;

[0016] Removing part of the voltage-resistant layer in the first groove, so that the voltage-resistant layer is located in the second groove, and the voltage-resistant layer covers the surface where the second groove and the first groove meet and the second side wall;

[0017] forming a gate structure in the first trench, the gate structure comprising an insulating layer and a gate electrode, the insulating layer being used for insulating and spacing the gate electrode and the semiconductor body, the insulation resistance of the voltage-resistant layer being greater than the insulation resistance of the insulating layer, and the voltage-resistant layer being used for reducing a peak electric field at the bottom of the gate structure;

[0018] forming a source electrode on the first surface;

[0019] A drain electrode is formed on the second surface.

[0020] According to a third aspect of the present invention, there is provided a power module, comprising a substrate and at least one semiconductor device as described in any of the embodiments of the present invention, wherein the substrate is used for carrying the semiconductor device.

[0021] According to a fourth aspect of the present invention, there is provided a power conversion circuit, the power conversion circuit being used for one or more of current conversion, voltage conversion, and power factor correction;

[0022] The power conversion circuit includes a circuit board and at least one semiconductor device as described in any of the embodiments of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0023] According to a fifth aspect of the present invention, a vehicle is provided, comprising a load and a power conversion circuit as described in any of the embodiments of the present invention, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0024] In the MOSFET semiconductor device provided by the embodiment of the present invention, the voltage-resistant layer is located in the second groove, and the voltage-resistant layer covers the surface where the second groove and the first groove meet and the second side wall, that is, a large part of the bottom of the gate structure is embedded in the voltage-resistant layer. Since the insulation resistance of the voltage-resistant layer is greater than the insulation resistance of the insulating layer, the maximum electric field is transferred to the voltage-resistant layer at the bottom of the gate structure, thereby reducing the peak electric field at the bottom of the gate structure and avoiding the gate structure from being broken down. In the above-mentioned MOSFET semiconductor device, it is not necessary to set the source electrode to occupy the area of ​​the semiconductor body by the trench-type source electrode structure to reduce the peak electric field at the bottom of the trench-type gate structure, thereby reducing the specific on-resistance of the semiconductor device and improving the electrical performance of the semiconductor device. Among them, since the insulation resistance of the voltage-resistant layer is greater than the insulation resistance of the insulating layer and covers the second side wall of the first groove, in the present semiconductor device, the well region in contact with the first side wall serves as the channel of the semiconductor device, and the well region in contact with the second side wall does not serve as the channel of the semiconductor device, thereby enhancing the pressure-bearing capacity of the gate structure located at the second side wall and reducing the risk of the gate structure being broken down.

[0025] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0027] Figure 1 It is a structural schematic diagram of a semiconductor device provided by the prior art;

[0028] Figure 2 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention;

[0029] Figure 3 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0030] Figure 4 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0031] Figure 5 yes Figure 2 A schematic structural diagram of a second trench including two sub-trenches in a corresponding semiconductor device;

[0032] Figure 6 yes Figure 3 A schematic structural diagram of a second trench including two sub-trenches in a corresponding semiconductor device;

[0033] Figure 7 yes Figure 4 A schematic structural diagram of a second trench including two sub-trenches in a corresponding semiconductor device;

[0034] Figure 8 is a flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0035] Figure 9-Figure 18 It is a structural schematic diagram corresponding to each step of a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0036] Fig.19 yes Figure 8 A schematic diagram of the process included in S160;

[0037] Fig. 20 yes Figure 8 The process view included before S140;

[0038] Figure 21-22 yes Fig. 20 The structural schematic diagram corresponding to each step in the figure;

[0039] Fig.23 yes Fig. 20 The schematic diagram of the process included in S1401;

[0040] Fig.24 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0041] Fig.25 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0042] Fig.26 It is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0043] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solution in the embodiment of the present invention will be described clearly and completely in conjunction with the drawings in the embodiment of the present invention. Obviously, the described embodiment is only a part of the embodiment of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0044] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations of "including" and "having" are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or devices is not necessarily limited to those steps or devices that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0045] Figure 1 It is a schematic diagram of the structure of a semiconductor device provided by the prior art. Figure 1 As shown, the semiconductor device includes a semiconductor body 100, including a first surface 101 and a second surface 102 arranged opposite to each other. The semiconductor body 100 also includes a well region 103, a first region 104 and a third region 105, the conductivity type of the first region 104 is opposite to the conductivity type of the well region 103, the conductivity type of the third region 105 is the same as the conductivity type of the well region 103, and the doping concentration of the third region 105 is greater than the doping concentration of the well region 103. The first surface 101 is provided with a gate trench T1 and a source trench T2. The semiconductor device also includes a gate structure 200, a source structure 300 and a drain 400. The gate structure 200 includes a first insulating layer 201 and a gate electrode 202. The gate structure 200 is located in the gate trench T1. The spacer insulating layer 203 is used to space the gate structure 200 and the source structure 300. The source structure 300 is located in the source trench T2 , and includes a source 301 , an ohmic contact layer 302 , a polysilicon filling layer 303 and a second insulating layer 304 .

[0046] Figure 1The MOSFET semiconductor device shown is a double trench MOSFET semiconductor device, and the source structure 300 is located in the source trench T2. Although the setting of the source structure 300 can reduce the peak electric field at the first insulating layer 201 at the bottom of the gate structure 200, the source structure 300 occupies the area of ​​the semiconductor body 100, reduces the specific on-resistance of the semiconductor device, and makes the electrical performance of the semiconductor device relatively poor.

[0047] In order to reduce the specific on-resistance of a MOSFET semiconductor device and the peak electric field at the bottom of the gate structure, thereby improving the electrical performance of the semiconductor device, the embodiment of the present invention provides the following technical solutions:

[0048] like Figure 2 As shown, Figure 2 1 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention, the semiconductor device comprising: a semiconductor body 100, comprising a first surface 101 and a second surface 102 arranged opposite to each other; the semiconductor body 100 further comprises a well region 103 and a first region 104; the first region 104 is arranged on the first surface 101, and the well region 103 is arranged on a side of the first region 104 away from the first surface 101; the first surface 101 is further provided with a first trench T3 and a second trench T4, the first trench T3 is arranged on the first surface 101, the second trench T4 is connected to the first trench T3, and the second trench T4 is located between the first trench T3 and the second surface 102; the conductivity type of the first region 104 is the same as and opposite to the conductivity type of the well region 103; the first trench T3 comprises a first sidewall T01 and a second sidewall T02 arranged opposite to each other; the first trench T3 comprises a first sidewall T01 and a second sidewall T02 arranged opposite to each other; The second trench T4 includes a third side wall T03 and a fourth side wall T04 that are arranged opposite to each other; the direction in which the first side wall T01 points to the second side wall T02 is parallel to the direction in which the third side wall T03 points to the fourth side wall T04; a voltage-resistant layer 106 is located in the second trench T4, and the voltage-resistant layer 106 covers the surface T05 where the second trench T4 and the first trench T3 are connected and the second side wall T02; a gate structure 200 is located in the first trench T3; the gate structure 200 includes an insulating layer 201 and a gate electrode 202, the insulating layer 201 is used to insulate the gate electrode 202 and the semiconductor body 100, the insulation resistance of the voltage-resistant layer 106 is greater than the insulation resistance of the insulating layer 201, and the voltage-resistant layer 106 is used to reduce the peak electric field at the bottom of the gate structure 200; a source 305 is located on the first surface 101; and a drain 400 is located on the second surface 102.

[0049] For example, Figure 2As shown, the semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of the present invention, the semiconductor body 100 may also include a substrate 10 and a semiconductor layer formed by other processes. Among them, the epitaxial layer 20 is a semiconductor layer formed by a single epitaxial process on the basis of the substrate 10, and the epitaxial process includes chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD) and atomic layer epitaxy (ALE) and other processes.

[0050] Optionally, in other embodiments, the MOSFET semiconductor device may further include a third region, the conductivity type of the third region is the same as the conductivity type of the well region 103, the doping concentration of the third region is greater than the doping concentration of the well region 103, and the third region is electrically connected to the source 305 to form a good ohmic contact with the source 305. The third region is located on a side of the well region 103 away from the second surface 102.

[0051] In the MOSFET semiconductor device provided by the embodiment of the present invention, the voltage-resistant layer 106 is located in the second trench T4, and the voltage-resistant layer 106 covers the surface T05 where the second trench T4 and the first trench T3 meet and the second side wall T02, that is, a large part of the bottom of the gate structure 200 is embedded in the voltage-resistant layer 106. Since the insulation resistance of the voltage-resistant layer 106 is greater than the insulation resistance of the insulating layer 201, the maximum electric field is transferred to the voltage-resistant layer 106 at the bottom of the gate structure 200, thereby reducing the peak electric field at the bottom of the gate structure 200 and avoiding the gate structure 200 from being broken down. In addition, in the above-mentioned MOSFET semiconductor device, it is not necessary to set the source 305 as a trench-type source structure to occupy the area of ​​the semiconductor body 100 to reduce the peak electric field at the bottom of the trench-type gate structure 200, thereby reducing the specific on-resistance of the semiconductor device and improving the electrical performance of the semiconductor device. Among them, since the insulation resistance of the voltage-resistant layer 106 is greater than the insulation resistance of the insulating layer 201 and covers the second side wall T02 of the first trench T3, in the present semiconductor device, the well region 103 in contact with the first side wall T01 serves as a channel of the semiconductor device, while the well region 103 in contact with the second side wall T02 does not serve as a channel of the semiconductor device, thereby enhancing the pressure-bearing capacity of the gate structure 200 located at the second side wall T02 and reducing the risk of the gate structure 200 being broken down.

[0052] Optionally, based on the above technical solution, Figure 2 As shown, the vertical projection area of ​​the second trench T4 on the first surface 101 is smaller than the vertical projection area of ​​the first trench T3 on the first surface 101 .

[0053] Specifically, the vertical projection area of ​​the second trench T4 on the first surface 101 is smaller than the vertical projection area of ​​the first trench T3 on the first surface 101. Compared with the solution in which the vertical projection area of ​​the second trench T4 on the first surface 101 is equal to the vertical projection area of ​​the first trench T3 on the first surface 101, the area of ​​the semiconductor body 100 occupied by the voltage-resistant layer 106 is reduced, thereby reducing the specific on-resistance of the semiconductor device.

[0054] Optionally, based on the above technical solution, Figure 2 As shown, the vertical projections of the second side wall T02 and the fourth side wall T04 on the first surface 101 coincide with each other.

[0055] Specifically, the vertical projections of the second side wall T02 and the fourth side wall T04 on the first surface 101 overlap, and the vertical projection area of ​​the second trench T4 on the first surface 101 can be controlled by controlling the position of the third side wall T03, so that the vertical projection area of ​​the second trench T4 on the first surface 101 is smaller than the vertical projection area of ​​the first trench T3 on the first surface 101.

[0056] Optionally, based on the above technical solution, Figure 2 , in the direction perpendicular to the second surface 102 pointing to the first surface 101, the spacing between the two side walls of the second trench T4 is equal to half of the spacing between the two side walls of the first trench T3. On the one hand, half of the bottom of the gate structure 200 is embedded in the voltage-resistant layer 106. Since the insulation resistance of the voltage-resistant layer 106 is greater than the insulation resistance of the insulating layer 201, the maximum electric field is transferred to the voltage-resistant layer 106 at the bottom of the gate structure 200, thereby reducing the peak electric field at the bottom of the gate structure 200 and preventing the gate structure 200 from being broken down; on the other hand, the spacing between the two side walls of the second trench T4 is equal to the spacing between the two side walls of the first trench T3, which reduces the area of ​​the semiconductor body 100 occupied by the voltage-resistant layer 106 and reduces the specific on-resistance of the semiconductor device. The direction perpendicular to the second surface 102 pointing to the first surface 101 is the X direction in the figure.

[0057] Optionally, based on the above technical solution, Figure 2As shown, the gate structure 200 includes an insulating layer 201 and a gate electrode 202; the insulating layer 201 is at least located at the bottom T06 and the first side wall T01 of the first trench T3; the gate electrode 202 is located on the side of the insulating layer 201 and the voltage-resistant layer 106 in the first trench T3 away from the semiconductor body 100. In the direction perpendicular to the second surface 102 pointing to the first surface 101, the spacing between the first side wall T01 and the gate electrode 202 is smaller than the spacing between the gate electrode 202 and the second side wall T02. Specifically, the insulating layer 201 is at least located at the bottom T06 and the first side wall T01 of the first trench T3, and is used to insulate the gate electrode 202 from the semiconductor body 100, and the gate electrode 202 is used to access the gate electrical signal. In the direction perpendicular to the second surface 102 pointing to the first surface 101, the spacing between the first side wall T01 and the gate electrode 202 is smaller than the spacing between the gate electrode 202 and the second side wall T02, which is used to increase the thickness of the voltage-resistant layer 106 located on the second side wall T02, thereby increasing its insulation resistance, so as to achieve the function of the voltage-resistant layer 106 for reducing the peak electric field at the bottom of the gate structure 200, and enhance the pressure-bearing capacity of the gate structure 200 located at the first side wall T01. In the embodiment of the present invention, the direction from the second surface 102 to the first surface 101 is the Y direction in the figure.

[0058] Exemplarily, the insulating layer 201 includes a high-k dielectric layer such as silicon dioxide, aluminum oxide, hafnium oxide, etc. When the insulating layer 201 is silicon dioxide, it can be obtained by performing an oxidation process on the semiconductor body 100. The voltage-resistant layer 106 includes at least one of silicon oxide, silicon nitride and polysilicon.

[0059] The example in which the insulating layer 201 includes silicon dioxide is used for the following description. Figure 2 As shown, the insulating layer 201 includes silicon dioxide, and the voltage-resistant layer 106 includes silicon dioxide. Figure 3 As shown, Figure 3 1 is a schematic diagram of the structure of another semiconductor device provided by an embodiment of the present invention, wherein the insulating layer 201 comprises silicon dioxide, and the voltage-resistant layer 106 comprises silicon nitride. Figure 4 As shown, Figure 4 1 is a schematic diagram of the structure of another semiconductor device provided by an embodiment of the present invention, wherein the insulating layer 201 includes silicon dioxide, and the voltage-resistant layer 106 includes polysilicon.

[0060] like Figure 2 and Figure 3 As shown, when the material of the voltage-resistant layer 106 and the material of the insulating layer 201 are the same, or are both insulating materials, the insulating layer 201 is located at the bottom T06 and the first sidewall T01 of the first trench T3 .

[0061] Optionally, based on the above technical solution, Figure 4As shown, when the material of the voltage-resistant layer 106 is conductive, such as polysilicon with weak conductivity, the insulating layer 201 is located on the first side wall T01, the bottom T06 of the first trench T3, and on the surface of the voltage-resistant layer 106 away from the semiconductor body 100. The insulating layer 201 is located on the surface of the voltage-resistant layer 106 away from the semiconductor body 100 and is used to insulate the gate electrode 202 and the voltage-resistant layer 106.

[0062] Alternatively, if Figure 2 As shown, the semiconductor device further includes a spacer insulating layer 203 and an ohmic contact layer 302. The spacer insulating layer 203 is used to space the gate structure 200 and the source 305. The ohmic contact layer 302 enables the source 305 to form a good ohmic contact with the first region 104. The ohmic contact layer 302 includes one or more of metal Ni, an alloy or stack of metal Ti and metal Ni, an alloy or stack of metal Ni and metal Pt, metal Co, an alloy or stack of metal Ti and metal Al, and a stack of metal Ti and TiN.

[0063] Optionally, based on the above technical solution, Figure 2-Figure 4 As shown, the semiconductor body 100 also includes a second region 107 , which surrounds the bottom of the second trench T4 and the third sidewall T03 ; the conductivity type of the second region 107 is the same as that of the well region 103 , and the doping concentration of the second region 107 is greater than the doping concentration of the well region 103 .

[0064] Specifically, the conductivity type of the second region 107 is the same as the conductivity type of the well region 103, that is, the conductivity type of the second region 107 is opposite to the conductivity type of the drift region between the second region 107 and the second surface 102, so that the second region 107 and the drift region between the second region 107 and the second surface 102 constitute a depletion layer, which can further reduce the peak electric field at the bottom of the trench-type gate structure 200.

[0065] In the embodiment of the present invention, the MOSFET semiconductor device includes an N-type MOSFET semiconductor device or a P-type MOSFET semiconductor device. Taking the N-type MOSFET semiconductor device as an example, the semiconductor body 100 is an N-type semiconductor body, the first region 104 is an N+ doped region, the second region 107 is a P+ doped region, and the well region 103 is a P-well region.

[0066] Optionally, based on the above technical solution, Figure 2-Figure 4 As shown, the second region 107 includes a first portion and a second portion, the first portion is located at the third sidewall T03, and the second portion is located at the bottom of the second trench T4.

[0067] Specifically, the second region 107 surrounds the bottom of the second trench T4 and the third sidewall T03, so that the second region 107 includes a portion of the second region formed on the third sidewall T03 by the inclined ion implantation process and a portion of the second region 107 formed on the bottom of the second trench T4 by the vertical ion implantation process. The above semiconductor device can complete the preparation process of the second region 107 only by the vertical ion implantation process and the single-side inclined ion implantation process.

[0068] Optionally, based on the above technical solution, Figure 5-Figure 7 As shown, Figure 5 yes Figure 2 A schematic diagram of the structure of the second trench including two sub-trench in the corresponding semiconductor device, Figure 6 yes Figure 3 A schematic diagram of the structure of the second trench including two sub-trench in the corresponding semiconductor device, Figure 7 yes Figure 4 A schematic structural diagram of a corresponding semiconductor device in which the second trench includes two sub-trenches, the second trench T4 includes at least two sub-trenches T5; the sub-trench T5 includes a fifth side wall T07 and a sixth side wall T08 that are relatively arranged; the sixth side wall T08 of the sub-trench T5 coincides with the vertical projection of the second side wall T02 on the first surface 101; in the direction from the first surface 101 to the second surface 102, a plurality of sub-trenches T5 are arranged adjacent to each other, and the spacing between the two side walls of the sub-trench T5 decreases successively.

[0069] For example, Figure 5-Figure 7 In the embodiment, the second trench T4 includes two sub-trench T5. The depths of the sub-trench T5 may be the same or different. The depth of a single sub-trench T5 is greater than or equal to 0.3 micrometers and less than or equal to 10 micrometers.

[0070] Specifically, in the direction from the first surface 101 to the second surface 102 (i.e. Figure 5-Figure 7 In the direction opposite to the Y direction), the spacing between the two side walls of the sub-groove T5 is successively reduced. Compared with the technical solution in which the spacing between the two side walls of the sub-groove T5 is equal, the area of ​​the semiconductor body 100 occupied by the voltage-resistant layer 106 is reduced, and the specific on-resistance of the semiconductor device is reduced. In addition, the second trench T4 includes at least two sub-grooves T5, which reduces the etching depth of each etching of the second trench T4, thereby reducing the etching difficulty and improving the etching accuracy. Especially for the semiconductor body 100 that is a silicon carbide semiconductor body or a gallium nitride semiconductor body, its hardness is relatively large, and the solution in which the second trench T4 includes at least two sub-grooves T5 has a more significant effect on improving the etching accuracy of the second trench T4.

[0071] Optionally, based on the above technical solution, Figure 2-Figure 4 as well as Figure 5-Figure 7As shown, the vertical projection of the second region 107 on the first surface 101 is within the vertical projection of the first trench T3 on the first surface 101 .

[0072] Specifically, compared with the solution in which the vertical projection of the first trench T3 on the first surface 101 is within the vertical projection of the second region 107 on the first surface 101, the above technical solution reduces the area of ​​the semiconductor body 100 occupied by the second region 107, thereby reducing the specific on-resistance of the semiconductor device. The direction perpendicular to the second surface 102 pointing to the first surface 101 is the X direction in the figure.

[0073] Optionally, based on the above technical solution, the semiconductor body 100 includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0074] Specifically, the semiconductor body 100 includes a silicon carbide semiconductor body, and the MOSFET semiconductor device is a silicon carbide MOSFET semiconductor device. The semiconductor body 100 includes a gallium nitride semiconductor body, and the MOSFET semiconductor device is a gallium nitride MOSFET semiconductor device. Silicon carbide MOSFET semiconductor devices or gallium nitride MOSFET semiconductor devices have the advantages of high withstand voltage, low on-resistance and high frequency, which can further improve the performance of semiconductor devices.

[0075] The embodiment of the present invention also provides a method for manufacturing a semiconductor device. Figure 8 As shown, Figure 8 A flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention is provided. The method for manufacturing a semiconductor device comprises the following steps:

[0076] S110, providing a semiconductor body, including a first surface and a second surface arranged opposite to each other; the semiconductor body also includes a well region and a first region; the first region is arranged on the first surface, and the well region is arranged on a side of the first region away from the first surface.

[0077] like Fig. 9 As shown, a semiconductor body 100 is provided, and the semiconductor body 100 includes a silicon carbide semiconductor body or a gallium nitride semiconductor body. The semiconductor body 100 includes a first surface 101 and a second surface 102 that are oppositely arranged; the semiconductor body 100 also includes a well region 103 and a first region 104; the first region 104 is arranged on the first surface 101, and the well region 103 is arranged on a side of the first region 104 away from the first surface 101.

[0078] Exemplarily, the semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of the present invention, the semiconductor body 100 may also include a substrate 10 and a semiconductor layer formed by other processes. Among them, the epitaxial layer 20 is a semiconductor layer formed by a single epitaxial process on the basis of the substrate 10, and the epitaxial process includes chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD) and atomic layer epitaxy (ALE) and other processes.

[0079] Optionally, the MOSFET semiconductor device may further include a third region, the conductivity type of the third region is the same as the conductivity type of the well region 103, the doping concentration of the third region is greater than the doping concentration of the well region 103, and the third region is electrically connected to the source 305 to form a good ohmic contact with the source 305. The third region is located on a side of the well region 103 away from the second surface 102.

[0080] S120, forming a first groove on the first surface, wherein the first groove includes a first sidewall and a second sidewall that are oppositely disposed.

[0081] The process of forming the first trench T3 on the first surface 101 is as follows:

[0082] like Fig.10 As shown, a first photoresist layer 500 is formed on the first surface 101. Fig.11 As shown, a first trench T3 including a first sidewall T01 and a second sidewall T02 oppositely disposed is formed on the first surface 101 by photolithography and etching processes.

[0083] S130. Form a second groove in the first groove, wherein the second groove is connected to the first groove and is located between the first groove and the second surface; the second groove includes a third sidewall and a fourth sidewall that are oppositely arranged; and the direction from the first sidewall to the second sidewall is parallel to the direction from the third sidewall to the fourth sidewall.

[0084] The process of forming the second trench T4 in the first trench T3 is as follows:

[0085] like Fig.12 As shown, a second photoresist 501 is formed inside the first trench T3. Then, a second trench T4 is formed in the first trench T3 by photolithography and etching processes. The second trench T4 includes a third sidewall T03 and a fourth sidewall T04 that are arranged opposite to each other; the direction of the first sidewall T01 pointing to the second sidewall T02 is parallel to the direction of the third sidewall T03 pointing to the fourth sidewall T04; and the well region 103 in contact with the first sidewall T01 serves as a channel of the semiconductor device.

[0086] S140 , forming a voltage-resistant layer in the second trench and the first trench.

[0087] like Figure 13-Figure 15 As shown, after removing the second photoresist 501 inside the first trench T3, a voltage-resistant layer 106 is formed in the second trench T4 and the first trench T3 by oxidation or deposition. Fig.13 As shown, the voltage-resistant layer 106 is silicon dioxide. Fig.14 As shown, the voltage-resistant layer 106 is silicon nitride. Fig.15 As shown, the voltage-resistant layer 106 is polysilicon with weak conductivity.

[0088] S150, removing part of the voltage-resistant layer in the first trench, so that the voltage-resistant layer is located in the second trench, and the voltage-resistant layer covers the surface where the second trench and the first trench are connected and the second side wall.

[0089] The process of removing part of the voltage-resistant layer 106 in the first trench T3 is as follows:

[0090] like Fig.16 As shown, the voltage-resistant layer 106 and the insulating layer 201 of the gate structure 200 formed subsequently are made of the same material. For example, when the voltage-resistant layer 106 and the insulating layer 201 are made of silicon dioxide, a third photoresist 502 is first formed on the first surface 101. Then, a portion of the voltage-resistant layer 106 in the first trench T3 is removed by photolithography and etching processes, so that the voltage-resistant layer 106 is located in the second trench T4, and the voltage-resistant layer 106 covers the surface T05 where the second trench T4 and the first trench T3 meet and the second sidewall T02. The vertical projection of the surface T05 where the second trench T4 and the first trench T3 meet on the first surface 101 coincides with the vertical projection of the second trench T4 on the first surface 101. It should be noted that when the material of the insulating layer 201 is the same as that of the voltage-resistant layer 106 , when part of the voltage-resistant layer 106 in the first trench T3 is removed, the voltage-resistant layer 106 at the bottom T06 of the first trench T3 can be retained and reused as the insulating layer 201 of the gate structure 200 formed subsequently.

[0091] like Fig.17 and Fig.18 As shown, the voltage-resistant layer 106 and the insulating layer 201 of the gate structure 200 formed subsequently are made of different materials. First, a layer of third photoresist 502 is formed on the first surface 101. Then, a portion of the voltage-resistant layer 106 in the first trench T3 is removed by photolithography and etching processes, so that the voltage-resistant layer 106 is located in the second trench T4, and the voltage-resistant layer 106 covers the surface T05 where the second trench T4 and the first trench T3 meet and the second sidewall T02; the vertical projection of the surface T05 where the second trench T4 and the first trench T3 meet on the first surface 101 coincides with the vertical projection of the second trench T4 on the first surface 101. Wherein, Fig.17 The medium voltage-resistant layer 106 is silicon nitride. Fig.18 The medium voltage-resistant layer 106 is made of polysilicon.

[0092] S160. Form a gate structure in the first trench, the gate structure including an insulating layer and a gate electrode, the insulating layer is used to insulate the gate electrode and the semiconductor body, the insulation resistance of the voltage-resistant layer is greater than the insulation resistance of the insulating layer, and the voltage-resistant layer is used to reduce the peak electric field at the bottom of the gate structure.

[0093] like Figure 2-Figure 4 As shown, a gate structure 200 is formed in the first trench T3. The gate structure 200 includes an insulating layer 201 and a gate electrode 202. The insulating layer 201 is used to insulate the gate electrode 202 and the semiconductor body 100. The insulation resistance of the voltage-resistant layer 106 is greater than the insulation resistance of the insulating layer 201. The voltage-resistant layer 106 is used to reduce the peak electric field at the bottom of the gate structure 200.

[0094] S170 , forming a source on the first surface.

[0095] like Figure 2-Figure 4 As shown, a source electrode 305 is formed on the first surface 101 , wherein the ohmic contact layer 302 enables the source electrode 305 to form a good ohmic contact with the first region 104 and the third region 105 .

[0096] S180, forming a drain on the second surface.

[0097] like Figure 2-Figure 4 As shown, a drain electrode 400 is formed on the second surface 102. The drain electrode 400 may include a stack of metal Ti, metal Ni, and metal Ag.

[0098] In the MOSFET semiconductor device manufactured by the embodiment of the present invention, the voltage-resistant layer 106 is located in the second trench T4, and the voltage-resistant layer 106 covers the surface T05 where the second trench T4 and the first trench T3 meet and the second side wall T02, that is, a large part of the bottom of the gate structure 200 is embedded in the voltage-resistant layer 106. Since the insulation resistance of the voltage-resistant layer 106 is greater than the insulation resistance of the insulating layer 201, the maximum electric field is transferred to the voltage-resistant layer 106 at the bottom of the gate structure 200, thereby reducing the peak electric field at the bottom of the gate structure 200 and avoiding the gate structure 200 from being broken down. In addition, in the above-mentioned MOSFET semiconductor device, it is not necessary to set the source 305 as a trench-type source structure to occupy the area of ​​the semiconductor body 100 to reduce the peak electric field at the bottom of the trench-type gate structure 200, thereby reducing the specific on-resistance of the semiconductor device and improving the electrical performance of the semiconductor device. Among them, since the insulation resistance of the voltage-resistant layer 106 is greater than the insulation resistance of the insulating layer 201 and covers the second side wall T02 of the first trench T3, in the present semiconductor device, the well region 103 in contact with the first side wall T01 serves as a channel of the semiconductor device, while the well region 103 in contact with the second side wall T02 does not serve as a channel of the semiconductor device, thereby enhancing the pressure-bearing capacity of the gate structure 200 located at the second side wall T02 and reducing the risk of the gate structure 200 being broken down.

[0099] Optionally, based on the above technical solution, S130 forming a second groove in the first groove includes:

[0100] A second trench is formed in the first trench, the second trench having a vertical projection area on the first surface smaller than the vertical projection area of ​​the first trench on the first surface.

[0101] like Fig.12 As shown, the vertical projection area of ​​the second trench T4 on the first surface 101 is smaller than the vertical projection area of ​​the first trench T3 on the first surface 101, and the voltage-resistant layer 106 covers the surface T05 where the second trench T4 and the first trench T3 are connected. Compared with the solution in which the vertical projection area of ​​the second trench T4 on the first surface 101 is greater than or equal to the vertical projection area of ​​the first trench T3 on the first surface 101, the area of ​​the semiconductor body 100 occupied by the voltage-resistant layer 106 is reduced, thereby reducing the specific on-resistance of the semiconductor device.

[0102] Optionally, based on the above technical solution, S130 forming a second groove in the first groove includes:

[0103] A second groove is formed in the first trench, where the fourth side wall and the second side wall overlap in vertical projection on the first surface.

[0104] like Fig.12As shown, a second trench T4 is formed in the first trench T3 , where the fourth side wall T04 coincides with the vertical projection of the second side wall T02 on the first surface 101 .

[0105] Specifically, the vertical projections of the second side wall T02 and the fourth side wall T04 on the first surface 101 overlap, and the vertical projection area of ​​the second trench T4 on the first surface 101 can be controlled by controlling the position of the third side wall T03, so that the vertical projection area of ​​the second trench T4 on the first surface 101 is smaller than the vertical projection area of ​​the first trench T3 on the first surface 101.

[0106] Optionally, based on the above technical solution, Fig.19 As shown, Fig.19 yes Figure 8 The schematic diagram of the process included in S160, S160 forms a gate structure in the first trench including:

[0107] S1601 , forming an insulating layer at least on the bottom and first sidewall of the first trench.

[0108] Exemplarily, the insulating layer 201 includes a high-k dielectric layer such as silicon dioxide, aluminum oxide, hafnium oxide, etc. When the insulating layer 201 is silicon dioxide, it can be obtained by performing an oxidation process on the semiconductor body 100. The voltage-resistant layer 106 includes at least one of silicon oxide, silicon nitride and polysilicon.

[0109] The example in which the insulating layer 201 includes silicon dioxide is used for the following description. Figure 2 As shown, the insulating layer 201 includes silicon dioxide, and the voltage-resistant layer 106 includes silicon dioxide. Figure 3 As shown, the insulating layer 201 includes silicon dioxide, and the voltage-resistant layer 106 includes silicon nitride. Figure 4 As shown, the insulating layer 201 includes silicon dioxide, and the voltage-resistant layer 106 includes polysilicon.

[0110] like Figure 2 and Figure 3 As shown, when the material of the voltage-resistant layer 106 and the material of the insulating layer 201 are the same, or are both insulating materials, the insulating layer 201 is located at the bottom T06 and the first sidewall T01 of the first trench T3 .

[0111] Optionally, when the voltage-resistant layer 106 is conductive, S1601 forms an insulating layer at least on the bottom and the first sidewall of the first trench, including:

[0112] An insulating layer is formed on the first side wall, the second bottom, and a surface of the voltage-resistant layer away from the semiconductor body.

[0113] like Figure 4As shown, when the material of the voltage-resistant layer 106 is conductive, such as polysilicon with weak conductivity, the insulating layer 201 is located on the first side wall T01, the bottom T06 of the first trench T3, and on the surface of the voltage-resistant layer 106 away from the semiconductor body 100. The insulating layer 201 is located on the surface of the voltage-resistant layer 106 away from the semiconductor body 100 and is used to insulate the gate electrode 202 and the voltage-resistant layer 106.

[0114] S1602. Form a gate electrode on a side of the insulating layer and the voltage-resistant layer in the first trench away from the semiconductor body, wherein, in a direction perpendicular to the second surface pointing to the first surface, a distance between the first side wall and the gate electrode is smaller than a distance between the gate electrode and the second side wall.

[0115] like Figure 2-Figure 4 As shown, a gate electrode 202 is formed on a side of the insulating layer 201 and the voltage-resistant layer 106 in the first trench T3 away from the semiconductor body 100. The gate electrode 202 can be made of polysilicon material.

[0116] Specifically, the insulating layer 201 is at least located at the bottom T06 and the first sidewall T01 of the first trench T3 and is used to insulate the gate electrode 202 and the semiconductor body 100 . The gate electrode 202 is used to access a gate electrical signal.

[0117] In the direction perpendicular to the second surface 102 pointing to the first surface 101, the spacing between the first side wall T01 and the gate electrode 202 is smaller than the spacing between the gate electrode 202 and the second side wall T02, which is used to increase the thickness of the voltage-resistant layer 106 located on the second side wall T02, thereby increasing its insulation resistance, so as to achieve the function of the voltage-resistant layer 106 for reducing the peak electric field at the bottom of the gate structure 200, and enhance the pressure-bearing capacity of the gate structure 200 located at the first side wall T01. In the embodiment of the present invention, the direction from the second surface 102 to the first surface 101 is the Y direction in the figure.

[0118] Optionally, based on the above technical solution, Fig. 20 As shown, Fig. 20 yes Figure 8 In the process view before S140, S140 further includes before forming the voltage-resistant layer in the second trench and the first trench:

[0119] S1401. Form a second region at the bottom of the second trench and on the third sidewall, wherein the conductivity type of the second region is the same as the conductivity type of the well region, and the doping concentration of the second region is greater than the doping concentration of the well region.

[0120] The process of forming the second region 107 at the bottom of the second trench T4 and the third sidewall T03 is as follows:

[0121] like Fig.21As shown, the second photoresist 501 is used as a mask, and a suitable ion implantation angle is selected to form a second region 107 at the bottom of the second trench T4 and the third sidewall T03.

[0122] like Fig. 22 As shown, after the ion implantation process is completed, the second photoresist 501 is removed.

[0123] Specifically, the conductivity type of the second region 107 is the same as the conductivity type of the well region 103, that is, the conductivity type of the second region 107 is opposite to the conductivity type of the drift region between the second region 107 and the second surface 102, so that the second region 107 and the drift region between the second region 107 and the second surface 102 form a depletion layer, which can further reduce the peak electric field at the bottom of the trench-type gate structure 200.

[0124] The MOSFET semiconductor device includes an N-type MOSFET semiconductor device or a P-type MOSFET semiconductor device. Taking the N-type MOSFET semiconductor device as an example, the semiconductor body 100 is an N-type semiconductor body, the first region 104 is an N+ doped region, the second region 107 is a P+ doped region, and the well region 103 is a P-well region.

[0125] Optionally, based on the above technical solution, Fig.23 As shown, Fig.23 yes Fig. 20 The process diagram of S1401 includes: S1401 forms a second region at the bottom of the second trench and the third sidewall, including:

[0126] S14011. Form a first portion of the second region on the third side wall through an inclined ion implantation process.

[0127] like Fig.21 As shown, a first portion of the second region 107 is formed on the third sidewall T03 by an inclined ion implantation process.

[0128] S14012. Form a second part of the second region at the bottom of the second trench by a vertical ion implantation process, wherein the conductivity type of the second region is the same as the conductivity type of the well region, and the doping concentration of the second region is greater than the doping concentration of the well region.

[0129] like Fig.21 As shown, a second portion of the second region 107 is formed at the bottom of the second trench T4 by a vertical ion implantation process, wherein the conductivity type of the second region 107 is the same as that of the well region 103 , and the doping concentration of the second region 107 is greater than that of the well region 103 .

[0130] Specifically, the second region 107 surrounds the bottom of the second trench T4 and the third sidewall T03, so that the second region 107 includes a portion of the second region formed on the third sidewall T03 by the inclined ion implantation process and a portion of the second region 107 formed on the bottom of the second trench T4 by the vertical ion implantation process. The above semiconductor device can complete the preparation process of the second region 107 only by the vertical ion implantation process and the single-side inclined ion implantation process.

[0131] Optionally, based on the above technical solution, S130 forming a second groove in the first groove includes:

[0132] At least two sub-grooves are formed in the first groove, wherein the sub-grooves include a fifth sidewall and a sixth sidewall arranged opposite to each other; the sixth sidewall of the sub-groove coincides with the vertical projection of the second sidewall on the first surface; in the direction from the first surface to the second surface, the multiple sub-grooves are arranged adjacent to each other, and the spacing between the two sidewalls of the sub-grooves decreases successively.

[0133] The process of forming at least two sub-trench T5 at the bottom of the first trench T3 is as follows:

[0134] like Fig.24 and Fig.25 As shown, a second photoresist 501 is formed inside the first trench T3. Then, two sub-trench T5 are formed at the bottom of the first trench T3 by photolithography and etching processes. The sub-trench T5 includes a fifth sidewall T07 and a sixth sidewall T08 that are oppositely disposed; the sixth sidewall T08 of the sub-trench T5 overlaps with the vertical projection of the second sidewall T02 on the first surface 101.

[0135] In the direction from the first surface 101 to the second surface 102, a plurality of sub-grooves T5 are arranged adjacent to each other, and the distance between the two side walls of the sub-grooves T5 decreases successively. Fig.24 and Fig.25 The scheme of forming two sub-trench T5 at the partial bottom of the first trench T3 is shown. The fifth sidewalls T07 of at least the two sub-trench T5 constitute the third sidewall T03 of the second trench T4.

[0136] Specifically, in the direction from the first surface 101 to the second surface 102, the spacing between the two side walls of the sub-groove T5 is reduced successively, and compared with the technical solution in which the spacing between the two side walls of the sub-groove T5 is equal, the area of ​​the semiconductor body 100 occupied by the voltage-resistant layer 106 is reduced, and the specific on-resistance of the semiconductor device is reduced. Moreover, the second trench T4 includes at least two sub-grooves T5, which reduces the etching depth of each etching of the second trench T4, thereby reducing the etching difficulty and improving the etching accuracy. Especially for the semiconductor body 100 that is a silicon carbide semiconductor body or a gallium nitride semiconductor body, which has a relatively large hardness, the solution in which the second trench T4 includes at least two sub-grooves T5 has a more significant effect on improving the etching accuracy of the second trench T4.

[0137] like Fig.26 As shown, the second photoresist 501 is removed.

[0138] Alternatively, if Fig.25 As shown, before the voltage-resistant layer 106 is formed in the second trench T4 and the first trench T3, it also includes: using the second photoresist 501 as a mask, forming the first part of the second region 107 on the fifth side wall T07 by an inclined ion implantation process, and forming the second part of the second region 107 at the bottom of the sub-trench T5 by a vertical ion implantation process, wherein the conductivity type of the second region 107 is the same as the conductivity type of the well region 103, and the doping concentration of the second region 107 is greater than the doping concentration of the well region 103.

[0139] Specifically, the second region 107 surrounds the bottom of the second trench T4 and the third sidewall T03, so that the second region 107 includes a portion of the second region 107 formed on the fifth sidewall T07 by the inclined ion implantation process and a portion of the second region 107 formed on the bottom of the sub-trench T5 by the vertical ion implantation process. The above semiconductor device can complete the preparation process of the second region 107 only by the vertical ion implantation process and the single-side inclined ion implantation process.

[0140] The embodiment of the present invention provides a power module, including a substrate and at least one semiconductor device described in any embodiment of the present invention, wherein the substrate is used to carry the semiconductor device. Therefore, the beneficial effects of the power module including the semiconductor device described in any embodiment of the present invention are not described in detail here.

[0141] An embodiment of the present invention provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and at least one semiconductor device as described in any of the embodiments of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0142] Therefore, the beneficial effects of the power conversion circuit including any semiconductor device described in the embodiments of the present invention will not be repeated here.

[0143] The embodiment of the present invention further provides a vehicle, comprising a load and any power conversion circuit as in the embodiment of the present invention, the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power, and then input it into the load. Therefore, the beneficial effects of the power conversion circuit described in any embodiment of the present invention are not repeated here.

[0144] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0145] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor body, comprising a first surface and a second surface arranged opposite to each other; the semiconductor body further comprising a well region and a first area; the first area is arranged on the first surface, and the well region is arranged on a side of the first area away from the first surface; the first surface is further provided with a first trench and a second trench, the first trench is arranged on the first surface, the second trench is connected to the first trench, and the second trench is located between the first trench and the second surface; the conductivity type of the first area is the same as and opposite to the conductivity type of the well region; the first trench comprises a first sidewall and a second sidewall arranged opposite to each other; the second trench comprises a third sidewall and a fourth sidewall arranged opposite to each other; the direction of the first sidewall pointing to the second sidewall is parallel to the direction of the third sidewall pointing to the fourth sidewall; A voltage-resistant layer, located in the second groove, and the voltage-resistant layer covers a surface where the second groove and the first groove meet and the second side wall; A gate structure is located in the first trench; the gate structure includes an insulating layer and a gate electrode, the insulating layer is used to insulate and space the gate electrode and the semiconductor body, the insulation resistance of the voltage-resistant layer is greater than the insulation resistance of the insulating layer, and the voltage-resistant layer is used to reduce the peak electric field at the bottom of the gate structure; A source electrode, located on the first surface; The drain is located on the second surface.

2. The semiconductor device according to claim 1, wherein: A vertical projection area of ​​the second groove on the first surface is smaller than a vertical projection area of ​​the first groove on the first surface.

3. The semiconductor device according to claim 2, characterized in that The vertical projections of the second side wall and the fourth side wall on the first surface overlap.

4. The semiconductor device according to claim 1, wherein: The insulating layer is at least located at the bottom of the first trench and the first sidewall; The gate electrode is located on a side of the insulating layer and the voltage-resistant layer in the first trench away from the semiconductor body, wherein in a direction perpendicular to the second surface pointing to the first surface, a distance between the first side wall and the gate electrode is smaller than a distance between the gate electrode and the second side wall.

5. The semiconductor device according to claim 4, characterized in that When the voltage-resistant layer is conductive, the insulating layer is located on the first side wall, the bottom of the first trench, and the surface of the voltage-resistant layer away from the semiconductor body.

6. The semiconductor device according to any one of claims 1 to 3, characterized in that: The semiconductor body further includes a second region, the second region surrounding a bottom and a third sidewall of the second trench; The conductivity type of the second region is the same as that of the well region, and the doping concentration of the second region is greater than the doping concentration of the well region.

7. The semiconductor device according to any one of claims 1 to 3, characterized in that: The second groove includes at least two sub-grooves; The sub-groove comprises a fifth side wall and a sixth side wall which are arranged opposite to each other; The vertical projections of the sixth sidewall of the sub-groove and the second sidewall on the first surface overlap; In the direction from the first surface to the second surface, a plurality of the sub-grooves are arranged adjacent to each other, and the distance between the two side walls of the sub-grooves decreases successively.

8. The semiconductor device according to claim 6, characterized in that A vertical projection of the second region on the first surface is within a vertical projection of the first groove on the first surface.

9. The semiconductor device according to claim 1, wherein: The material of the voltage-resistant layer includes at least one of silicon oxide, silicon nitride and polysilicon.

10. The semiconductor device according to claim 1, wherein: The semiconductor body includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

11. A method for manufacturing a semiconductor device, characterized in that: include: A semiconductor body is provided, comprising a first surface and a second surface arranged opposite to each other; the semiconductor body further comprises a well region and a first area; the first area is arranged on the first surface, and the well region is arranged on a side of the first area away from the first surface; forming a first groove on the first surface, wherein the first groove comprises a first sidewall and a second sidewall disposed opposite to each other; A second groove is formed in the first groove, wherein the second groove is connected to the first groove, and the second groove is located between the first groove and the second surface; the second groove includes a third sidewall and a fourth sidewall that are oppositely arranged; and the direction from the first sidewall to the second sidewall is parallel to the direction from the third sidewall to the fourth sidewall; forming a voltage-resistant layer in the second groove and the first groove; Removing part of the voltage-resistant layer in the first groove, so that the voltage-resistant layer is located in the second groove, and the voltage-resistant layer covers the surface where the second groove and the first groove meet and the second side wall; forming a gate structure in the first trench, the gate structure comprising an insulating layer and a gate electrode, the insulating layer being used for insulating and spacing the gate electrode and the semiconductor body, the insulation resistance of the voltage-resistant layer being greater than the insulation resistance of the insulating layer, and the voltage-resistant layer being used for reducing a peak electric field at the bottom of the gate structure; forming a source electrode on the first surface; A drain electrode is formed on the second surface.

12. The method for manufacturing a semiconductor device according to claim 11, wherein: Forming a second trench in the first trench comprises: A second groove having a vertical projection area on the first surface smaller than a vertical projection area of ​​the first groove on the first surface is formed in the first groove.

13. The method for manufacturing a semiconductor device according to claim 12, wherein: Forming a second trench in the first trench comprises: A second trench is formed in the first trench, wherein the fourth sidewall and the vertical projection of the second sidewall on the first surface overlap.

14. The method for manufacturing a semiconductor device according to claim 11, wherein: Forming a gate structure in the first trench includes: forming an insulating layer at least on the bottom of the first trench and the first sidewall; A gate electrode is formed on a side of the insulating layer and the voltage-resistant layer in the first trench away from the semiconductor body, wherein in a direction perpendicular to the second surface pointing to the first surface, a distance between the first side wall and the gate electrode is smaller than a distance between the gate electrode and the second side wall.

15. The method for manufacturing a semiconductor device according to claim 14, wherein: When the voltage-resistant layer is conductive, forming an insulating layer at least on the bottom and the first sidewall of the first trench comprises: The insulating layer is formed on the first side wall, the bottom of the first trench, and the surface of the voltage-resistant layer away from the semiconductor body.

16. The method for manufacturing a semiconductor device according to any one of claims 11 to 13, characterized in that: Before forming the voltage-resistant layer in the second trench and the first trench, the method further includes: A second region is formed at the bottom of the second trench and the third sidewall, wherein the conductivity type of the second region is the same as the conductivity type of the well region, and the doping concentration of the second region is greater than the doping concentration of the well region.

17. The method for manufacturing a semiconductor device according to claim 16, wherein: Forming a second region at the bottom of the second trench and the third sidewall includes: forming a first portion of the second region on the third sidewall by an inclined ion implantation process; A second portion of the second region is formed at the bottom of the second trench by a vertical ion implantation process.

18. The method for manufacturing a semiconductor device according to any one of claims 11 to 13, characterized in that: Forming a second trench in the first trench comprises: At least two sub-grooves are formed in the first groove, wherein the sub-grooves include a fifth sidewall and a sixth sidewall arranged opposite to each other; the sixth sidewall of the sub-groove and the vertical projection of the second sidewall on the first surface coincide with each other; in the direction from the first surface to the second surface, the plurality of sub-grooves are arranged adjacent to each other, and the spacing between the two sidewalls of the sub-grooves decreases successively.

19. A power module, characterized in that: The invention comprises a substrate and at least one semiconductor device according to any one of claims 1 to 10, wherein the substrate is used for carrying the semiconductor device.

20. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit comprises a circuit board and at least one semiconductor device according to any one of claims 1 to 10, wherein the semiconductor device is electrically connected to the circuit board.

21. A vehicle, characterized in that: It includes a load and a power conversion circuit as described in claim 20, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

Images