Semiconductor structure and preparation method thereof

Abstract

The embodiment of the invention relates to a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a substrate; the semiconductor column is located on the surface of the substrate, the semiconductor column is provided with a channel region and a first side face, and at least part of the first side face corresponding to the channel region is recessed towards the center of the semiconductor column; and the word line at least covers the first side surface corresponding to the channel region. The semiconductor structure provided by the embodiment of the invention at least can improve the performance of the semiconductor structure.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] Memory is a common semiconductor structure. As the size of semiconductor structures continues to shrink, more memory can be incorporated on the chip, which helps increase the capacity of the product. There are many tiny conductive structural units inside the semiconductor structure, such as channels and source and drain electrodes. Among them, the channel is used to form a conductive channel between the source and the drain. The semiconductor structure also has a word line, which is in electrical contact with the channel region and is used to provide a control voltage sufficient to turn on the channel to control the conduction between the source and the drain. The control ability of the word line over the channel has an important influence on the performance of the semiconductor structure. The stronger the control ability of the word line over the channel, the faster the response rate of the transistor in the semiconductor structure and the better the performance of the semiconductor structure.

[0003] However, the performance of current semiconductor structures needs to be further improved. Summary of the invention

[0004] The embodiments of the present disclosure provide a semiconductor structure and a method for preparing the same, which are at least beneficial to improving the performance of the semiconductor structure.

[0005] An embodiment of the present disclosure provides a semiconductor structure, including: a substrate; a semiconductor column located on the surface of the substrate, the semiconductor column having a channel region, the semiconductor column having a first side surface, at least a portion of the first side surface corresponding to the channel region being recessed toward the center of the semiconductor column; and a word line, the word line at least covering the first side surface corresponding to the channel region.

[0006] In some embodiments, the semiconductor column also includes: doped regions located on both sides of the channel region, the arrangement direction of the channel region and the doped regions is perpendicular to the substrate surface, a portion of the first side surface corresponding to the channel region is recessed toward the center of the semiconductor column to form a first groove, the first groove extends in a direction away from the substrate surface, and the first groove spans the doped region and the channel region.

[0007] In some embodiments, a portion of the first side surface corresponding to the channel region is recessed toward the center of the semiconductor column to form a first groove, and there are multiple first grooves, which are arranged at intervals.

[0008] In some embodiments, the semiconductor column has a second side surface opposite to the first side surface, a portion of the second side surface corresponding to the channel region is recessed toward a center of the semiconductor column, and the word line also covers the second side surface corresponding to the channel region.

[0009] In some embodiments, the number of semiconductor pillars is multiple, including: multiple rows of semiconductor pillars arranged at intervals along a first direction, wherein each row of semiconductor pillars includes multiple semiconductor pillars arranged at intervals along a second direction, the number of word lines is multiple, each word line extends along the second direction, and one word line covers the first side surface corresponding to the channel region of each semiconductor pillar in a row of the semiconductor pillars.

[0010] In some embodiments, a word line surrounds an entire side of the semiconductor pillar of the channel region.

[0011] In some embodiments, there are multiple semiconductor columns, and the multiple semiconductor columns include: first sub-semiconductor columns and second sub-semiconductor columns are alternately arranged along a first direction, wherein the first side surface of the first sub-semiconductor column and the first side surface of the second sub-semiconductor column are arranged opposite to each other along the first direction.

[0012] In some embodiments, the word line covers a first side surface of a channel region of the first semiconductor sub-column and a first side surface of a channel region of the second semiconductor sub-column which are arranged opposite to each other.

[0013] In some embodiments, the first sub-semiconductor pillar and the second sub-semiconductor pillar each include a second side surface opposite to the first side surface, and the second side surface is exposed outside the word line.

[0014] In some embodiments, the first sub-semiconductor column and the second sub-semiconductor column both include: a third side surface connected to the first side surface, and a fourth side surface arranged opposite to the third side surface, and the word line also covers at least a portion of the third side surface and at least a portion of the fourth side surface of the first sub-semiconductor column, and covers at least a portion of the third side surface and at least a portion of the fourth side surface of the second sub-semiconductor column.

[0015] In some embodiments, the semiconductor structure includes: multiple rows of first sub-semiconductor columns arranged at intervals along the first direction, each row of the first sub-semiconductor columns includes multiple first sub-semiconductor columns arranged at intervals along the second direction; multiple rows of second sub-semiconductor columns arranged at intervals along the second direction, each row of the second sub-semiconductor columns includes multiple second sub-semiconductor columns arranged at intervals along the second direction, each row of the first sub-semiconductor columns and each row of the second sub-semiconductors are alternately arranged along the first direction; there are multiple word lines, and each word line covers the first side surface corresponding to the channel region in a row of the first sub-semiconductor columns and a row of the second sub-semiconductors that are alternately arranged.

[0016] In some embodiments, the method further includes: a gate dielectric layer, wherein the gate dielectric layer is located between the word line and the semiconductor column.

[0017] In some embodiments, there are multiple semiconductor pillars, and the multiple semiconductor pillars include: first sub-semiconductor pillars and second sub-semiconductor pillars are alternately arranged along a first direction, a word line covers a first side surface of a channel region of a first sub-semiconductor pillar and a first side surface of a channel region of a second sub-semiconductor pillar that are relatively arranged, and the gate dielectric layer covers an entire side surface of the channel region of the first sub-semiconductor pillar corresponding to a word line and an entire side surface of the channel region of the second sub-semiconductor pillar corresponding to another adjacent word line.

[0018] Correspondingly, an embodiment of the present disclosure also provides a method for preparing a semiconductor structure, comprising: providing a substrate; forming a semiconductor column on the surface of the substrate, the semiconductor column having a channel region, the semiconductor column having a first side surface, at least a portion of the first side surface corresponding to the channel region being recessed toward the center of the semiconductor column; forming a word line, the word line at least covering the first side surface corresponding to the channel region.

[0019] In some embodiments, the method for forming the semiconductor column includes: providing an initial substrate; etching a portion of the initial substrate to form a semiconductor layer arranged at intervals along a second direction, and the remaining portion of the initial substrate serves as the substrate; forming a first graphic layer on a portion of the surface of the semiconductor layer, the first graphic layer being used to define the cross-sectional shape of the semiconductor column parallel to the surface of the substrate; etching the semiconductor layer not covered by the first graphic layer, and the remaining portion of the semiconductor layer forms the semiconductor column.

[0020] In some embodiments, the plurality of semiconductor pillars include: first sub-semiconductor pillars and second sub-semiconductor pillars alternately arranged along a first direction, wherein the first side surface of the first sub-semiconductor pillar and the first side surface of the second sub-semiconductor pillar are arranged opposite to each other along the first direction, and a word line covers the first side surface of the channel region of the first sub-semiconductor pillar and the first side surface of the channel region of the second sub-semiconductor pillar that are arranged opposite to each other. The method for forming the semiconductor pillars includes: forming a first graphic layer on a portion of the surface of the semiconductor layer, the first graphic layer includes a first sub-graphic layer and a second sub-graphic layer alternately arranged along the first direction, the first sub-graphic layer includes a first recessed side having a first recess, the second sub-graphic layer includes a second recessed side having a second recess, and the first recessed side and the second recessed side are arranged opposite to each other along the first direction; etching the semiconductor layer not covered by the first sub-graphic layer and the semiconductor layer not covered by the second sub-graphic layer, and the remaining portion of the semiconductor layer forms the semiconductor pillars.

[0021] In some embodiments, the orthographic projection shape of the first sub-pattern layer on the surface of the substrate is a "concave" shape, and the orthographic projection shape of the second sub-pattern layer on the surface of the substrate is a "concave" shape.

[0022] In some embodiments, the first sub-pattern layer includes a first non-recessed side opposite to the first recessed side, and the second sub-pattern layer includes a second non-recessed side opposite to the second recessed side. The method for forming the word line includes: forming an isolation layer between adjacent semiconductor layers, wherein the isolation layer contacts the sidewall of the semiconductor layer, and the top surface of the isolation layer is flush with the top surface of the semiconductor layer; forming a plurality of second pattern layers spaced along a first direction on the top surface of the isolation layer, wherein a second pattern layer is directly opposite to the gap between the first non-recessed side and the second non-recessed side; etching the semiconductor layer with a second preset thickness along the surface of the semiconductor layer not covered by the first pattern layer to form a first groove, etching the isolation layer with a first preset thickness along the surface of the isolation layer not covered by the second pattern layer to form a second groove, wherein the first groove is connected to the second groove; forming a gate dielectric layer on the sidewall of the semiconductor column, wherein the gate dielectric layer also fills the gap between the first non-recessed side and the second non-recessed side; forming the word line filled in the first groove and the second groove, and the word line covers the gate dielectric layer.

[0023] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0024] In the semiconductor structure provided by the embodiment of the present disclosure, the first side surface corresponding to the channel region of the semiconductor column has a depression, thereby increasing the surface area of ​​the first side surface compared to the case without the depression. The word line covers the first side surface corresponding to the channel region. Since the surface area of ​​the first side surface increases, the contact area between the word line and the channel region increases, thereby increasing the channel length of the transistor, enhancing the control ability of the word line over the transistor, and improving the electrical performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, and these exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise specified, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0026] Figure 1 A schematic diagram of a top view of a semiconductor structure;

[0027] Figure 2 A schematic diagram of a top view of a semiconductor structure provided by an embodiment of the present disclosure;

[0028] Figure 3 for Figure 2 Schematic diagram of the partial cross-section structure along the aa' direction;

[0029] Figure 4 A schematic diagram of a top view of another semiconductor structure provided by an embodiment of the present disclosure;

[0030] Figure 5 A schematic diagram of a top view of another semiconductor structure provided by an embodiment of the present disclosure;

[0031] Figures 6 to 22 A schematic top view of the structure corresponding to each step of a method for preparing a semiconductor structure provided in another embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] As can be seen from the background technology, the performance of the current semiconductor structure needs to be further improved. Figure 1 An analysis of one of the reasons for the poor performance of the semiconductor structure found that the current semiconductor structure includes: a semiconductor column 1 and a word line 2 arranged around the channel region of the semiconductor column 1. As the size of the semiconductor structure becomes smaller and smaller, the contact area between the word line and the channel region in the semiconductor column becomes smaller and smaller, resulting in a shorter channel length of the transistor and a weaker control ability of the word line over the channel, which in turn leads to poor electrical performance of the semiconductor structure.

[0033] The disclosed embodiment provides a semiconductor structure, wherein the first side surface corresponding to the channel region of the semiconductor column has a depression, thereby increasing the surface area of ​​the first side surface compared to a case without the depression. The word line covers the first side surface corresponding to the channel region, and due to the increase in the surface area of ​​the first side surface, the contact area between the word line and the channel region increases, thereby increasing the channel length of the transistor, enhancing the control capability of the word line over the transistor, and improving the electrical performance of the semiconductor structure.

[0034] The following will describe the various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented.

[0035] Figure 2 A schematic diagram of a top view of a semiconductor structure provided by an embodiment of the present disclosure; Figure 3 for Figure 2 A partial structural schematic diagram of the cross-sectional structure along the aa' direction; Figure 4 Another schematic diagram of a top view of a semiconductor structure provided by an embodiment of the present disclosure; Figure 5 A schematic top view of another semiconductor structure provided in accordance with an embodiment of the present disclosure.

[0036] refer to Figures 2 to 5 The semiconductor structure includes: a substrate. The semiconductor structure also includes: a semiconductor column 101, located on the surface of the substrate, the semiconductor column 101 has a channel region 111, the semiconductor column 101 has a first side surface 11, and at least a portion of the first side surface 11 corresponding to the channel region 111 is recessed toward the center of the semiconductor column 101. The semiconductor structure also includes: a word line 102, the word line 102 at least covers the first side surface 11 corresponding to the channel region 111.

[0037] In some embodiments, the material of the substrate may be a semiconductor material. In some embodiments, the material of the substrate may be silicon. In some embodiments, the substrate may also be germanium, germanium silicon, or silicon on insulator.

[0038] In some embodiments, the material of the semiconductor pillar 101 may be the same as that of the substrate. In some implementations, the material of the semiconductor pillar 101 may be silicon. In some embodiments, the material of the semiconductor pillar 101 may also be germanium, germanium silicon, or silicon on insulator.

[0039] refer to Figure 3 In some embodiments, the semiconductor column 101 further includes doped regions located on both sides of the channel region 111, and the doped regions may include: a first doped region 112 and a second doped region 113. The first doped region 112 is located on the side of the channel region 111 facing the substrate, and the second doped region 113 is located on the side of the channel region 111 away from the substrate. The first doped region 112, the second doped region 113, and the channel region 111 are used to form a transistor. In some embodiments, the first doped region 112 is used to form a source of the transistor, the second doped region 113 is used to form a drain of the transistor, and the channel region 111 is used to form a channel of the transistor.

[0040] In some embodiments, the doping ion type of the first doping region 112 is the same as the doping ion type of the second doping region 113 , and the doping ion type of the first doping region 112 is different from the doping ion type of the channel region 111 .

[0041] In some embodiments, the doping ion type of the first doping region 112 is P type, the doping ion type of the second doping region 113 is N type, and the doping ion type of the channel region 111 is P type.

[0042] In some embodiments, the doping ion type of the first doping region 112 is N-type, the doping ion type of the second doping region 113 is P-type, and the doping ion type of the channel region 111 is N-type.

[0043] In some embodiments, the doping ion type of the first doping region 112 is the same as the doping ion type of the second doping region 113 and the doping ion type of the channel region 111 , and the doping ion concentration of the channel region 111 is less than the doping ion concentrations of the first doping region 112 and the second doping region 113 .

[0044] In some embodiments, the P-type doping ions may include any one of boron ions, aluminum ions, gallium ions, or indium ions. In some embodiments, the N-type doping ions may include any one of phosphorus ions, bismuth ions, antimony ions, or arsenic ions.

[0045] In some embodiments, the semiconductor structure further includes a bit line 104 . The bit line 104 is located on a side of the first doped region 112 facing the substrate and is in electrical contact with a surface of the first doped region 112 facing the substrate.

[0046] In some embodiments, the bit line 104 can be obtained by doping a substrate corresponding to the semiconductor pillar 101 so that a portion of the substrate corresponding to the bottom surface of the semiconductor pillar 101 has conductivity.

[0047] In some embodiments, the substrate corresponding to the semiconductor pillar 101 may be etched to form a groove in the substrate corresponding to the bottom of the semiconductor pillar 101, the groove exposing the bottom surface of the semiconductor pillar 101, and then the bit line 104 is deposited in the groove. In one embodiment, the material of the bit line 104 may include a metal material, for example, at least one of aluminum, tungsten, silver, copper, gold, cobalt, nickel, or nail.

[0048] In some embodiments, there are a plurality of semiconductor pillars 101, and the plurality of semiconductor pillars 101 are arranged at intervals along the first direction X and the second direction Y. There are a plurality of bit lines 104, each bit line 104 extends along the first direction X, and the plurality of bit lines 104 are arranged at intervals along the second direction Y, and the bit lines 104 are in electrical contact with the first doped region 112 of each of the plurality of semiconductor pillars 101 arranged at intervals along the first direction X.

[0049] The first side surface 11 of the semiconductor column 101 has a recess, which increases the surface area of ​​the first side surface 11 compared to the case where the first side surface 11 does not have a recess, thereby increasing the contact area between the word line 102 on the first side surface 11 covering the channel area 111 and the channel area 111, thereby increasing the channel length of the transistor, thereby enhancing the control ability of the word line 102 over the channel, improving the response rate of the transistor, and improving the electrical performance of the semiconductor structure.

[0050] It is worth noting that the semiconductor pillar 101 has a top surface and a bottom surface parallel to the substrate surface, and also has a side surface connected to the top surface and the bottom surface. The first side surface 11 referred to here is the side surface of the semiconductor pillar 101.

[0051] In some embodiments, the orthographic projection of the semiconductor column 101 on the substrate surface is circular or elliptical, that is, the semiconductor column 101 has no ridges, and the first side surface 11 can be any part of the side surface of the semiconductor. In some embodiments, the semiconductor column 101 has ridges, that is, the semiconductor column 101 has multiple side surfaces divided by ridges in different directions, and the first side surface 11 can be one of the side surfaces of the semiconductor column 101.

[0052] refer to Figure 2 , only a portion of the first side surface 11 is recessed toward the center of the semiconductor column 101. In some embodiments, the semiconductor column further includes: doped regions located on both sides of the channel region 111, the arrangement direction of the channel region 111 and the doped regions is perpendicular to the substrate surface, and a portion of the first side surface 11 corresponding to the channel region 111 is recessed toward the center of the semiconductor column 101 to form a first groove, which extends in a direction away from the surface of the substrate, and the first groove spans the doped region and the channel region 111.

[0053] In some embodiments, the orthographic projection shape of the first groove on the surface of the substrate may be a “concave” shape.

[0054] In some embodiments, the doping region includes a first doping region 112 and a second doping region 113, the first doping region 112 is located on the side of the channel region 111 facing the substrate, and the second doping region 113 is located on the side of the channel region 111 away from the substrate, and the first groove may only span the channel region 111 and the second doping region 113. In other words, the first side surface 11 corresponding to the first doping region 112 does not have a depression toward the center of the semiconductor column 101. In this way, it can be ensured that the semiconductor column 101 corresponding to the first doping region 112 has a larger area, thereby increasing the contact area between the bit line 104 and the bottom surface of the semiconductor column 101 corresponding to the first doping region 112, thereby improving the electrical connection performance between the bit line 104 and the first doping region 112. The second doped region 113 and the first side surface 111 of the channel region 111 have a depression toward the center of the semiconductor column 101, so that in the actual step of forming the depression, the second doped region 113 can be etched from the top of the second doped region 113. The second doped region 113 is located at the top of the semiconductor column 101, that is, the semiconductor column 101 can be etched from the top of the semiconductor column 101 to form a first groove, which is conducive to simplifying the process of forming the first groove.

[0055] In some embodiments, the first groove may also span the first doped region 112 , the second doped region 113 and the channel region 111 , that is, the first side surfaces 11 corresponding to the first doped region 112 , the second doped region 113 and the channel region 111 all have a depression toward the center of the semiconductor column 101 .

[0056] In some embodiments, a portion of the first side surface 11 corresponding to the channel region 111 is recessed toward the center of the semiconductor column 101 to form a first groove, and the number of the first grooves is multiple, and the multiple first grooves are arranged at intervals. In other words, the multiple first grooves can be dispersedly arranged on the first side surface 11. In some embodiments, the multiple first grooves can be arranged at intervals along a direction perpendicular to the substrate surface.

[0057] In some embodiments, the orthographic projection shape of the first groove on the first side surface 11 may be at least one of a circle, a rectangle, or a polygon.

[0058] In some embodiments, the semiconductor column 101 has a second side surface 12 opposite to the first side surface 11, and the distance between the first side surface 11 and the second side surface 12 is a first distance. The first groove is recessed from the first side surface 11 toward the second side surface 12, and the ratio of the recess depth of the first groove to the first distance is less than or equal to 0.7. Within this range, on the one hand, the recess depth of the first groove is larger, so that the first side surface 11 has a larger surface area, which is beneficial to increase the contact area between the word line 102 and the first side surface 11. On the other hand, within the above range, the recess depth of the first groove is not too large, so as to prevent the first distance from being too small due to the excessive recess depth of the first groove, that is, the distance between the first side surface 11 and the second side surface 12 is too small, so that the volume of the semiconductor column 101 is too small, and the electrical performance of the semiconductor column 101 is deteriorated.

[0059] refer to Figure 4 In some embodiments, part of the second side surface 12 corresponding to the channel region is recessed toward the center of the semiconductor column 101, and the word line 102 also covers the second side surface 12 corresponding to the channel region 111. That is, both the first side surface 11 and the second side surface 12 are recessed toward the center of the semiconductor column 101. Part of the first side surface 11 is recessed toward the direction of the second side surface 12, and part of the second side surface 12 is recessed toward the direction of the first side surface 11. In this way, the surface area of ​​the side surface of the semiconductor column 101 in the channel region 111 can be further increased. The word line 102 covers the first side surface 11 of the channel region 111 and the second side surface 12 of the channel region 111, so that the contact area between the word line 102 and the channel region 111 is further increased, thereby further increasing the length of the channel, enhancing the control ability of the word line 102 over the channel, and thereby improving the electrical performance of the semiconductor structure.

[0060] In some embodiments, a portion of the second side surface 12 is recessed toward the center of the semiconductor pillar 101 to form a second groove.

[0061] In some embodiments, the second groove crosses the large second doped region 113 and the channel region 111 .

[0062] In some embodiments, the second groove is adjacent to the first doped region 112 , the channel region 111 , and the second doped region 113 .

[0063] In some embodiments, there are multiple second grooves, and the multiple second grooves are arranged at intervals. In a specific example, the multiple second grooves are arranged at intervals along a direction perpendicular to the surface of the substrate.

[0064] In some embodiments, a portion of the first side surface 11 is recessed toward the center of the semiconductor column 101 to form a first groove, a portion of the second side surface 12 is recessed toward the center of the semiconductor column 101 to form a second groove, and the ratio of the sum of the recess depth of the first groove and the recess depth of the second groove to the first distance is less than or equal to 0.7. Within this range, it can be ensured that the first distance is not too small, so that the thickness of the semiconductor column 101 in the direction from the first side surface 11 to the first side surface 11 is not too small, thereby ensuring that the electrical performance of the semiconductor column 101 is better.

[0065] refer to Figure 4 In some embodiments, part of the second side surface 12 is recessed toward the center of the semiconductor pillar 101, and the word line 102 surrounds the entire side surface corresponding to the semiconductor pillar 101 in the channel region 111. In other words, the word line 102 surrounds the entire side surface of the semiconductor pillar 101 in the channel region 111, so that the word line 102 can be ensured to be located in the first groove and the first groove, thereby increasing the contact area between the word line 102 and the channel region 111.

[0066] Specifically, in some embodiments, the side surface of the semiconductor column 101 further includes a third side surface and a fourth side surface, the third side surface and the fourth side surface are arranged opposite to each other, and the first side surface 11, the second side surface 12, the third side surface and the fourth side surface are sequentially connected to form the semiconductor column 101. The entire side surface of the semiconductor column 101 referred to here includes the first side surface 11, the second side surface 12, the third side surface and the fourth side surface.

[0067] It is worth noting that in some embodiments, a portion of the first side surface 11 is recessed toward the center of the semiconductor column 101, a portion of the second side surface 12 is recessed toward the center of the semiconductor column 101, and the number of semiconductor columns is multiple, including: multiple rows of semiconductor columns 101 arranged at intervals along the first direction X, wherein each row of semiconductor columns 101 includes multiple semiconductor columns 101 arranged at intervals along the second direction Y, the number of word lines 102 is multiple, each word line 102 extends along the second direction Y, and a word line 102 covers the first side surface 11 corresponding to the channel region 111 of each semiconductor column 101 in a row of semiconductor columns 101.

[0068] That is, one word line 102 corresponds to one row of semiconductor pillars 101 , one word line 102 only covers the side surfaces of the channel regions 111 of one row of semiconductor pillars 101 , and one word line 102 covers the side surfaces of the semiconductor pillars 101 in the entire channel regions 111 of one row of semiconductor pillars 101 .

[0069] In some embodiments, an isolation layer 105 is provided between adjacent word lines 102, and the side of the isolation layer 105 is in contact with the side of the word line 102. The isolation layer 105 is used to isolate adjacent word lines 102 to prevent signal crosstalk between adjacent word lines 102. In some embodiments, the material of the isolation layer 105 may be an insulating material such as silicon nitride, silicon oxynitride, or silicon oxide. In some embodiments, the material of the word line 102 may be a metal material, for example, at least one of aluminum, tungsten, silver, copper, gold, cobalt, nickel, or ruthenium.

[0070] refer to Figure 5 In some embodiments, there are multiple semiconductor columns, and the multiple semiconductor columns 101 include: first sub-semiconductor columns 101 and second sub-semiconductor columns 101 alternately arranged along the first direction X, wherein the first side surface 11 of the first sub-semiconductor column 101 and the first side surface 11 of the second sub-semiconductor column 101 are arranged opposite to each other along the first direction X.

[0071] Specifically, part of the first side surface 11 of the first sub-semiconductor column 101 is recessed toward the center of the first sub-semiconductor column 101 to form a first sub-groove, and part of the first side surface 11 of the second sub-semiconductor column 101 is recessed toward the center of the second sub-semiconductor column 101 to form a second sub-groove, and the first sub-groove and the second sub-groove are arranged face to face.

[0072] In some embodiments, the orthographic projection shape of the first sub-groove on the surface of the substrate is a "concave" shape, and the orthographic projection shape of the second sub-groove on the surface of the substrate is a "concave" shape.

[0073] In some embodiments, a word line 102 covers the first side surface 11 of the channel region 111 of a first sub-semiconductor column 101 and the first side surface 11 of the channel region 111 of a second sub-semiconductor column 101 that are arranged opposite to each other. That is, the word line 102 is located between the first side surface 11 and the second side surface 12 of the first sub-semiconductor column 101, and the word line 102 is also located in the first sub-groove and the second sub-groove, and the word line 102 is electrically in contact with both the first sub-semiconductor column 101 and the second sub-semiconductor column 101, that is, one word line 102 controls the first sub-semiconductor column 101 and the second sub-semiconductor column 101.

[0074] The channel region 111 of the first sub-semiconductor column 101 and the channel region 111 of the second sub-semiconductor column 101 are used together to form the channel region 111 of a transistor. Compared with the word line 102 only covering the first side surface 11 of a semiconductor column 101, the word line 102 contacts the first side surface 11 of the first sub-semiconductor column 101 and the first side surface 11 of the second sub-semiconductor column 101, so that the contact area between the word line 102 and the channel region 111 is further increased, so that the channel length of the transistor formed by the first sub-semiconductor column 101 and the second sub-semiconductor column 101 is increased, which is beneficial to enhance the control ability of the word line 102 over the transistor.

[0075] In some embodiments, the first sub-semiconductor pillar 101 and the second sub-semiconductor pillar 101 both include a second side surface 12 opposite to the first side surface 11, and the second side surface 12 is exposed outside the word line 102. In other words, the word line 102 does not cover the second side surface 12. It can be understood that the same word line 102 covers the first side surface 11 of the first sub-semiconductor pillar 101 and the first side surface 11 of the second sub-semiconductor pillar 101. If the word line 102 also covers the second side surface 12 of the first sub-semiconductor pillar 101 and the second side surface 12 of the second sub-semiconductor pillar 101, then compared with the word line 102 only surrounding the side surface of one semiconductor pillar 101, the thickness of the word line 102 in the direction from the first side surface 11 to the second side surface 12 will increase, so that within the same area, the number of word lines 102 will be reduced, which is not conducive to improving the integration of the semiconductor structure.

[0076] Therefore, setting the word line 102 not to cover the second side surface 12 can ensure that the contact area between the word line 102 and the channel region 111 is increased without increasing the thickness of the word line 102 in the direction from the first side surface 11 to the second side surface 12, thereby enhancing the control ability of the word line 102 over the channel.

[0077] In a specific example, the first sub-semiconductor column 101 and the second sub-semiconductor column 101 both include: a third side surface connected to the first side surface 11, and a fourth side surface arranged opposite to the third side surface, and the word line 102 also covers at least a portion of the third side surface and at least a portion of the fourth side surface of the first sub-semiconductor column 101, and covers at least a portion of the third side surface and at least a portion of the fourth side surface of the second sub-semiconductor column 101.

[0078] That is to say, the relatively arranged first sub-semiconductor column 101 and the second sub-semiconductor column 101 are surrounded on three sides by the same word line 102, so that the contact area between the word line 102 and the side surface of the channel region 111 of the first sub-semiconductor column 101 and the side surface of the channel region 111 of the second sub-semiconductor column 101 is further increased.

[0079] In some embodiments, the word line 102 surrounds a portion of the third side surface of the channel region 111 of the first sub-semiconductor pillar 101 and a portion of the fourth side surface of the channel region 111. In some embodiments, the word line 102 surrounds a portion of the third side surface of the channel region 111 of the second sub-semiconductor pillar 101 and a portion of the fourth side surface of the channel region 111. In some embodiments, the word line 102 surrounds the entire third side surface of the channel region 111 of the first sub-semiconductor pillar 101 and the entire fourth side surface of the channel region 111.

[0080] In some embodiments, the first sub-semiconductor pillar 101 and the second sub-semiconductor pillar 101 both include: a third side surface connected to the first side surface 11, and a fourth side surface disposed opposite to the third side surface. In a specific example, the word line 102 may cover at least a portion of the third side surface, at least a portion of the fourth side surface, and the first side surface 11 of the first sub-semiconductor pillar 101, and only cover the first side surface 11 of the second sub-semiconductor pillar 101. In another specific example, the word line 102 may only cover the first side surface 11 of the first sub-semiconductor pillar 101, and cover at least a portion of the third side surface, at least a portion of the fourth side surface, and the first side surface 11 of the second sub-semiconductor pillar 101.

[0081] refer to Figure 5 In some embodiments, the semiconductor structure includes: a plurality of rows of first sub-semiconductor pillars 101 arranged at intervals along a first direction X, each row of the first sub-semiconductor pillars 101 includes a plurality of first sub-semiconductor pillars 101 arranged at intervals along a second direction Y; a plurality of rows of second sub-semiconductor pillars 101 arranged at intervals along the second direction Y, each row of second sub-semiconductor pillars 101 includes a plurality of second sub-semiconductor pillars 101 arranged at intervals along the second direction Y, each row of first sub-semiconductor pillars 101 and each row of second sub-semiconductors are alternately arranged along the first direction X; there are a plurality of word lines 102, each word line 102 covers a first side surface 11 corresponding to a channel region 111 in a row of first sub-semiconductor pillars 101 and a row of second sub-semiconductors that are alternately arranged.

[0082] Specifically, a row of first sub-semiconductor pillars 101 and a row of second sub-semiconductor pillars 101 that are arranged opposite to each other are recorded as a semiconductor pillar 101 group. In each semiconductor pillar 101 group, the first sub-grooves of the first side surfaces 11 of the first sub-semiconductor pillars 101 are arranged opposite to the second sub-grooves of the first side surfaces 11 of the second sub-semiconductor pillars 101. One word line 102 corresponds to one semiconductor pillar 101 group, and is located between a row of first sub-semiconductor pillars 101 and a row of second sub-semiconductor pillars 101 that belong to the same semiconductor pillar 101 group.

[0083] In some embodiments, reference Figures 2 to 5 , further comprising: a gate dielectric layer 103, the gate dielectric layer 103 being located between the word line 102 and the semiconductor pillar 101. The gate dielectric layer 103 is located on the side of the semiconductor pillar 101 in the channel region 111, and the word line 102 covers the surface of the gate dielectric layer 103. In some embodiments, the material of the gate dielectric layer 103 may be silicon oxide.

[0084] refer to Figures 2 to 4 In some embodiments, a word line 102 covers the channel regions 111 of a row of semiconductor pillars 101 arranged at intervals along the second direction Y, and the gate dielectric layer 103 is located on the side of the channel region 111 of each semiconductor pillar 101 .

[0085] refer to Figure 5 In some embodiments, there are multiple semiconductor pillars, and the multiple semiconductor pillars 101 include: first sub-semiconductor pillars 114 and second sub-semiconductor pillars 115 are alternately arranged along the first direction X, a word line 102 covers the first side surface 11 of the channel region 111 of a first sub-semiconductor pillar 114 and the first side surface 11 of the channel region 111 of a second sub-semiconductor pillar 115 that are relatively arranged, and the gate dielectric layer 103 covers the entire side surface of the channel region 111 of the first sub-semiconductor pillar 114 corresponding to a word line 102 and the entire side surface of the channel region 111 of the second sub-semiconductor pillar 115 corresponding to another adjacent word line 102.

[0086] Specifically, the semiconductor columns arranged at intervals along the first direction X are divided into first sub-semiconductor column groups 14 and second sub-semiconductor column groups 15 arranged alternately, and the second sub-semiconductor columns 115 in the first sub-semiconductor column group 14 are adjacent to the first sub-semiconductor columns 114 in the second sub-semiconductor column group 15 .

[0087] The word line 102 includes: a first sub-word line 102 located between adjacent first sub-semiconductor pillars 114 and adjacent second sub-semiconductor pillars 115 in the first sub-semiconductor pillar group 14, and a second sub-word line 102 located between adjacent first sub-semiconductor pillars 114 and adjacent second sub-semiconductor pillars 115 in the second sub-semiconductor pillar group 15. That is, the first sub-word line 102 corresponds to the first sub-semiconductor pillar group 14, and the second sub-word line 102 corresponds to the second sub-semiconductor pillar group 15. An isolation layer 105 is provided between the first sub-word line 102 and the second sub-word line 102 for isolating the first sub-word line 102 from the second sub-word line 102.

[0088] The gate dielectric layer 103 covers the side of the channel region 111 of the second sub-semiconductor column 115 belonging to the first sub-semiconductor column group 14 and covers the side of the channel region 111 of the first sub-semiconductor column 114 belonging to the second sub-semiconductor column group 15. The gate dielectric layer 103 is also located in the gap between the second sub-semiconductor column 115 belonging to the first sub-semiconductor column group 14 and the first sub-semiconductor column 114 belonging to the second sub-semiconductor column group 15, and is used to isolate the first sub-semiconductor column 114 and the second sub-semiconductor column 115 that do not belong to the same semiconductor column 101 group.

[0089] In the semiconductor structure provided by the above embodiment, the first side surface 11 corresponding to the channel region 111 of the semiconductor pillar 101 has a depression, thereby increasing the surface area of ​​the first side surface 11 compared to the case without the depression. The word line 102 covers the first side surface 11 corresponding to the channel region 111. Since the surface area of ​​the first side surface 11 increases, the contact area between the word line 102 and the channel region 111 increases, thereby increasing the channel length of the transistor, enhancing the control capability of the word line 102 over the transistor, and improving the electrical performance of the semiconductor structure.

[0090] Correspondingly, an embodiment of the present disclosure also provides a method for preparing a semiconductor structure, which can be used to prepare the semiconductor structure provided by the above embodiment. The semiconductor structure provided by an embodiment of the present disclosure will be described in detail below in conjunction with the accompanying drawings.

[0091] Figure 7 for Figure 6 Schematic diagram of the cross-sectional structure along the AA' direction, Fig. 9 for Figure 8 Schematic diagram of the cross-sectional structure along the AA' direction, Fig.11 for Fig.10 Schematic diagram of the cross-sectional structure along the AA' direction, Fig.13 for Fig.12 Schematic diagram of the cross-sectional structure along the AA' direction, Fig.15 for Fig.14 Schematic diagram of the cross-sectional structure along the AA' direction.

[0092] refer to Figures 6 to 15 , the method for preparing the semiconductor structure comprises:

[0093] A substrate 100 is provided, and a semiconductor column 101 is formed on the surface of the substrate 100 . The semiconductor column 101 has a channel region 111 . The semiconductor column 101 has a first side surface 11 . At least a portion of the first side surface 11 corresponding to the channel region 111 is recessed toward the center of the semiconductor column 101 .

[0094] In some embodiments, a method of forming the semiconductor pillar 101 includes:

[0095] refer to Figure 6 as well as Figure 7 , providing an initial substrate (not shown). In some embodiments, the material of the initial substrate may be a semiconductor material. In some embodiments, the material of the initial substrate may be silicon. In some embodiments, the initial substrate may also be germanium, germanium silicon, or silicon on insulator.

[0096] Afterwards, a portion of the initial substrate is etched to form semiconductor layers 20 arranged at intervals along the second direction Y, and the remaining portion of the initial substrate serves as the substrate 100. Each semiconductor layer 20 extends along the first direction X.

[0097] In some embodiments, the method of etching a portion of the initial substrate to form the semiconductor layer 20 includes: performing a patterning process on the surface of the initial substrate to define the position of the initial semiconductor portion. In some embodiments, the surface of the initial substrate can be patterned using either a SADP (Self-aligned Double Patterning) process or a SAQP (Self-Aligned Quadruple Patterning) process. Afterwards, an etching process is performed on the patterned surface of the initial substrate to etch a portion of the thickness of the initial substrate to form a mutually discrete semiconductor layer 20. In some embodiments, the etching process can be either a dry etching process or a wet etching process.

[0098] refer to Figure 8 as well as Fig. 9In some embodiments, after forming the mutually separated semiconductor layers 20, the bit lines 104 are formed. The adjacent semiconductor layers 20 expose a portion of the surface of the substrate 100, and the substrate 100 is doped from the gap between the adjacent semiconductor layers 20 to convert the portion of the thickness of the substrate 100 directly opposite to the semiconductor layer 20 into a conductive bit line 104. In some embodiments, the substrate 100 may be doped using an ion implantation process. The implantation angle of the ion implantation process may be controlled to convert the substrate 100 directly opposite to the semiconductor layer 20 into the bit line 104, so that the formed bit line 104 is consistent with the extension direction of the semiconductor layer 20, that is, extends along the first direction X. In this way, after the semiconductor layer 20 is subsequently etched to form the semiconductor pillars 101 arranged at intervals along the first direction X, the semiconductor pillars 101 extending along the first direction X may be electrically contacted with each of the plurality of semiconductor pillars 101 arranged at intervals along the first direction X.

[0099] refer to Fig.12 as well as Fig.13 , a first pattern layer 30 is formed on a portion of the surface of the semiconductor layer 20, and the first pattern layer 30 is used to define the cross-sectional shape of the semiconductor pillar 101 parallel to the surface of the substrate 100. In some embodiments, the first pattern layer 30 can be formed on the surface of the semiconductor layer 20 by using either a SADP process or a SAQP process. In some embodiments, the first pattern layer 30 can be any one of a photoresist, a spin-on hard mask, or silicon oxide.

[0100] refer to Fig.14 as well as Fig.15 After forming the first pattern layer 30, the semiconductor layer 20 not covered by the first pattern layer 30 is etched, and the remaining part of the semiconductor layer 20 forms a semiconductor pillar 101. The semiconductor layer 20 other than the first pattern layer 30 is etched, and the semiconductor layer 20 covered by the first pattern layer 30 is retained. The cross-sectional shape of the semiconductor layer 20 not etched in the direction parallel to the surface of the substrate 100 is the same as the shape of the first pattern layer 30. The shape of the first pattern layer 30 is set to have a concave shape, so that the formed semiconductor pillar 101 also has a concave shape.

[0101] In some embodiments, the semiconductor column 101 has a channel region 111 and first and second doped regions 113 located on both sides of the channel region 111 . The first doped region 112 is located on the side of the channel region 111 facing the substrate 100 , and the second doped region 113 is located on the side of the channel region 111 away from the substrate 100 .

[0102] In some embodiments, doping processes may be performed on different portions of the same semiconductor column 101 to form the first doping region 112 , the second doping region 113 , and the channel region 111 , respectively.

[0103] In some embodiments, after etching to form the semiconductor column 101, different parts of the semiconductor column 101 may be doped to respectively form a first doping region 112, a second doping region 113, and a channel region 111. Specifically, the semiconductor column 101 includes a first region, a second region, and a third region sequentially arranged in a direction perpendicular to the surface of the substrate 100. The method for forming the semiconductor column 101 includes:

[0104] The first region, the second region, and the third region are respectively subjected to a doping process to transform the first region into a first doping region 112, transform the second region into a channel region 111, and transform the third region into a second doping region 113. The doping ion type of the first doping region 112 is the same as the doping ion type of the second doping region 113, and the doping ion type of the second doping region 113 is different from the doping ion type of the channel region 111. In some embodiments, the doping process may be an ion implantation process.

[0105] Since the doping ion type of the first doping region 112 is the same as the doping ion type of the second doping region 113, the first region and the third region can be doped in the same process step to respectively form the second doping region 113 and the first doping region 112. In the step of doping the first region and the third region, a mask layer is formed on the side of the semiconductor portion of the second region to protect the second region and prevent the doping ions from diffusing into the second region.

[0106] It is understandable that, in the step of doping the second region, a mask layer may also be formed on the side of the semiconductor portion of the first region and the third region to protect the first region and the third region and prevent the doping ions from diffusing into the first region and the third region. In some embodiments, the mask layer may be silicon oxide, which may be formed by a thermal oxidation process.

[0107] In some embodiments, P-type dopant ions may be implanted into the first region and the third region, and N-type dopant ions may be implanted into the second region. In some embodiments, N-type dopant ions may be implanted into the first region and the third region, and P-type dopant ions may be implanted into the second region.

[0108] In some embodiments, the P-type doping ions may include any one of boron ions, aluminum ions, gallium ions, or indium ions. In some embodiments, the N-type doping ions may include any one of phosphorus ions, bismuth ions, antimony ions, or arsenic ions.

[0109] In some embodiments, before forming the semiconductor pillar 101, different parts of the semiconductor layer 20 may be doped to form the first doping region 112, the second doping region 113 and the channel region 111. In this way, only a small number of semiconductor layers 20 need to be doped, simplifying the process.

[0110] In some embodiments, the plurality of semiconductor pillars 101 include: first sub-semiconductor pillars 114 arranged alternately along a first direction X (refer to Figure 5 ) and the second semiconductor sub-column 115 (reference Figure 5 ), wherein the first side surface 11 of the first semiconductor sub-pillar 114 and the first side surface 11 of the second semiconductor sub-pillar 115 are arranged opposite to each other along the first direction X, and a word line 102 covers the first side surface 11 of the channel region 111 of the first semiconductor sub-pillar 114 and the first side surface 11 of the channel region 111 of the second semiconductor sub-pillar 115 which are arranged opposite to each other, and the method for forming the semiconductor pillar 101 includes:

[0111] refer to Fig.12 as well as Fig.13 A first pattern layer 30 is formed on a portion of the surface of the semiconductor layer 20. The first pattern layer 30 includes a first sub-pattern layer and a second sub-pattern layer alternately arranged along the first direction X. The first sub-pattern layer includes a first recessed side having a first recess, and the second sub-pattern layer includes a second recessed side having a second recess. The first recessed side and the second recessed side are arranged opposite to each other along the first direction X.

[0112] The first sub-pattern layer is used to define the cross-sectional shape of the first sub-semiconductor column 114 along the surface parallel to the substrate 100 , and the second sub-pattern layer is used to define the cross-sectional shape of the second sub-semiconductor column 115 along the surface parallel to the substrate 100 .

[0113] The first recess is used to define the orthographic projection shape of the first groove of the first side surface 11 of the first sub-semiconductor column 114 on the surface of the substrate 100 , and the second recess is used to define the orthographic projection shape of the first groove of the first side surface 11 of the second sub-semiconductor column 115 on the surface of the substrate 100 .

[0114] The first recessed side and the second recessed side are arranged opposite to each other along the first direction X. In the first sub-semiconductor column 114 and the second sub-semiconductor column 115 formed subsequently, the first side surface 11 of the first sub-semiconductor column 114 and the first side surface 11 of the second sub-semiconductor column 115 are face to face.

[0115] In some embodiments, the first graphic layer 30 and the second graphic layer can be formed by either SADP process or SAQP process. The material of the first graphic layer 30 can be any one of photoresist, spin-on hard mask or silicon oxide, and the material of the second graphic layer can be any one of photoresist, spin-on hard mask or silicon oxide.

[0116] In some embodiments, the orthographic projection shape of the first sub-pattern layer 30 on the surface of the substrate 100 is a "concave" shape, and the orthographic projection shape of the second sub-pattern layer on the surface of the substrate 100 is a "concave" shape. The concave side of the "concave" shape of the first sub-pattern layer is the first concave side, and the concave side of the "concave" shape of the second sub-pattern layer is the second concave side.

[0117] refer to Fig.14 as well as Fig.15 , the semiconductor layer 20 not covered by the first sub-pattern layer and the semiconductor layer 20 not covered by the second sub-pattern layer are etched, and the remaining semiconductor layer 20 forms a semiconductor pillar 101. In some embodiments, only a portion of the semiconductor layer 20 is etched, for example, only the semiconductor layer 20 corresponding to the second doping region 113 and the channel region 111 may be etched, so that the formed first groove only spans the second doping region 113 and the channel region 111, that is, the first side surface 11 corresponding to the first doping region 112 has no depression.

[0118] In some embodiments, the semiconductor layer 20 corresponding to the first doping region 112 , the second doping region 113 , and the channel region 111 may also be etched so that the formed first groove spans the first doping region 112 , the second doping region 113 , and the channel region 111 .

[0119] Fig.17 for Fig.16 Schematic diagram of the cross-sectional structure along the AA' direction, Fig.19 for Fig.18 Schematic diagram of the cross-sectional structure along the AA' direction.

[0120] refer to Figures 16 to 19 , forming a word line 102, the word line 102 at least covers the first side surface 11 corresponding to the channel region 111. Since the first side surface 11 has a depression, compared with the first side surface 11 without a depression, the surface area of ​​the first side surface 11 is greatly increased, that is, the area of ​​the channel region 111 is greatly increased, thereby increasing the contact area between the formed word line 102 and the channel region 111, increasing the channel length of the transistor, and thereby increasing the control capability of the word line 102 over the channel region 111 of the transistor.

[0121] In some embodiments, the first sub-pattern layer includes a first non-depressed side opposite to the first depressed side, and the second sub-pattern layer includes a second non-depressed side opposite to the second depressed side. The first non-depressed side is a side of the first sub-pattern layer that does not have a depression, and the second non-depressed side is a side of the second sub-pattern layer that does not have a depression. In some embodiments, the orthographic projection shape of the first sub-pattern layer on the surface of the substrate 100 is a "concave" shape, and the orthographic projection shape of the second sub-pattern layer on the surface of the substrate 100 is a "concave" shape. The depressed side of the "concave" shape of the first sub-pattern layer is the first depressed side, and the non-depressed side opposite to the depressed side is the first non-depressed side; the depressed side of the "concave" shape of the second sub-pattern layer is the second depressed side, and the non-depressed side opposite to the depressed side is the second non-depressed side. The method for forming the word line 102 includes:

[0122] An isolation layer 105 is formed between adjacent semiconductor layers 20 . The isolation layer 105 is in contact with the sidewalls of the semiconductor layer 20 , and a top surface of the isolation layer 105 is flush with a top surface of the semiconductor layer 20 .

[0123] In some embodiments, reference Fig.10 as well as Fig.11 After forming the bit lines 104, an isolation layer 105 may be formed between adjacent semiconductor layers 20. In some embodiments, a deposition process, such as an atomic layer deposition process or a chemical vapor deposition process, may be used to form the isolation layer 105 between adjacent semiconductor layers 20. In some embodiments, the material of the isolation layer 105 may be either silicon nitride or silicon oxynitride.

[0124] refer to Fig.12 as well as Fig.13 A plurality of second pattern layers 31 are formed on the top surface of the isolation layer 105 and are arranged at intervals along the first direction X. A second pattern layer 31 is directly opposite to the gap between the first non-recessed side and the second non-recessed side. The second pattern layer 31 is used to define the shape of the isolation layer 105 to be retained. After a plurality of word lines 102 are subsequently formed, the isolation layer 105 defined by the second pattern layer 31 can be used to isolate adjacent word lines 102.

[0125] Since each word line 102 formed subsequently covers the first side surface 11 of the first sub-semiconductor column 114 and the first side surface 11 of the second sub-semiconductor column 115, the first recessed side is used to define the first side surface 11 of the first sub-semiconductor column 114, and the second recessed side is used to define the first side surface 11 of the second semiconductor column 101. That is, the word line 102 formed subsequently is located in the area between the first recessed side and the second recessed side, so the second pattern layer 31 is arranged to face the gap between the first non-recessed side and the second non-recessed side, so that the isolation layer 105 formed subsequently and the formed word line 102 can be staggered, thereby isolating adjacent word lines 102.

[0126] In some embodiments, the second pattern layer 31 may be formed by using either a SADP process or a SAQP process. In some embodiments, the material of the second pattern layer 31 may be any one of a photoresist, a spin-on hard mask, or silicon oxide.

[0127] refer to Fig.14 as well as Fig.15 , the semiconductor layer 20 is etched to a second preset thickness along the surface of the semiconductor layer 20 not covered by the first pattern layer 30 to form a first trench 40, and the isolation layer 105 is etched to a first preset thickness along the surface of the isolation layer 105 not covered by the second pattern layer 31 to form a second trench (not shown), and the first trench 40 is connected to the second trench. The first trench 40 is connected to the second trench, so that the word line 102 formed subsequently can be located in the first trench 40 and the second trench, and the word line 102 located in the first trench 40 and the second trench is connected to form a word line 102 extending along the second direction Y, so that the same word line 102 can cover the first side surface 11 of the channel region 111 of the plurality of first sub-semiconductor pillars 114 arranged at intervals along the second direction Y and cover the first side surface 11 of the channel region 111 of the plurality of second sub-semiconductor pillars 115 arranged at intervals along the second direction Y.

[0128] In some embodiments, the semiconductor layer 20 and the isolation layer 105 may be etched by using either a dry etching process or a wet etching process.

[0129] refer to Fig.16 as well as Fig.17 In some embodiments, before forming the word line 102, the method further includes: forming a gate dielectric layer 103 on the sidewall of the semiconductor pillar 101, wherein the gate dielectric layer 103 also fills the gap between the first non-recessed side and the second non-recessed side.

[0130] In some embodiments, a deposition process may be used to form a gate dielectric layer 103 on the surface of the semiconductor column 101 in the channel region 111. In some embodiments, the material of the gate dielectric layer 103 may be silicon oxide, and a thermal oxidation process may be used to form the gate dielectric layer 103 on the surface of the semiconductor column 101. In some embodiments, the gate dielectric layer 103 located on the non-recessed side of the first sub-semiconductor layer 20 is also connected to the gate dielectric layer 103 located on the non-recessed side of the second sub-semiconductor column 115, and the gate dielectric layer 103 located between the first sub-semiconductor column 114 and the second sub-semiconductor column 115 is directly opposite to the isolation layer 105, so that the gate dielectric layer 103 located between the first sub-semiconductor column 114 and the second sub-semiconductor column 115 plays a role in isolating the adjacent first sub-semiconductor column 114 from the adjacent second sub-semiconductor column 115.

[0131] refer to Figures 16 to 19 , a word line 102 is formed filling the first trench 40 and the second trench, and the word line 102 covers the gate dielectric layer 103 .

[0132] refer to Figure 16 to Figure 17 An initial word line 22 is formed on the top surface of the semiconductor column 101, the top surface of the isolation layer 105, and the top surface of the gate dielectric layer 103. The initial word line 22 covers the entire surface of the semiconductor column 101, the top surface of the isolation layer 105, and the surface of the gate dielectric layer 103. The initial word line 22 is located on the surface of the gate dielectric layer 103 in the channel region 111 and the surface of the gate dielectric layer 103 in the second doping region 113.

[0133] In some embodiments, a deposition process such as an atomic layer deposition process or a chemical vapor deposition process may be used to form the initial word line 22. In some embodiments, the material of the initial word line 22 may be a metal material, such as at least one of aluminum, tungsten, silver, copper, gold, cobalt, nickel, or ruthenium.

[0134] refer to Figure 18 to Figure 19 ,in, Fig.19 for Fig.18 Schematic diagram of the cross-sectional structure along the AA' direction, the initial word line 22 is patterned to form a plurality of word lines 102 arranged at intervals along the first direction X, each word line 102 extends along the second direction Y, and each word line 102 covers the first side surface 11 of the channel region 111 of each first sub-semiconductor of a plurality of first sub-semiconductor pillars 114 arranged at intervals along the second direction Y and covers the first side surface 11 of the channel region 111 of each second sub-semiconductor pillar 115 arranged at intervals along the second direction Y.

[0135] In some embodiments, the word line 102 also covers at least a portion of the third side of the channel region 111 of the first sub-semiconductor column 114 and at least a portion of the fourth side of the channel region 111 , and the word line 102 also covers at least a portion of the third side of the channel region 111 of the second sub-semiconductor column 115 and at least a portion of the fourth side of the channel region 111 .

[0136] In some embodiments, the word line 102 covers a portion of the third side surface and a portion of the fourth side surface of the channel region 111 of the first sub-semiconductor column 114, and the word line 102 covers a portion of the third side surface and a portion of the fourth side surface of the channel region 111 of the second sub-semiconductor. Fig.12 , the width of the second graphic layer 31 along the first direction X can be controlled to be greater than the spacing between the first non-recessed side and the second non-recessed side. Fig.14, part of the third side and part of the fourth side of the first sub-semiconductor column 114 formed subsequently are opposite to the isolation layer 105, so that the word line 102 located on both sides of the isolation layer 105 cannot cover the third side and the fourth side opposite to the isolation layer 105, so that the formed word line 102 only covers part of the third side and part of the fourth side.

[0137] In some embodiments, the word line 102 covers the entire third side surface of the channel region 111 of the first sub-semiconductor column 114 and the entire fourth side surface of the channel region 111, and the word line 102 covers the entire third side surface of the channel region 111 of the second sub-semiconductor and the entire fourth side surface of the channel region 111. Fig.12 , the second graphic layer 31 can be controlled to be equal to the spacing between the first non-recessed side and the second non-recessed side along the first direction X, so that the reference Fig.14 , part of the third side and part of the fourth side of the first sub-semiconductor column 114 formed subsequently are offset from the isolation layer 105, so that the word lines 102 located on both sides of the isolation layer 105 cover the entire third side of the channel region 111 and the entire fourth side of the channel region 111.

[0138] In some embodiments, the method of patterning the initial word line 22 may include: patterning the top surface of the initial word line 22 to define the position of the word line 102. In some embodiments, the initial word line 22 may be etched by using either a SADP process or a SAQP process, and then the patterned initial word line 22 is etched to remove the gate dielectric layer 103 and the initial word line 22 on the side of the first sub-semiconductor column 114 in the second doping region 113, and to remove the gate dielectric layer 103 and the initial word line 22 on the side of the second sub-semiconductor column 115 in the second doping region 113, and the remaining initial word line 22 forms a plurality of word lines 102 arranged at intervals along the first direction X, and each word line 102 extends along the second direction Y. In some embodiments, the etching process may be either a dry etching process or a wet etching process.

[0139] refer to Figure 20 to Figure 22 , forming an isolation structure 106 . The isolation structure 106 is used to isolate the adjacent semiconductor pillars 101 corresponding to the second doping regions 113 .

[0140] In some embodiments, a method of forming the isolation structure 106 may include:

[0141] refer to Figure 20 to Figure 21, forming an initial isolation structure 23, the initial isolation structure 23 is located on the top surface of the word line 102, the top surface of the gate dielectric layer 103 and the top surface of the second doping region 113, and is also located between adjacent semiconductor pillars 101 corresponding to the second doping region 113. In some embodiments, a deposition process, such as an atomic layer deposition process, can be used to form the initial isolation structure 23, and the material of the initial isolation structure 23 can be silicon nitride.

[0142] refer to Fig. 22 , the initial isolation structure 23 is etched to expose the top surface of the semiconductor column 101 of the second doping region 113, and the remaining initial isolation structure 23 forms the isolation structure 106. In this way, other conductive structures, such as a capacitor structure, can be formed on the top surface of the semiconductor column 101 corresponding to the second doping region 113.

[0143] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for realizing the present disclosure, and in practical applications, various changes can be made to them in form and details without departing from the spirit and scope of the present disclosure. Any person skilled in the art can make their own changes and modifications without departing from the spirit and scope of the present disclosure, so the protection scope of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A semiconductor column, located on the surface of the substrate, the semiconductor column having a channel region, the semiconductor column having a first side surface, and at least a portion of the first side surface corresponding to the channel region is recessed toward the center of the semiconductor column; A word line at least covers the first side surface corresponding to the channel region.

2. The semiconductor structure according to claim 1, characterized in that: The semiconductor column also includes: doped regions located on both sides of the channel region, the arrangement direction of the channel region and the doped regions is perpendicular to the substrate surface, a portion of the first side surface corresponding to the channel region is recessed toward the center of the semiconductor column to form a first groove, the first groove extends in a direction away from the substrate surface, and the first groove spans the doped region and the channel region.

3. The semiconductor structure according to claim 1 or 2, characterized in that: A portion of the first side surface corresponding to the channel region is recessed toward the center of the semiconductor column to form a first groove. There are a plurality of first grooves, and the plurality of first grooves are arranged at intervals.

4. The semiconductor structure according to claim 1, characterized in that: The semiconductor column has a second side surface opposite to the first side surface, a portion of the second side surface corresponding to the channel region is recessed toward the center of the semiconductor column, and the word line also covers the second side surface corresponding to the channel region.

5. The semiconductor structure according to claim 1, characterized in that: There are multiple semiconductor columns, and the multiple semiconductor columns include: first sub-semiconductor columns and second sub-semiconductor columns are alternately arranged along a first direction, wherein the first side surface of the first sub-semiconductor column and the first side surface of the second sub-semiconductor column are arranged opposite to each other along the first direction.

6. The semiconductor structure according to claim 5, characterized in that: The word line covers a first side surface of a channel region of the first semiconductor sub-column and a first side surface of a channel region of the second semiconductor sub-column which are arranged opposite to each other.

7. The semiconductor structure according to claim 6, characterized in that: The first sub-semiconductor pillar and the second sub-semiconductor pillar each include a second side surface opposite to the first side surface, and the second side surface is exposed outside the word line.

8. The semiconductor structure according to claim 7, characterized in that: The first sub-semiconductor column and the second sub-semiconductor column both include: a third side surface connected to the first side surface, and a fourth side surface arranged opposite to the third side surface. The word line also covers at least a portion of the third side surface and at least a portion of the fourth side surface of the first sub-semiconductor column, and covers at least a portion of the third side surface and at least a portion of the fourth side surface of the second sub-semiconductor column.

9. The semiconductor structure according to any one of claims 5 to 8, characterized in that: The semiconductor structure comprises: A plurality of rows of first sub-semiconductor pillars arranged at intervals along a first direction, wherein each row of the first sub-semiconductor pillars comprises a plurality of first sub-semiconductor pillars arranged at intervals along a second direction; A plurality of rows of second sub-semiconductor columns are arranged at intervals along a second direction, each row of the second sub-semiconductor columns includes a plurality of second sub-semiconductor columns arranged at intervals along the second direction, each row of the first sub-semiconductor columns and each row of the second sub-semiconductors are alternately arranged along the first direction; a plurality of word lines are provided, each of the word lines covers the first side surface corresponding to the channel region in a row of the first sub-semiconductor columns and a row of the second sub-semiconductors that are alternately arranged.

10. The semiconductor structure according to claim 1 or 6, characterized in that: Also includes: a gate dielectric layer, the gate dielectric layer being located between the word line and the semiconductor column; There are multiple semiconductor pillars, and the multiple semiconductor pillars include: first sub-semiconductor pillars and second sub-semiconductor pillars are alternately arranged along a first direction, a word line covers a first side surface of a channel region of a first sub-semiconductor pillar and a first side surface of a channel region of the second sub-semiconductor pillar that are relatively arranged, and the gate dielectric layer covers an entire side surface of the channel region of the first sub-semiconductor pillar corresponding to a word line and an entire side surface of the channel region of the second sub-semiconductor pillar corresponding to another adjacent word line.

11. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; Forming a semiconductor column on the surface of the substrate, wherein the semiconductor column has a channel region, the semiconductor column has a first side surface, and at least a portion of the first side surface corresponding to the channel region is recessed toward the center of the semiconductor column; A word line is formed, wherein the word line at least covers the first side surface corresponding to the channel region.

12. The method for preparing a semiconductor structure according to claim 11, characterized in that: The method of forming the semiconductor pillar comprises: providing an initial substrate; Etching a portion of the initial substrate to form semiconductor layers arranged at intervals along the second direction, and the remaining portion of the initial substrate serves as the substrate; Forming a first pattern layer on a portion of the surface of the semiconductor layer, wherein the first pattern layer is used to define a cross-sectional shape of the semiconductor column parallel to the surface of the substrate; The semiconductor layer not covered by the first pattern layer is etched, and the remaining portion of the semiconductor layer forms the semiconductor column.

13. The method for preparing a semiconductor structure according to claim 12, characterized in that: The plurality of semiconductor pillars include: first sub-semiconductor pillars and second sub-semiconductor pillars are alternately arranged along a first direction, wherein the first side surface of the first sub-semiconductor pillar and the first side surface of the second sub-semiconductor pillar are arranged opposite to each other along the first direction, and a word line covers the first side surface of the channel region of the first sub-semiconductor pillar and the first side surface of the channel region of the second sub-semiconductor pillar that are arranged opposite to each other, and the method for forming the semiconductor pillars includes: forming a first pattern layer on a portion of the surface of the semiconductor layer, the first pattern layer comprising first sub-pattern layers and second sub-pattern layers alternately arranged along the first direction, the first sub-pattern layer comprising a first concave side having a first concave, the second sub-pattern layer comprising a second concave side having a second concave, the first concave side and the second concave side being arranged opposite to each other along the first direction; The semiconductor layer not covered by the first sub-pattern layer and the semiconductor layer not covered by the second sub-pattern layer are etched, and the remaining portion of the semiconductor layer forms the semiconductor pillar.

14. The method for preparing a semiconductor structure according to claim 13, characterized in that: The orthographic projection shape of the first sub-pattern layer on the surface of the base is a "concave" shape, and the orthographic projection shape of the second sub-pattern layer on the surface of the base is a "concave" shape.

15. The method for preparing a semiconductor structure according to claim 13 or 14, characterized in that: The first sub-pattern layer includes a first non-recessed side opposite to the first recessed side, the second sub-pattern layer includes a second non-recessed side opposite to the second recessed side, and the method for forming the word line includes: forming an isolation layer between adjacent semiconductor layers, wherein the isolation layer contacts the sidewalls of the semiconductor layer, and the top surface of the isolation layer is flush with the top surface of the semiconductor layer; A plurality of second graphic layers are formed on the top surface of the isolation layer and are arranged in a first direction at intervals, wherein the second graphic layer is directly opposite to the first non-recessed side and the gap between the second non-recessed side; Etching the semiconductor layer with a second preset thickness along the surface of the semiconductor layer not covered by the first pattern layer to form a first trench, and etching the isolation layer with a first preset thickness along the surface of the isolation layer not covered by the second pattern layer to form a second trench, wherein the first trench is connected to the second trench; forming a gate dielectric layer on the sidewall of the semiconductor column, wherein the gate dielectric layer also fills the gap between the first non-recessed side and the second non-recessed side; The word line filled in the first trench and the second trench is formed, and the word line covers the gate dielectric layer.

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