Wafer dynamic parameter test circuit and test method

Abstract

The invention provides a dynamic parameter test circuit and test method of a wafer, the test circuit can comprise a power supply module, a path selector, an energy storage module, an accompanying test device, a slide holder, a test module, a main test device and at least one auxiliary test device, the power supply module is used for providing a current signal; the energy storage module is used for storing current signals; the path selector is used for transmitting the current signal to the main test device and / or the auxiliary test device through the energy storage module and the slide holder, or transmitting the current signal to the main test device through the auxiliary test device and the energy storage module; the test accompanying device is connected between the auxiliary test device and the power supply module; the slide holder is used for fixing the main test device and transmitting a current signal provided by the power supply module; the test module is used for acquiring voltage and current of the main test device so as to determine a test result according to the voltage and current.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor characteristic testing, and in particular to a dynamic parameter testing circuit and testing method for a wafer. Background Art

[0002] At present, power semiconductor devices mainly include Metal Oxide Semiconductor Field Effect Transistor (MOSFET), bipolar transistor (BJT), diode (DIODE), SiC field effect transistor, GaN field effect transistor, insulated gate bipolar transistor (IGBT). In order to ensure the effective use of power semiconductor devices in power electronic systems, it is necessary to pre-test the intermediate products of the power semiconductor devices, i.e. wafers, to eliminate failed devices so that qualified devices can be used for subsequent packaging processes.

[0003] With the development of technological requirements, a large number of bare chips are used for the assembly of power switch modules, which requires that the DC parameters and AC parameters of the bare chip itself must meet the requirements of the power switch module. In order to improve the overall switching performance of the power switch module, it is necessary to perform matching tests on the DC parameters and AC parameters of the bare chip. However, there is a lack of corresponding testing means for wafer-level AC parameters, that is, dynamic parameter testing of the power semiconductor device, because the dynamic parameter testing of the power semiconductor device requires that the stray inductance in the test main circuit is extremely small, generally required to be at least less than 50nH, otherwise the stray inductance will cause a large current, resulting in a high voltage spike generated by the high-speed switch, and the voltage spike will destroy the accuracy of the dynamic parameter test data and also pose a threat to the safety of the power semiconductor device. Summary of the invention

[0004] In view of this, the present disclosure hopes to provide a dynamic parameter test circuit and test method for a wafer, which can reduce the influence of stray inductance in the test circuit, improve the accuracy and reliability of dynamic parameter testing of the main test device, and ensure the safety of the main test device.

[0005] The technical solution of the present disclosure is achieved as follows: In a first aspect, the present disclosure provides a dynamic parameter test circuit for a wafer, the test circuit comprising: a power module, a path selector, an energy storage module, a companion test device, a wafer carrier, a test module, a main test device, and at least one auxiliary test device, wherein: The power supply module is used to provide a current signal for the test circuit; The energy storage module is used to store the current signal; The router is used to transmit the current signal to the main test device and / or the auxiliary test device via the energy storage module and the wafer stage, or to transmit the current signal to the main test device via the auxiliary test device and the energy storage module; The accompanying test device is connected between the auxiliary test device and the power module; The wafer stage is used to fix the main test device and transmit the current signal provided by the power module; The test module is used to obtain the voltage and current of the main test device to determine the test result according to the voltage and current. In a second aspect, the present disclosure provides a method for testing dynamic parameters of a wafer, the testing method being applied to the test circuit described in the first aspect, the testing method comprising: Determine the driving signal according to the parameters to be tested; Controlling the states of the main test device, the companion test device and the auxiliary test device in the test circuit in the first aspect according to the driving signal, and obtaining the voltage and current of the main test device corresponding to the parameter to be tested; The parameters to be tested are determined according to the voltage and current of the main test device, wherein the parameters to be tested include switching parameters of the wafer and parameters of the reverse recovery process.

[0006] The present disclosure provides a dynamic parameter test circuit and test method for a wafer. When testing the dynamic parameters of the wafer, the different states of the selector and the accompanying test device provide more test configuration options, can accurately control the flow direction of the current signal, so that the test circuit can adapt to different types of main test devices and test requirements, and can quickly switch test conditions to improve the repeatability and test efficiency of the test. The setting of the energy storage module allows rapid release and recovery of energy, so that the test circuit can support complex tests, and improves the efficiency of the test in test scenarios where the main test device needs to be frequently switched. By controlling the precise path of the current signal, the error in the test process is reduced and the accuracy of the test results is improved. In addition, by accurately controlling the voltage and current, connecting the line between the wafer carrier of the main test device and the energy storage module, the dynamic parameters of the wafer can also be tested, which significantly reduces the influence of stray inductance in the test circuit, and can effectively avoid excessive voltage or current shocks to the main test device, thereby protecting the main test device from damage and ensuring the safety of the main test device. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 A schematic diagram of a standard double pulse test circuit for dynamic parameter testing of a wafer; Figure 2This is a working principle diagram of a double-pulse dynamic parameter test; Figure 3 It is a typical waveform diagram of a switch parameter test; Figure 4 A schematic diagram of the module composition of a dynamic parameter test circuit for a wafer provided by the present disclosure; Figure 5 A schematic diagram of the composition of a main test device and an auxiliary test device provided by the present disclosure; Figure 6 A schematic diagram of an integration method of a main test device and an auxiliary test device provided by the present disclosure; Figure 7 A schematic diagram of another main test device and an auxiliary test device provided by the present disclosure; Figure 8 A schematic diagram of another integration method of a main test device and an auxiliary test device provided by the present disclosure; Fig. 9 A schematic diagram of the composition of another main test device and an auxiliary test device provided by the present disclosure; Fig.10 A schematic diagram of another integration method of a main test device and an auxiliary test device provided by the present disclosure; Fig.11 A schematic diagram of the composition of a companion test device provided by the present disclosure; Fig.12 A schematic diagram of another test device provided by the present invention; Fig.13 A schematic diagram of the composition of a power module, an energy storage module, a test module, a controller and a router provided by the present disclosure; Fig.14 A schematic diagram of current signal flow direction for a switch parameter test in which both the main test device and the accompanying test device are MOS tubes provided by the present disclosure; Fig.15 A schematic diagram of current signal flow direction for another switch parameter test of a MOS tube in which both the main test device and the accompanying test device provided by the present disclosure are MOS tubes; Fig.16 A switch parameter test waveform diagram provided by the present disclosure; Fig.17 A schematic diagram of current signal flow direction for parameter testing of a reverse recovery process of a MOS tube in which both the main test device and the accompanying test device provided by the present disclosure are MOS tubes; Fig.18 A schematic diagram of current signal flow direction for parameter testing of a reverse recovery process of a MOS tube in which both the main test device and the accompanying test device provided by the present invention are MOS tubes; Fig.19 A parameter test waveform diagram of a reverse recovery process provided by the present disclosure; Fig. 20 A schematic diagram of current signal flow direction for parameter testing in a reverse recovery process in which a main test device is a diode and a companion test device is a MOS tube provided by the present disclosure; Fig.21 A schematic diagram of current signal flow direction for parameter testing in a reverse recovery process in which another main test device is a diode and a companion test device is a MOS tube provided by the present invention; Fig. 22 A schematic diagram of current signal flow direction for parameter testing of a reverse recovery process in which a main test device is a diode, a companion test device is a MOS tube, and a constant current device is provided in the present disclosure; Fig.23 A schematic diagram of current signal flow direction of a parameter test of a reverse recovery process in which a main test device is a diode, a companion test device is a MOS tube, and a second power supply module is provided in the present disclosure; Fig.24 Another current signal flow diagram of a parameter test of a reverse recovery process in which a main test device is a diode, a companion test device is a MOS tube, and a second power supply module is provided in the present disclosure; Fig.25 A schematic diagram of current signal flow direction for a switch parameter test in which a main test device is an insulated gate bipolar transistor and a companion test device is a diode provided by the present disclosure; Fig.26 Another current signal flow diagram for a switch parameter test in which the main test device is an insulated gate bipolar transistor and the accompanying test device is a diode provided by the present disclosure; Fig. 27 A connection diagram of a sampling resistor provided by the present invention. DETAILED DESCRIPTION

[0007] In order to more clearly illustrate the technical solutions in the present disclosure or the prior art, the technical solutions in the present disclosure will be clearly and completely described below in conjunction with the drawings in the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0008] The terms "first" and "second" in this disclosure are used for descriptive purposes only and are used only to distinguish one entity or operation from another entity or operation. They do not necessarily require or imply any actual relationship or order between these entities or operations, nor can they be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features.

[0009] See also Figure 1 , which shows a schematic diagram of a standard double-pulse test circuit for dynamic parameter testing of a wafer, wherein K1 is a first switch, K2 is a second switch, C1 is a capacitor array arranged in parallel, L1 is a freewheeling inductor, RS is a sampling resistor, a first transistor Q1 is a main test device, and a switching transistor Q3 is a companion test device. The gate (Gate) of the first transistor Q1 controls the first transistor Q1 to be in different states, i.e., an on state or an off state, by responding to a pulse signal from an external controller. The drain (Drain) of the first transistor Q1 constitutes a semiconductor substrate, which is connected to the source (Source) of the switching transistor Q3 through a wafer carrier and a cable. The source of the first transistor Q1 is connected to the second end of the capacitor array C1 through the sampling resistor RS. A special probe can be designed for this connection to minimize the distance from the probe to the second end of the capacitor array C1 to reduce stray inductance. The freewheeling inductor L1 and the switching transistor Q3 are arranged in parallel, the first end of the switching transistor Q3 and the first end of the freewheeling inductor L1 are connected to the first end of the capacitor array C1 through the first switch K1, the second end of the freewheeling inductor L1 and the second end of the switching transistor Q3 are connected to the wafer carrier, and the sampling resistor RS is connected to the source of the first transistor Q1 through a probe.

[0010] Combination Figure 1 The test circuit shown is shown in Figure 2 , which shows a working principle diagram of a dual pulse dynamic parameter test. Specifically, the dynamic parameter test of the wafer includes at least a switch parameter test, a diode reverse recovery process parameter test, and a short circuit parameter test. The present disclosure takes the test of the switch parameter and the diode reverse recovery process parameter as an example. It can be understood that the dynamic parameter test of the wafer is the dynamic parameter test of the main test device. Figure 1 In the test circuit shown in the figure, the switch parameter test is to apply two short pulse signals to the first transistor Q1 to simulate the fast switching process of the main test device in the actual circuit, and at the same time use the high-speed oscilloscope G2 to monitor and record the key dynamic parameters of the main test device in the switching process, such as Figure 3 The turn-on delay time Ton, turn-off delay time Toff, rise time Tr, fall time Tf, turn-on time Tdon and turn-off time Tdoff are shown to evaluate the dynamic performance of the switching performance and transient behavior of the main test device.

[0011] The present disclosure takes a MOS tube as an example of a main test device. The MOS tube can be Si-MOS or SiC-MOS. Its state includes an on state and an off state. Applying two short pulse signals is a gate voltage pulse. Figure 2In the test circuit shown, the first switch K1 is closed and the second switch K2 is open. The switch transistor Q3 is generally selected from the same MOS tube as the first transistor Q1 and both have built-in body diodes. In this test circuit, the switch transistor Q3 is always in the off state, and only the parasitic anti-parallel body diode inside it is used as a freewheeling diode. The Power-IGBT is a protection switch. When the first transistor Q1 is in an abnormal state such as a short circuit, the entire main current loop is promptly shut down to avoid accidents such as tube explosion. A high-speed oscilloscope G2 with at least 3 channels monitors the gate-source voltage (VGS), drain-source voltage (VDS) and drain-source current (IDS) of the first transistor Q1 during the test.

[0012] Before testing the switching parameters of the wafer, charge the capacitor array C1 to the rated voltage. Figure 2 The test circuit shown in the figure provides energy. A high-level pulse, namely the first pulse, which can also be called the turn-on pulse, is applied to the gate of the MOS tube through an external power supply, so that it is quickly turned on from the cut-off state, and the conduction duration is T1. Figure 3 As shown, at this time, a conductive channel is formed between the drain and source of the MOS tube, and the current begins to flow through the first transistor Q1. After the first transistor Q1 is turned on, the gate voltage is maintained so that the current flows between the drain and the source, simulating the behavior of the first transistor Q1 in the on state. After a certain period of time, the gate voltage is reduced, that is, a second pulse is applied, which can also be called a turn-off pulse. The turn-off duration is T2, so that the first transistor Q1 is quickly turned off from the on state, and the current flows through the body diode or other freewheeling path built into the first transistor Q1. The gate voltage is suddenly increased, and the turn-on duration of the first transistor Q1 is T3. At the end of the T1 and T3 stages, it can be used to test the transient process of the first transistor Q1 turning off and its dynamic parameters. At the end of the T2 stage, it can be used to test the transient process of the first transistor Q1 turning on and its dynamic parameters.

[0013] During the entire test process, a high-speed oscilloscope G2 was used to monitor the Figure 3 The gate-source voltage (VGS) and drain-source current (IDS) shown in the figure are used to measure the switching parameters of the first transistor Q1. By analyzing the waveform captured by the high-speed oscilloscope G2, the transient behavior of the first transistor Q1 during the switching process can be obtained, including the rate of change of voltage and current as well as voltage spikes and oscillations.

[0014] In some examples, the parameters of the diode reverse recovery process are tested by first forward-conducting the body diode built into the first transistor Q1, then suddenly cutting off the current and applying a reverse voltage within a specified time, and measuring the reverse recovery time Trr, reverse recovery current Irr, and reverse recovery charge Qrr required for the body diode to recover from the forward conduction state to the reverse blocking state. These parameters characterize the dynamic characteristics and efficiency of the body diode in fast switching applications. Specifically, combined with Figure 2 The test schematic diagram shown and Figure 3 As shown in the switching parameter test waveform diagram, during the test process, the first transistor Q1 is always in the cut-off state, and the test process is controlled by the switching pulse of the switching transistor Q3.

[0015] For the above example, in detail, the test process of the parameters of the diode reverse recovery process is: energy is stored on the capacitor array C1 to the rated voltage, the gate-source voltage (VGS) of the switching transistor Q3 suddenly increases, the switching transistor Q3 is turned on for a duration of T1, and the current signal in the test circuit flows to the switching transistor Q3, the freewheeling inductor L1, and the second switch K2. The current slope rises to ID At point ID1, the reverse voltage drain-source voltage (VDS) is added to the body diode of the first transistor Q1; the gate-source voltage (VGS) of the switching transistor Q3 suddenly drops, and the switching transistor Q3 is suddenly turned off. At this time, the current signal in the test circuit flows to the body diode in the first transistor Q1, the freewheeling inductor L1, and the second switch K2, and the duration is T2; the gate-source voltage (VGS) of the switching transistor Q3 suddenly increases, and the switching transistor Q3 is turned on for a duration of T3. The current signal in the test circuit flows to the switching transistor Q3, the freewheeling inductor L1, and the second switch K2, and the current slope rises from slightly lower than ID1 to ID2; then, the gate-source voltage (VGS) of the switching transistor Q3 becomes low, and the current signal in the test circuit flows to the first transistor Q1, the freewheeling inductor L1, and the second switch K2, and the current slope gradually decreases to 0; finally, the Power-IGBT is turned off and the test is completed. At the end of the T2 phase, the parameters of the reverse recovery process of the built-in body diode of the first transistor Q1, such as the reverse recovery time Trr, the reverse recovery current Irr and the reverse recovery charge Qrr, can be tested, and the rate of current change can be controlled by controlling the turn-off speed of the switching transistor Q3.

[0016] In the present disclosure, for wafer testing equipment, a wafer stage refers to a mechanical component used to fix and move wafers. It usually refers to a part that can clamp the wafer, and may include a vacuum suction cup or other types of clamping structures to ensure that the wafer is stably fixed on the wafer stage during the test. In some examples, the wafer stage is movable, for example, translational or rotational, so that different positions on the wafer can be sent to the test area in sequence. This design enables the test equipment to test multiple chip units (Die) on the wafer within one test cycle. Therefore, if Figure 1 The wafer stage in the test circuit shown in is a moving part, so the cable cannot be shortened directly. Therefore, the test circuit between the wafer stage and the cable is difficult to optimize and the stray inductance in the test circuit far exceeds the test requirements. This is because the parasitic inductance in the test circuit is large, which generates voltage spikes, causing serious oscillations in the drive waveform, further affecting the performance of the power semiconductor device, making the waveform data inaccurate, and making the dynamic parameter test of the wafer more difficult. In addition, it will cause overvoltage damage to the power semiconductor device and cause safety hazards.

[0017] Based on this, the present disclosure provides a test circuit for dynamic parameters in the test phase between photolithography and packaging during wafer manufacturing, which is used to test the dynamic parameters of multiple MOS tubes without electrodes on the wafer. The MOS tubes are arranged in a common drain configuration, so that the test circuit can effectively evaluate the performance of the MOS tubes under actual working conditions and provide important electrical characteristic data for subsequent packaging and application. Figure 4 , which shows a schematic diagram of the module composition of a dynamic parameter test circuit 10 of a wafer provided by the present disclosure, wherein the test circuit 10 includes: a power module 11, a path selector 12, an energy storage module 13, a companion test device 14, a test module 15, a main test device 16, an auxiliary test device 17 and a wafer stage 18, wherein the power module 11 is used to provide a current signal for the test circuit; the energy storage module 13 is used to store the current signal; the path selector 12 is used to transmit the current signal to the main test device 16 and / or the auxiliary test device 17 via the energy storage module 13 and the wafer stage 18 The auxiliary test device 17 or the current signal is transmitted to the main test device 16 via the auxiliary test device 17 and the energy storage module 13; the accompanying test device 14 is connected between the auxiliary test device 17 and the power module 11, and is used to assist in conducting the current signal provided by the power module 11 when testing dynamic parameters to complete the test of the main test device 16; the wafer carrier 18 is used to fix the main test device 16 and transmit the current signal provided by the power module 11; the test module 15 is used to obtain the voltage and current of the main test device 16 to determine the test result according to the voltage and current. According to the description of the above scheme, when testing the dynamic parameters of the wafer, the different states of the selector 12 and the accompanying test device 14 provide more test configuration options, which can accurately control the flow direction of the current signal, so that the test circuit 10 can adapt to different types of main test devices 16 and test requirements, and can quickly switch test conditions to improve the repeatability and test efficiency of the test. The setting of the energy storage module 13 allows for rapid release and recovery of energy, so that the test circuit 10 can support complex tests, and improve the efficiency of the test in test scenarios where the main test device 16 needs to be frequently switched. By controlling the precise path of the current signal, the error in the test process is reduced and the accuracy of the test results is improved. In addition, by accurately controlling the voltage and current, the connection line between the energy storage module 13 and the wafer carrier 18 of the main test device 16 can also be used to test the dynamic parameters of the wafer, significantly reducing the influence of stray inductance in the test circuit 10, and effectively avoiding excessive voltage or current shocks to the main test device 16, thereby protecting the main test device 16 from damage and ensuring the safety of the main test device 16.

[0018] In some examples, the main test device 16 and the auxiliary test device 17 are adjacent to and arranged in series, a plurality of auxiliary test devices 17 are arranged in parallel, and the main test device 16 and the auxiliary test device 17 are integrated on the same semiconductor substrate.

[0019] For example, when there is one auxiliary test device 17, the auxiliary test device 17 is set in series with the main test device 16. When there are multiple auxiliary test devices 17, the multiple auxiliary test devices 17 are first set in parallel, and then the multiple auxiliary test devices 17 connected in parallel are connected in series with the main test device 16.

[0020] For some examples, see Figure 5 The main test device 16 may include a first transistor Q1, wherein the first end of the first transistor Q1 is connected to the second end of the power module 11, the second end is connected to the wafer stage 18, and the first control end is used to control the first transistor Q1 to enter an on state or an off state; the auxiliary test device 17 may include a second transistor Q2, wherein the first end of the second transistor Q2 is connected to the first end of the accompanying test device 14, the second end is connected to the wafer stage 18, and the second control end is used to control the second transistor Q2 to enter a continuously on state.

[0021] For the above example, the main test device 16 and the auxiliary test device 17 are integrated on the same semiconductor substrate, such as Figure 6As shown, the main test device 16 is a first transistor Q1, and the auxiliary test device 17 is a second transistor Q2. The drains of the first transistor Q1 and the second transistor Q2 are integrated on the same semiconductor substrate, which can serve as part of the transistor drain and has good conductivity. The drain current can flow through the semiconductor substrate.

[0022] In some examples, for dynamic parameter testing of wafers, both the tested die and the auxiliary die need to be contacted by the probe at the same time. Since each adjacent chip unit die in the wafer needs to be tested, each die will be probed once as the tested die and the auxiliary die. In order to ensure the reliability of the pressure welding process, it is generally not desirable to have too many needle marks on the wafer, so the number of probes should be reduced as much as possible, preferably only once for each die.

[0023] Based on this, for Figure 5 and Figure 6 The selection of the first transistor Q1 and its adjacent MOS tube, i.e., the second transistor Q2, shown in , in some possible implementations, the first transistor Q1 is used as the die to be tested, and the second transistor Q2 is used as the auxiliary die, and the needle positions of the die to be tested and the auxiliary die are set to be exactly the same, so that each repeated needle insertion will be at the same position, and no needle marks will be added. In some examples, two auxiliary dies are selected at the adjacent position of the die to be tested, and one can be selected on each of the left and right sides of the die to be tested, or one can be selected on each of the upper and lower sides of the die to be tested. In this implementation, the wafer is tested once, and each die is needled 3 times. In some examples, three to four auxiliary dies can also be selected at the adjacent position of the die to be tested, and one auxiliary die can be selected on each of the upper, lower, left and right sides of the die to be tested, and the main circuit of the auxiliary die is connected in parallel, so that as long as any one of the three to four auxiliary dies can be turned on normally, the dynamic parameters of the die to be tested can be tested normally, and the three to four auxiliary dies and the probe circuit of the die to be tested can form a good surround, which can reduce the stray inductance again. In this case, the wafer is tested once and each die is pierced with needles 4 to 5 times.

[0024] In some possible implementations, in order to increase the complexity of the probe card design, the tested die and the auxiliary die can be interchanged during the same needle piercing process, and two dies are tested at a time, and the two dies are adjacent particles. For example, multiple dies are selected for dynamic testing together, and multiple dies can be auxiliary dies to each other during the test process. Taking the example of selecting four auxiliary dies from the upper left, upper right, lower left, and lower right of the tested die for dynamic testing together, the four auxiliary dies are arranged in a grid pattern to form a dynamic test circuit. For the first test, the needle is not lifted, and the circuit is switched on the probe card. The test of other dies is carried out in the same way. In this way, the needle can be pierced once, the wafer stage 18 moves once, and all four dies are tested for dynamic parameters. Among the four auxiliary dies, as long as any two are qualified dies, the dynamic parameters can be tested without omission. At the edge of the wafer, most of the dies can also be tested normally. In this way, not only are there fewer needle piercings, but the wafer stage 18 moves less times, which can improve the test efficiency.

[0025] For some examples, see Figure 7 The main test device 16 may include a first diode D1, wherein a first end of the first diode D1 is connected to a second end of the power module 11, and a second end is connected to the wafer stage 18. The auxiliary test device 17 may include a second diode D2, wherein a first end of the second diode D2 is connected to a first end of the accompanying test device 14, and a second end is connected to the wafer stage 18.

[0026] Combination Figure 7 , see Figure 8 , which shows a schematic diagram of another main test device and auxiliary test device integration method provided by the present disclosure, wherein the cathodes (negative electrodes) of the first diode D1 and the second diode D2 are integrated on the same semiconductor substrate to form a common cathode connection point. This integration method allows multiple diodes to share a common current path, while the anodes are respectively connected to their respective pins or contacts, wherein the semiconductor substrate can serve as a part of the cathode of the diode and has good conductivity, and the current signal can flow through the semiconductor substrate.

[0027] For some examples, see Fig. 9 The main test device 16 may include a first insulated gate bipolar transistor IG1, wherein the first end of the first insulated gate bipolar transistor IG1 is connected to the second end of the power module 11, the second end is connected to the wafer carrier 18, and the first control end is used to control the first insulated gate bipolar transistor IG1 to enter an on state or an off state; the auxiliary test device 17 may include a second insulated gate bipolar transistor IG2, the first end of the second insulated gate bipolar transistor IG2 is connected to the second end of the accompanying test device 14, the second end is connected to the wafer carrier 18, and the second control end is used to control the second insulated gate bipolar transistor IG2 to enter a continuously on state or an off state.

[0028] Combination Fig. 9 , see Fig.10 , which shows a schematic diagram of another main test device and auxiliary test device integration method provided by the present disclosure, wherein the collectors (C poles) of the first insulated gate bipolar transistor IG1 and the second insulated gate bipolar transistor IG2 are integrated on the same semiconductor substrate to form a common collector connection point. This integration method allows multiple IGBT transistors to share a common current path, while the emitters (E poles) and gates (G poles) are respectively connected to their respective pins or contacts, wherein the semiconductor substrate can serve as a part of the collector of the IGBT transistor and has good conductivity, and the current signal can flow through the semiconductor substrate.

[0029] For some examples, see Fig.11 The accompanying test device 14 may include a switching transistor Q3, wherein a first end of the switching transistor Q3 is connected to a first end of the auxiliary test device 17, a second end is connected to a first end of the power module 11, and a third control end is used to control the switching transistor Q3 to enter an on state or an off state.

[0030] For some examples, see Fig.12 The companion test device 14 may include a third diode D3 , wherein a first end of the third diode D3 is connected to a first end of the power module 11 , and a second end of the third diode D3 is connected to a first end of the auxiliary test device 17 .

[0031] For some examples, see Fig.13 , which shows a schematic diagram of the composition of a power module 11, an energy storage module 13, a test module 15, a controller and a path selector 12 provided by the present disclosure, wherein: In some examples, the power module 11 may include a capacitor array C1 arranged in parallel, wherein a first end of the capacitor array C1 is connected to the energy storage module 13 through the path selector 12 , and a second end of the capacitor array C1 is connected to the main test device 16 .

[0032] Exemplarily, the power module 11 may also include a power management circuit, a pulse generator or a battery simulator.

[0033] In some examples, the first end of the energy storage module 13 is connected to the first end or the second end of the power module 11 , and the second end of the energy storage module 13 is connected to the wafer stage 18 for storing the current signal provided by the power module 11 or discharging to the main test device 16 .

[0034] Exemplarily, the energy storage module 13 may include a freewheeling inductor L1 .

[0035] In some examples, the test module 15 may include a high-speed oscilloscope G2 for measuring the voltage and current of the main test device 16 .

[0036] It should be noted that if Figure 5 and Fig.11 As shown, specifically, the first transistor Q1, the second transistor Q2 and the switch transistor Q3 can be transistors of the same type, and can be N-channel transistors or P-channel transistors. The first end is the source of the transistor, the second end is the drain of the transistor, and the control end is the gate of the transistor, which is in an on state and an off state. The conversion of the on state and the off state of the N-channel transistor and the P-channel transistor is controlled by the controller changing the gate voltage relative to the source voltage. Specifically, a high level or low level driving signal is applied to the first control end, the second control end and the third control end respectively by the first controller, the second controller and the third controller to control the first transistor Q1, the second transistor Q2 and the switch transistor Q3 to be in an on state or an off state.

[0037] The present disclosure takes the first transistor Q1 as an example to specifically explain the control principle of controlling the on state or off state of the first transistor Q1 by the first controller. The first transistor Q1 is an N-channel transistor, and its control principle is: when the gate-source voltage (VGS) of the first transistor Q1 is greater than or equal to the threshold voltage (Vth), that is, when the first controller outputs a high-level drive signal, the first transistor Q1 is in the on state. Specifically, the first controller provides sufficient positive voltage to the gate of the first transistor Q1, so that VGS ≥ Vth, and there is sufficient positive voltage between the gate and the source to form a conductive channel, allowing the current signal to flow from the source to the drain, thereby turning on the first transistor Q1. When the gate-source voltage (VGS) is less than the threshold voltage (Vth), that is, when the first controller outputs a low-level drive signal, the first transistor Q1 enters the off state, at which time there is not enough voltage to form a conductive channel, so no current signal can flow from the source to the drain. The first controller keeps the gate voltage at a value lower than Vth, thereby turning off the first transistor Q1.

[0038] Exemplarily, the first transistor Q1 is a P-channel transistor, and its control principle is: when the gate-source voltage (VGS) of the first transistor Q1 is less than or equal to a negative threshold voltage (-Vth), that is, when the first controller outputs a high-level drive signal, the first transistor Q1 is turned on. Specifically, the first controller provides enough negative voltage to the gate so that VGS≤-Vth, and there is enough negative voltage between the gate and the source to form a conductive channel, allowing the current signal to flow from the source to the drain, thereby turning on the first transistor Q1. When the gate-source voltage (VGS) is greater than the negative threshold voltage (-Vth), that is, when the first controller outputs a low-level drive signal, the first transistor Q1 enters the cut-off state, at which time there is not enough negative voltage to form a conductive channel, so no current signal can flow from the source to the drain. The first controller keeps the gate voltage at a value higher than -Vth, thereby turning off the first transistor Q1.

[0039] In some examples, the first controller, the second controller, and the third controller may include a microcontroller, a transistor driving circuit, an operational amplifier, or other electronic circuits, and provide appropriate voltage signals as needed to control the on and off states of the transistors. This control method enables the transistors to be used as switches in digital circuits and as amplifiers or switches in analog circuits.

[0040] In some examples, the selector 12 may include a first switch K1 and a second switch K2, whose states include a closed state and an open state. The first switch K1 and the second switch K2 are arranged in parallel, and only one of the first switch K1 and the second switch K2 is in a closed state.

[0041] In some examples, the first switch K1 can be used to transmit the current signal provided by the power module 11 back to the power module 11 via the energy storage module 13, the wafer stage 18, and the main test device 16 in sequence, or to transmit the current signal provided by the power module 11 back to the power module via the energy storage module 13, the wafer stage 18, the auxiliary test device 17, and the companion test device 14 in sequence.

[0042] The second switch K2 can be used to transmit the current signal provided by the power module 11 back to the power module 11 via the auxiliary test device 17, the wafer carrier 18 and the energy storage module 13 in sequence, or to transmit the current signal provided by the power module 11 back to the power module 11 via the main test device 16, the wafer carrier 18 and the energy storage module 13 in sequence.

[0043] Optionally, the switch parameter of the wafer may include a first switch parameter and a second switch parameter. When testing the first switch parameter of the main test device 16, the first switch K1 is in a closed state, and the first switch K1 can be used to transmit the current signal provided by the power module 11 back to the power module 11 via the energy storage module 13, the wafer stage 18, and the main test device 16 in sequence. When testing the second switch parameter of the main test device 16, the first switch K1 can also be used to transmit the current signal provided by the power module 11 back to the power module 11 via the energy storage module 13, the wafer stage 18, the auxiliary test device 17, and the accompanying test device 14 in sequence.

[0044] Optionally, the parameter test of the reverse recovery process of the wafer may include a first stage and a second stage, namely, a charging stage of the energy storage module 13 and a discharging stage of the energy storage module 13. In the first stage of testing the parameters of the reverse recovery process of the main test device 16, the second switch K2 is in a closed state, and the second switch K2 can be used to transmit the current signal provided by the power module 11 back to the power module 11 via the auxiliary test device 17, the wafer stage 18 and the energy storage module 13 in sequence. In the second stage of testing the parameters of the reverse recovery process of the main test device 16, the second switch K2 can also be used to transmit the current signal provided by the power module 11 back to the power module 11 via the main test device 16, the wafer stage 18, and the energy storage module 13 in sequence.

[0045] The following example is taken as follows: the main test device 16 is the first transistor Q1, the auxiliary test device 17 is the second transistor Q2, and the accompanying test device 14 is the switching transistor Q3, and the first transistor Q1, the second transistor Q2, and the switching transistor Q3 are N-channel transistors, and the number of the second transistor Q2 is one.

[0046] Combination Figure 4 In the test circuit 10 shown, in some examples, when testing the first switch parameter of the main test device 16, the first switch K1 is closed, the main test device 16 is in the on state, the auxiliary test device 17 is in the on state, and the companion test device 14 is in the off state, so that the current signal provided by the first end of the power module 11 is transmitted back to the second end of the power module 11 via the energy storage module 13, the cable, the wafer carrier 18 and the main test device 16 in sequence.

[0047] For the above examples, see Fig.14 , which shows a current signal flow diagram of a switch parameter test of a main test device 16 and a companion test device 14 provided by the present disclosure, where both the main test device 16 and the companion test device 14 are MOS tubes. In the present disclosure, Fig.14As shown in , when testing the first switch parameter of the main test device 16, the second controller outputs a high-level drive signal to control at least one second transistor Q2 to be in a continuous on state, and the first controller outputs a high-level drive signal to control the first transistor Q1 to be in an on state. At this time, the current can flow freely in both directions, providing a feasible method for using adjacent chip units, i.e., at least one second transistor Q2, to assist in testing the switch parameters. The third controller outputs a low-level drive signal to control the switch transistor Q3 to be in an off state, thus forming a test circuit 10 for testing the switch parameters of the wafer. Fig.14 The arrows of the test circuit 10 shown describe the Fig.16 The current signal provided by the first end of the power module 11 is transmitted from the energy storage module 13, the cable, the wafer stage 18 and the first transistor Q1 back to the second end of the power module 11. Fig.14 In fact, the power module 11 discharges to the energy storage module 13, and the current slope of the energy storage module 13 rises from 0 to the set current limit value I1 in the T1 stage. At this time, the gate-source voltage, drain-source voltage of the first transistor Q1 and the current value in the test circuit are tested using a high-speed oscilloscope G2, an ammeter or a voltmeter.

[0048] In some examples, when testing the second switch parameter of the main test device 16, the first switch K1 is closed, the main test device 16 is in the off state, the auxiliary test device 17 is in the on state, and the accompanying test device 14 is in the off state, so that the current signal provided by the first end of the power supply module 11 is transmitted back to the first end of the power supply module 11 via the energy storage module 13, the cable, the wafer carrier 18, the auxiliary test device 17 and the accompanying test device 14 in sequence.

[0049] For the above examples, see Fig.15 , which shows another current signal flow diagram of a switch parameter test of a main test device 16 and a companion test device 14 provided by the present disclosure, in which both the main test device 16 and the companion test device 14 are MOS tubes. When testing the second switch parameter of the main test device 16, as shown in FIG. Fig.15 The arrows in the figure describe the Fig.16 At this time, the first switch K1 is closed, and the first controller and the third controller respectively output low-level drive signals to control the first transistor Q1 and the switching transistor Q3 to be in the off state, and the second controller outputs a high-level drive signal to control the second transistor Q2 to be in the continuous on state, and the current signal provided by the first end of the power module 11 is transmitted from the energy storage module 13, the cable, the wafer stage 18, the second transistor Q2 and the switching transistor Q3 back to the first end of the power module 11.

[0050] exist Fig.15In the process, the energy storage module 13 is actually discharging, and the current on the energy storage module 13 remains basically unchanged in the T2 stage.

[0051] In some examples, Fig.16 In the T3 phase, the current signal of the test circuit 10 flows into Fig.14 At this time, the current in the test circuit 10 does not start from 0, but starts from the set current limit value I1 and increases to I2. After the T3 stage ends, it enters the Fig.15 As shown in the arrow direction, the first transistor Q1 enters the cut-off state, and the current on the energy storage module 13 slowly decreases to 0.

[0052] It should be noted that, through Fig.14 and Fig.15 After obtaining the first switch parameter and the second switch parameter, the test circuit 10 performs data verification to ensure that there are no errors or abnormal values. According to the test requirements and standards, the final switch parameter is obtained based on the first switch parameter and the second switch parameter, for example, by calculating statistical parameters such as average value, maximum value, minimum value, etc.

[0053] Based on the above examples, Figure 3 and Fig.16 From the waveform diagram of the switching parameters of the main test device 16 shown, it can be seen that: Fig.16 Compare Figure 3 The drain-source voltage on the first transistor Q1 and the current on the freewheeling inductor L1 are added to more clearly describe the change process of voltage and current, but the switching parameters such as the turn-on delay time Ton, the turn-off delay time Toff, the rise time Tr, the fall time Tf, the turn-on time Tdon and the turn-off time Tdoff are not described, wherein VGS is the change of the gate-source voltage of the first transistor Q1 tested by the high-speed oscilloscope G2 in the test module 15; IDS is the change of the drain-source current of the first transistor Q1 tested by the high-speed oscilloscope G2 in the test module 15; VDS is the change of the drain-source voltage of the first transistor Q1 tested by the high-speed oscilloscope G2 in the test module 15; L1 (CURRENT) is the estimated waveform of the current change flowing through the freewheeling inductor L1.

[0054] Based on the above description, Fig.14 and Fig.15The path of the current signal flow of the switch parameter test shown by the arrow in the middle, the non-overlapping part of the current loop through which the main current flows in the test circuit 10 has been greatly reduced. In the present disclosure, although the circuit of the wafer stage 18 and the cable connection part is retained, the current signal mainly flows directly between the auxiliary test device 17 and the accompanying test device 14, and the cable connection part is only used to connect the current loop with the energy storage module 13, and therefore bears a smaller part of the sudden change current, thereby reducing the stray inductance effect of the cable on the whole. Therefore, the test circuit 10 can greatly reduce the stray inductance effect of the test circuit.

[0055] It should be noted that the switch transistor Q3 in the above test circuit 10 is always in the off state, and only the parasitic anti-parallel body diode inside it is used as a freewheeling diode. The body diode can also be called a parasitic diode, which is naturally formed due to the manufacturing process of the MOS tube. It is located between the drain and the substrate of the MOS tube and is a parasitic element inside the MOS tube. In an N-channel transistor, the body diode is formed by a PN junction between the source and the drain, while in a P-channel transistor, the body diode is formed by a PN junction between the drain and the source. Its main function is to provide a current path from the drain to the source when the MOS tube is turned off. When the gate drive signal of the MOS tube is removed and the MOS tube is turned off, if there is a voltage between the drain and the source, the body diode will be turned on, allowing the current signal to flow from the drain to the source in the N-channel transistor, thereby protecting the MOS tube from the influence of voltage spikes. In switch applications, the body diode acts as a freewheeling diode to maintain the current continuity in the inductive circuit. When the MOS tube is turned off during the switching process, the energy stored in the inductor circuit will be released through the body diode to provide a circuit path to prevent the current from being suddenly interrupted and generating a high-level spike, thereby ensuring the continuity of the current in the test circuit, which is crucial for the accuracy of the test and the safety of the device. In some examples, a higher-speed diode can be connected in parallel to the switching transistor Q3 to replace the role of the body diode.

[0056] In some examples, in the first stage of testing the parameters of the reverse recovery process of the main test device 16, the second switch K2 is closed, the main test device 16 is in the off state, the auxiliary test device 17 is in the on state, and the companion test device 14 is in the on state, so that the current signal provided by the first end of the power module 11 is transmitted back to the second end of the power module 11 via the companion test device 14, the auxiliary test device 17, the wafer stage 18, the cable and the energy storage module 13 in sequence to charge the energy storage module 13.

[0057] For the above examples, specifically, see Fig.17 , which shows a current signal flow diagram of a parameter test of a reverse recovery process of a MOS tube in which both the main test device 16 and the accompanying test device 14 provided by the present disclosure are MOS tubes, such as Fig.17 As shown, the first transistor Q1, the second transistor Q2 and the switch transistor Q3 are all built with body diodes for freewheeling, and their dynamic parameters, i.e., the parameters of the reverse recovery process, need to be tested, mainly including the reverse recovery time Trr, the reverse recovery current Irr and the reverse recovery charge Qrr. It should be noted that Fig.17 With the aforementioned Fig.14 The difference is that the second switch K2 is closed, the first switch K1 is opened, the first controller outputs a low-level driving signal to control the first transistor Q1 to be in the off state, the second controller outputs a high-level driving signal to control at least one second transistor Q2 to be in the continuous on state, and the third controller outputs a high-level driving signal to control the switch transistor Q3 to be in the on state. Fig.17 The arrows shown in the figure describe the Fig.19 The flow direction of the current signal in the T1 phase, the current signal provided by the first end of the power module 11 is transmitted back to the second end of the power module 11 from the switching transistor Q3, the second transistor Q2, the wafer carrier 18, the cable and the energy storage module 13 to charge the energy storage module 13.

[0058] exist Fig.17 In fact, the power module 11 discharges to the energy storage module 13, that is, the energy storage module 13 is in the charging stage, so that the current slope on the energy storage module 13 rises from 0 to the set current limit value I1 in the T1 stage. The body diode in the first transistor Q1 is subjected to reverse voltage. At this time, the flow direction of the current signal does not pass through the main test device 16, so there is no need to test the gate-source voltage, drain-source voltage and current value in the test circuit of the main test device 16. Accordingly, the parameters in the reverse recovery process of the main test device 16 are not tested.

[0059] In some examples, in the second stage of testing the parameters of the reverse recovery process of the main test device 16, the energy storage module 13 is discharged, the second switch K2 is closed, the main test device 16 is in the off state, the auxiliary test device 17 is in the on state, and the companion test device 14 is in the off state, so that the current signal provided by the first end of the energy storage module 13 is transmitted back to the second end of the energy storage module 13 via the main test device 16, the wafer carrier 18 and the cable in sequence.

[0060] For the above examples, specifically, see Fig.18 , which shows another current signal flow diagram of a parameter test of a reverse recovery process of a MOS tube in which both the main test device 16 and the accompanying test device 14 provided by the present disclosure are tested. In the second stage of testing the parameters of the reverse recovery process of the main test device 16, that is, the discharge stage of the energy storage module 13, as shown in FIG. Fig.18 The arrows shown in the figure describe the Fig.19At this time, the second switch K2 is closed, and the first controller outputs a low-level drive signal to control the first transistor Q1 to be in the off state, the second controller outputs a high-level drive signal to control at least one second transistor Q2 to be in the continuous on state, and the third controller outputs a low-level drive signal to control the switch transistor Q3 to be in the off state. The current signal provided by the first end of the energy storage module 13 is transmitted from the first transistor Q1, the wafer stage 18, and the cable back to the second end of the energy storage module 13.

[0061] exist Fig.18 In fact, the energy storage module 13 is discharging, and the current on the energy storage module 13 remains basically unchanged in the T2 stage. At this time, the gate-source voltage, drain-source voltage of the first transistor Q1 and the current value in the test circuit are tested using a high-speed oscilloscope G2, an ammeter or a voltmeter.

[0062] In some examples, such as Fig.19 The T3 stage, and then enter Fig.17 The current signal flows in the direction indicated by the arrow. At this time, the current of the energy storage module 13 does not start from 0, but starts from the current limit value I1 and increases to I2. The current on the first transistor Q1, that is, the current conducted in the reverse direction through the diode, quickly drops from the current limit value I1 to 0; the voltage drop between the drain and source of the first transistor Q1 quickly changes from -0.7V (diode forward voltage drop) to a high level. Because the body diode of the first transistor Q1 has a reverse recovery characteristic, when a reverse voltage is applied instantaneously, the current will not drop directly from the current limit value I1 to 0, but there will be a reverse overshoot, the amplitude of which, that is, the reverse recovery current is Irr, and the time width of the overshoot, that is, the reverse recovery time is Trr. These parameters can be measured with a high-speed oscilloscope G2, and the condition of the current change rate di / dt is determined by the gate drive speed of the switching transistor Q3, where di / dt represents how fast the current i changes with time t.

[0063] like Fig.19 The waveform diagram of the parameters of the reverse recovery process of the main test device 16 shown in the figure shows that the reverse recovery characteristics of the diode can be tested at the moment when the T2 stage ends and the T3 stage begins, wherein VGS is the change in the gate-source voltage of the switching transistor Q3; IDS is the change in the drain-source current of the first transistor Q1 tested by the high-speed oscilloscope G2 in the test module 15; VDS is the change in the drain-source voltage of the first transistor Q1 tested by the high-speed oscilloscope G2 in the test module 15; and L1 (CURRENT) is the estimated waveform of the current change flowing through the energy storage module 13.

[0064] It should be noted that, through Fig.18The test circuit 10 shown by the middle arrow obtains the parameters of the reverse recovery process of the energy storage module 13 during the discharge phase, and then performs data verification to ensure that there are no errors or abnormal values. The final parameters of the reverse recovery process are obtained according to the test requirements and standards.

[0065] Based on the above description, Fig.17 and Fig.18 The path of the current signal shown in the figure, the current signal flow direction non-overlapping part in the test circuit 10 has been greatly reduced, the overlapping part includes the circuit of the wafer stage and the cable connection part, the cable is only used to connect to the current loop of the energy storage module, and the current mutation signal mainly flows directly between the auxiliary test device 17 and the accompanying test device 14, thereby reducing the impact of the cable stray inductance on the whole, and the stray inductance generated by other non-overlapping parts, for example, the inductance generated by the distance between two adjacent dies, can be reduced to meet the test requirements through wiring and space optimization. Therefore, the above test circuit 10 can greatly reduce the impact of stray inductance.

[0066] The following example is taken as follows: the main test device 16 is the first diode D1, the auxiliary test device 17 is the second diode D2, the accompanying test device 14 is the switch transistor Q3, and the switch transistor Q3 is an N-channel transistor, and the number of the second diode D2 is one.

[0067] In some examples, in the first stage of testing the parameters of the reverse recovery process of the main test device 16, the second switch K2 is closed, the companion test device 14 is in the on state, the main test device 16 is reverse biased, and the auxiliary test device 17 is forward biased, so that the current signal provided by the first end of the power module 11 is transmitted back to the second end of the power module 11 via the companion test device 14, the auxiliary test device 17, the wafer carrier 18, the cable and the energy storage module 13 in sequence to charge the energy storage module 13.

[0068] For the above examples, specifically, see Fig. 20 , which shows a current signal flow diagram of a parameter test of a reverse recovery process in which the main test device 16 is a diode and the auxiliary test device 14 is a MOS tube provided by the present disclosure. Since the diode is not a controllable semiconductor device, but can be in a unidirectional conduction state, the first diode D1 and the second diode D2 do not need to be controlled to be turned on. Fig. 20 As shown, taking the common cathode diode as an example, the wafer testing method of the common anode diode can also be deduced based on this principle, which will not be described in detail in this disclosure. Fig. 20 , the switching transistor Q3 has a built-in body diode for freewheeling. Fig. 20 With the aforementioned Fig.17 The difference is that the main test device 16 and the auxiliary test device 17 are both diodes, which can be unidirectionally conducted.

[0069] For example, in the first stage of testing the parameters of the reverse recovery process of the main test device 16, the second switch K2 is closed, and the third controller outputs a high-level driving signal to control the switch transistor Q3 to be in a continuous conduction state, the first diode D1 is reverse biased, and the second diode D2 is forward biased. Fig. 20 The arrows shown in the figure describe the Fig.19 The flow direction of the current signal in the T1 phase, the current signal provided by the first end of the power module 11 is transmitted back to the second end of the power module 11 from the switching transistor Q3, the second diode D2, the wafer carrier 18, the cable and the energy storage module 13 to charge the energy storage module 13.

[0070] exist Fig. 20 In fact, the power module 11 discharges to the energy storage module 13, so that the current slope of the energy storage module 13 rises from 0 to the set current limit value I1 in the T1 phase. The first diode D1 withstands the reverse voltage.

[0071] In some examples, in the second stage of testing the parameters of the reverse recovery process of the main test device 16, the discharge stage of the energy storage module 13, the second switch K2 is closed, the companion test device 14 is in the cut-off state, the main test device 16 is forward biased, and the auxiliary test device 17 is forward biased, so that the current signal provided by the first end of the energy storage module 13 is transmitted back to the second end of the energy storage module 13 via the main test device 16, the wafer carrier 18 and the cable in sequence.

[0072] For the above examples, see Fig.21 This is the discharge phase of the energy storage module 13, and the second phase of testing the parameters of the reverse recovery process of the main test device 16, such as Fig.21 The arrows shown in the figure describe the Fig.19 At this time, the second switch K2 is closed, the third controller outputs a low-level drive signal to control the switch transistor Q3 to be in the off state, the first diode D1 is forward biased, the second diode D2 is forward biased, and the current signal provided by the first end of the energy storage module 13 is transmitted back to the second end of the energy storage module 13 from the first diode D1, the wafer stage 18 and the cable.

[0073] exist Fig.21 In fact, the energy storage module 13 is discharging, and the current on the energy storage module 13 remains basically unchanged in the T2 stage. At this time, the voltage of the first diode D1 and the current value in the test circuit 10 are tested using a high-speed oscilloscope G2, an ammeter or a voltmeter.

[0074] In some examples, such as Fig.19 The T3 stage, and then enter Fig. 20The current signal flows in the direction shown by the arrow. At this time, the current of the energy storage module 13 does not start from 0, but starts from the current limit value I1 and increases to I2. The current on the first diode D1 quickly drops to 0 through the reverse conduction of the diode; the voltage drop of the first diode D1 quickly changes from the diode forward voltage drop of -0.7V to a high voltage. Because the main test device 16 is a diode, it has a reverse recovery characteristic. When the reverse voltage is applied instantaneously, the I1 current will not drop directly to 0, but there will be a reverse overshoot, whose amplitude, that is, the reverse recovery current is Irr, and the time width of the overshoot, that is, the reverse recovery time is Trr. These parameters can be measured with a high-speed oscilloscope G2. The condition of the current change rate di / dt is determined by the gate drive speed of the switching transistor Q3, where di / dt represents how fast the current i changes with time t. For other contents, please refer to the description of the above examples and will not be repeated here.

[0075] In some examples, the test circuit 10 may further include a constant current device for providing a constant direct current bias to the auxiliary test device 17 .

[0076] For example, the constant current device provides a constant DC current bias for the auxiliary test device 17. In some examples, the constant current device can be configured as a constant current source, and a simple current mirror circuit or operational amplifier feedback circuit can be used to keep the output current constant. By setting appropriate resistance and power supply voltage, the constant current device can provide a stable current at a specific operating point. In some examples, the constant current device can also be combined with other field effect transistors to form a current mirror circuit. By adjusting the reference current, the constant current device can copy the reference current, thereby providing a constant bias current for the auxiliary test device 17, so that the auxiliary test device 17 is always in the best state during the test process, wherein the reference current is determined by a known resistance and power supply voltage.

[0077] In some examples, the constant current device may include a constant current transistor Q4, wherein a first end of the constant current transistor Q4 is connected to a first end of the power module 11, and a second end is connected to a first end of the auxiliary test device 17, for replicating the current signal provided by the power module 11 and transmitting it to the first end of the auxiliary test device 17.

[0078] For the above example, the constant current transistor Q4 can be a field effect transistor (MOS), a bipolar transistor (BJT), a junction field effect transistor (JFET), a metal semiconductor field effect transistor (MESFET) and an insulated gate bipolar transistor (IGBT). In the present disclosure, the constant current transistor Q4 is taken as a MOS transistor as an example.

[0079] In some examples, in the first stage of testing the parameters of the reverse recovery process of the main test device 16, the second switch K1 is closed, the companion test device 14 is in the on state, the main test device 16 is reverse biased, and the auxiliary test device 17 is forward biased, so that the current signal provided by the first end of the power module 11 is transmitted back to the second end of the power module 11 via the companion test device 14, the auxiliary test device 17, the wafer stage 18, the cable and the energy storage module 13 in sequence, and the current signal provided by the first end of the power module 11 is transmitted back to the second end of the power module 11 via the constant current device, the auxiliary test device 17, the wafer stage 18, the cable and the energy storage module 13 in sequence.

[0080] For the above examples, see Fig. 22 , which shows a current signal flow diagram of a parameter test of a reverse recovery process in which the main test device 16 is a diode, the accompanying test device 14 is a MOS tube, and a constant current device is provided in the present disclosure, and compared with Fig. 22 and Fig. 20 It can be seen from the current path when testing the parameters of the reverse recovery process of the main test device 16 that, Fig. 20 The diode reverse recovery time wafer level test method is based on the consideration that the diode reverse recovery time is much longer than the forward conduction time, and the forward current response of the auxiliary test device 17, that is, the second diode D2, is an ideal condition. Fig.19 In the T2 stage, the cathode (common) is about -0.7V, the switching transistor Q3 is in the cut-off state, and the anode of the second diode D2 is equivalent to being suspended; Fig.19 In the T3 phase, the switch transistor Q3 is turned on instantaneously, and the anode of the second diode D2 suddenly changes to a high voltage.

[0081] In some examples, when the switch transistor Q3 is in the off state, the voltage drop of the second diode D2 is approximately 0 (the current is 0) and the current of the second diode D2 quickly becomes the current limit value I1, and its response speed will affect the parameter test of the reverse recovery process of the first diode D1. Fig. 22 In the case of Fig. 20 Same, such as Fig. 22 As shown by the black solid arrow in the figure, in the first stage of testing the parameters of the reverse recovery process of the main test device 16, the second switch K2 is closed, the third controller outputs a high-level signal to control the switching transistor Q3 to be in the on state, the first diode D1 is reverse biased, and the second diode D2 is forward biased, so that the current signal provided by the first end of the power module 11 is transmitted back to the second end of the power module 11 via the switching transistor Q3, the second diode D2, the wafer stage 18, the cable and the energy storage module 13 in sequence to charge the energy storage module 13.

[0082] In the present disclosure, a constant current branch is added to provide a DC current bias, i.e., Ibias, to the second diode D2 during the entire test cycle. Ibias is an intentionally introduced current used to set or maintain a specific operating point in the circuit to ensure that the transistor operates in a specific area, such as an amplification area, to achieve the desired circuit function. At this time, the current of the second diode D2 does not change from 0 to the current limit value I1, but changes from Ibias to Ibias+I1. The second diode D2 is continuously in forward bias, and its speed will be significantly improved, which has less impact on the parameter test of the reverse recovery process of the first diode D1. Fig. 22 The black solid arrow in the figure indicates the sudden change current loaded by the switch transistor Q3, and the black dotted arrow indicates that the constant current Ibias is added to the second diode D2 through the constant current transistor Q4, and the constant current Ibias does not pass through the first diode D1. Fig. 22 As shown by the black dotted arrow in FIG. 1 , the current signal provided by the first end of the power module 11 is transmitted back to the second end of the power module 11 via the constant current transistor Q4, the second diode D2, the wafer stage 18, the cable and the energy storage module 13 in sequence. Fig. 22 It can be seen that the addition of the constant current transistor Q4 has no other effect on the main test circuit, but only improves the response speed of the second diode D2. The current change rate condition di / dt is determined by the gate drive speed of the switching transistor Q3, where di / dt represents the speed at which the current i changes with time t. In the second stage of testing the parameters of the reverse recovery process of the main test device 16, see the above for details. Fig.21 The description and examples will not be repeated here.

[0083] It should be noted that for Fig. 22 The test circuit shown in is designed according to the standard reverse recovery test method. That is, the defined conditions are forward current I1, current change rate di / dt, and reverse voltage. The forward current I1 is controlled in the T1 stage, and di / dt is controlled by the gate drive speed of the switching transistor Q3. The reverse voltage can be set directly. In some examples, the conditional definition of the parameters of the reverse recovery process of the diode is different. For example, for low-voltage and low-current diodes, because the speed is faster, for example, less than 10nS, di / dt is not easy to accurately determine, so the defined conditions are often changed to forward current, reverse current, reverse bias voltage, and load resistance.

[0084] Based on this, in order to meet the defined conditions, such as forward current, reverse current, reverse bias, and load resistance, in some examples, the power supply module 11 includes a first power supply module C3 and a second power supply module C2, wherein the first power supply module C3 and the second power supply module C2 are arranged in parallel, and the first end of the first power supply module C3 is connected to the second end of the companion test device 14 through a first resistor, and the second end of the first power supply module C3 is connected to the first end of the main test device 16; the first end of the second power supply module C2 is connected to the first end of the auxiliary test device 17 through a second resistor, and the second end of the second power supply module C2 is connected to the first end of the main test device 16, for providing a bias current to the auxiliary test device 17.

[0085] For the above example, Fig.23 As shown, the power module 11 may include a first power module C3 and a second power module C2, wherein the first end of the first power module C3 is connected to the first end of the first resistor RL1, the second end of the first resistor RL1 is connected to the second end of the switch transistor Q3, and the second end of the first power module C3 is connected to the first end of the first diode D1. The first end of the second power module C2 is connected to the first end of the second resistor RL2, the second end of the second resistor RL2 is connected to the first end of the second diode D2, and the second end of the second power module C2 is connected to the first end of the first diode D1, wherein the first power module C3 is used to determine the reverse bias voltage; the second power module C2 and the second resistor RL2 are used to determine the bias current of the second diode D2; the first resistor RL1 is used to determine the forward current; the freewheeling inductor L1 is used to store energy, but because the T1 time is too small, the freewheeling inductor L1 is not used to determine the forward current.

[0086] In some examples, in the first stage of testing the parameters of the reverse recovery process of the main test device 16, the second switch K2 is closed, the companion test device 14 is in the on state, the main test device 16 is reverse biased, and the auxiliary test device 17 is forward biased, so that the current signal provided by the first end of the first power module C3 is transmitted back to the second end of the first power module C3 via the companion test device 14, the auxiliary test device 17, the wafer stage 18, the cable and the energy storage module 13 in sequence to charge the energy storage module 13; and the current signal provided by the first end of the second power module C2 is transmitted back to the second end of the second power module via the auxiliary test device 17, the wafer stage 18, the cable and the energy storage module 13.

[0087] For the above example, compare Fig.23 and Fig. 20 It can be seen from the current path when testing the parameters of the reverse recovery process of the main test device 16 that Fig.23In the embodiment, a current path is added to determine the bias current of the second diode D2. The second switch K2 is closed, the third controller controls the switch transistor Q3 to be in the on state, the first diode D1 is reverse biased, and the second diode D2 is forward biased. In the first stage of testing the parameters of the reverse recovery process of the main test device 16, that is, the charging stage of the energy storage module 13, as shown in FIG. Fig.23 shown Fig.19 The flow direction of the current signal in the T1 phase is to transmit the current signal provided by the first end of the first power module C3 back to the second end of the first power module C3 via the first resistor RL1, the switching transistor Q3, the second diode D2, the wafer stage 18, the cable and the energy storage module 13 in sequence.

[0088] In this disclosure, Fig.23 The direction of the increased current signal, such as Fig.24 As shown, when the second switch K2 is closed, the current signal provided by the first end of the second power module C2 is transmitted back to the second end of the second power module C2 via the second resistor RL2, the second diode D2, the wafer stage 18, the cable and the energy storage module 13.

[0089] It should be noted that in Fig.23 In fact, the first power module C3 is used to discharge the energy storage module 13, so that the current slope on the energy storage module 13 rises from 0 to the set current limit value I1 in the T1 stage. The first diode D1 withstands the reverse voltage. The second power module C2 is used to determine the bias current of the second diode D2. At this time, the direction of the current signal does not pass through the first diode D1. Therefore, there is no need to test the voltage of the main test device 16 and the current value in the test circuit. Accordingly, the parameters in the reverse recovery process of the main test device 16 are not tested. In the second stage of testing the parameters of the reverse recovery process of the main test device 16, see the aforementioned for details. Fig.21 The description and examples will not be repeated here.

[0090] The following example is taken as follows: the main test device 16 is the first insulated gate bipolar transistor IG1, the auxiliary test device 17 is the second insulated gate bipolar transistor IG2, both of which are N-channel IGBT transistors, the accompanying test device 14 is the third diode D3, and the number of the second insulated gate bipolar transistor IG2 is one.

[0091] In some examples, when testing the switching parameters of the main test device 16, the first switch K1 is closed, the main test device 16 is in the on state, the auxiliary test device 17 is in the on state, and the companion test device 14 is reverse biased, so that the current signal provided by the first end of the power module 11 is transmitted back to the second end of the power module 11 via the energy storage module 13, the cable, the wafer carrier 18 and the main test device 16 in sequence.

[0092] For the above example, Fig.25 As shown, the main test device 16 is a first insulated gate bipolar transistor IG1, the auxiliary test device 17 is a second insulated gate bipolar transistor IG2, and the accompanying test device 14 is a third diode D3, wherein the first insulated gate bipolar transistor IG1 and the second insulated gate bipolar transistor IG2 can be IGBT transistors or bipolar transistors (BJT). Since IGBT transistors or bipolar transistors (BJT) have different characteristics compared to MOS tubes, specifically, MOS tubes can be approximated as resistance paths when they are turned on, while IGBT transistors or bipolar transistors (BJT) can only be forward-conducted, not reverse-conducted, and have no built-in body diodes, therefore, there is no need to test the parameters of the reverse recovery process in wafer testing. The present disclosure takes IGBT transistors as an example, and can also be extended to bipolar transistors (BJT). When testing the first switch parameter of the main test device 16, the first switch K1 is closed, the first controller outputs a high-level drive signal to control the first insulated gate bipolar transistor IG1 to be in a conducting state, the second controller outputs a high-level drive signal to control the second insulated gate bipolar transistor IG2 to be in a continuously conducting state, and the third diode D3 is reverse biased, Fig.25 The arrows in the test circuit 10 are used to describe the Fig.16 The flow direction of the current signal in the T1 phase of the waveform diagram is that the current signal provided by the first end of the power module 11 is transmitted back to the second end of the power module 11 via the energy storage module 13, the cable, the wafer carrier 18 and the first insulated gate bipolar transistor IG1 in sequence.

[0093] It should be noted that the high level signal or low level signal output by the first controller and the second controller drives the G / B poles of the first insulated gate bipolar transistor IG1 and the second insulated gate bipolar transistor IG2. Fig.14 The description of the contents shown will not be repeated in detail here.

[0094] In some examples, when testing the switching parameters of the main test device 16, the first switch K1 is closed, the main test device 16 is in the off state, the auxiliary test device 17 is in the on state, and the accompanying test device 14 is forward biased, so that the current signal provided by the first end of the power supply module 11 is transmitted back to the first end of the power supply module 11 via the energy storage module 13, the cable, the wafer carrier 18, the auxiliary test device 17, and the accompanying test device 14 in sequence.

[0095] For the above examples, see Fig.26 , which shows another current signal flow diagram of a switch parameter test in which the main test device 16 is an insulated gate bipolar transistor and the accompanying test device 14 is a diode, provided by the present disclosure, Fig.26 The arrows in the figure depict the Fig.16At this time, when testing the second switch parameter of the main test device 16, the first switch K1 is closed, the first controller outputs a low-level drive signal to control the first insulated gate bipolar transistor IG1 to be in the off state, and the second controller outputs a high-level drive signal to control the second insulated gate bipolar transistor IG2 to be in the on state and the third diode D3 to be forward biased. The current signal provided by the first end of the power module 11 is transmitted from the energy storage module 13, the cable, the wafer carrier 18, the second insulated gate bipolar transistor IG2, and the third diode D3 back to the first end of the power module 11. For other contents, see Fig.15 The description of the contents shown will not be repeated in detail here.

[0096] It should be noted that, through Fig.25 and Fig.26 After obtaining the first switch parameter and the second switch parameter, the test circuit 10 performs data verification to ensure that there are no errors or abnormal values. According to the test requirements and standards, the final switch parameter is obtained based on the first switch parameter and the second switch parameter, for example, by calculating statistical parameters such as average value, maximum value, minimum value, etc.

[0097] For some examples, see Fig. 27 The test circuit 10 also includes a sampling resistor, a first end of which is connected to the second end of the power module 11 , and a second end of which is connected to the main test device 16 .

[0098] For example, the sampling resistor may be Fig. 27 The sampling resistor RS is shown in FIG.

[0099] In the present disclosure, a dynamic parameter testing method for a wafer is also provided. The testing method is applied to the above-mentioned test circuit 10, and the testing method may include: determining a driving signal according to the parameters to be tested; controlling the states of a main test device 16, a companion test device 14, and an auxiliary test device 17 in the test circuit 10 according to the driving signal, and obtaining the voltage and current of the main test device 16 corresponding to the parameters to be tested; determining the parameters to be tested according to the voltage and current of the main test device 16, wherein the parameters to be tested include the switching parameters of the wafer and the parameters of the reverse recovery process.

[0100] For the technical solution of the above-mentioned test method, a driver is used to generate an accurate drive signal, which can be a voltage pulse or a current pulse, to control the switching action of the main test device 16, the closing and opening of the selector 12 to select the current path, and transmit the current signal from the energy storage module 13 to the main test device 16, or reversely transmit it back to the power module 11 and the switching of the accompanying test device 14 between the on state and the off state, so as to cooperate with the test of the main test device 16, provide the necessary current return path or simulate different load conditions. The voltage and current direction of the main test device 16 are measured in different types and states of each device to obtain the switching parameters of the main test device 16 and the parameters of the reverse recovery process. This method can comprehensively evaluate the switching parameters of the main test device 16 and the parameters of the reverse recovery process, improve the accuracy and efficiency of the test, and protect the safety of the main test device 16, providing important data for device design and performance optimization.

[0101] For the above-mentioned test method, in some examples, the selector 12 includes a first switch K1 and a second switch K2, and the drive signal includes a first drive signal, a second drive signal and a third drive signal. The test method may include: controlling the first switch K1 to be closed, controlling the main test device 16 to be in an on state through the first drive signal, controlling the auxiliary test device 17 to be in an on state through the second drive signal, and controlling the companion test device 14 to be in an off state through the third drive signal, so that the current signal provided by the first end of the power supply module 11 is transmitted back to the second end of the power supply module 11 via the energy storage module 13, the cable, the wafer carrier 18 and the main test device 16 in sequence, obtaining the changes in the voltage and current of the main test device 16, and obtaining the switching parameters of the main test device 16 according to the changes in the voltage and current of the main test device 16.

[0102] For the above-mentioned test method, in some examples, the selector 12 includes a first switch K1 and a second switch K2, and the drive signal includes a first drive signal, a second drive signal and a third drive signal. The test method may include: controlling the first switch K1 to be closed, controlling the main test device 16 to be in an off state through the first drive signal, controlling the auxiliary test device 17 to be in an on state through the second drive signal, and controlling the accompanying test device 14 to be in an off state through the third drive signal, so that the current signal provided by the first end of the power supply module 11 is transmitted back to the first end of the power supply module 11 via the energy storage module 13, the cable, the wafer carrier 18, the auxiliary test device 17 and the accompanying test device 14 in sequence, obtaining the changes in the voltage and current of the main test device 16, and obtaining the switching parameters of the main test device 16 according to the changes in the voltage and current of the main test device 16.

[0103] For the above-mentioned test method, in some examples, the selector 12 includes a first switch K1 and a second switch K2, and the drive signal includes a first drive signal, a second drive signal and a third drive signal. The test method may include: controlling the second switch K2 to be closed, controlling the main test device 16 to be in an off state through the first drive signal, controlling the auxiliary test device 17 to be in an on state through the second drive signal, and controlling the accompanying test device 14 to be in an on state through the third drive signal, so that the current signal provided by the first end of the power module 11 is transmitted back to the second end of the power module 11 in sequence via the accompanying test device 14, the auxiliary test device 17, the wafer stage 18, the cable and the energy storage module 13 to charge the energy storage module 13.

[0104] For the above-mentioned test method, in some examples, the selector 12 includes a first switch K1 and a second switch K2, and the drive signal includes a first drive signal, a second drive signal and a third drive signal. The test method may include: controlling the second switch K2 to be closed, controlling the main test device 16 to be in an off state through the first drive signal, controlling the auxiliary test device 17 to be in an on state through the second drive signal, and controlling the companion test device 14 to be in an off state through the third drive signal, so that the current signal provided by the first end of the energy storage module 13 is transmitted back to the second end of the energy storage module 13 via the main test device 16, the wafer carrier 18 and the cable in sequence, obtaining the changes in the voltage and current of the main test device 16, and obtaining the parameters of the reverse recovery process of the main test device 16 according to the changes in the voltage and current of the main test device 16.

[0105] For the above-mentioned test method, in some examples, the selector 12 includes a first switch K1 and a second switch K2, and the drive signal includes a third drive signal. The test method may include: controlling the second switch K2 to be closed, controlling the accompanying test device 14 to be in an on state through the third drive signal, the main test device 16 to be reverse biased, and the auxiliary test device 17 to be forward biased, so that the current signal provided by the first end of the power module 11 is transmitted back to the second end of the power module 11 in sequence via the accompanying test device 14, the auxiliary test device 17, the wafer stage 18, the cable and the energy storage module 13 to charge the energy storage module 13.

[0106] For the above-mentioned test method, in some examples, the selector 12 includes a first switch K1 and a second switch K2, and the drive signal includes a third drive signal. The test method may include: controlling the second switch K2 to be closed, controlling the accompanying test device 14 to be in a cut-off state through the third drive signal, the main test device 16 to be forward biased, and the auxiliary test device 17 to be forward biased, so that the current signal provided by the first end of the energy storage module 13 is transmitted back to the second end of the energy storage module 13 via the main test device 16, the wafer carrier 18 and the cable in sequence, and the changes in the voltage and current of the main test device 16 are obtained, and according to the changes in the voltage and current of the main test device 16, the parameters of the reverse recovery process of the main test device 16 are obtained.

[0107] For the above-mentioned test method, in some examples, the selector 12 includes a first switch K1 and a second switch K2, and the drive signal includes a third drive signal. The test method may include: controlling the second switch K2 to be closed, controlling the accompanying test device 14 to be in an on state through the third drive signal, the main test device 16 to be reverse biased, and the auxiliary test device 17 to be forward biased, so that the current signal provided by the first end of the power module 11 is transmitted back to the second end of the power module 11 via the accompanying test device 14, the auxiliary test device 17, the wafer stage 18, the cable and the energy storage module 13 in sequence to charge the energy storage module 13; and the current signal provided by the first end of the power module 11 is transmitted back to the second end of the power module 11 via the constant current device, the auxiliary test device 17, the wafer stage 18, the cable and the energy storage module 13 in sequence.

[0108] For the above-mentioned test method, in some examples, the selector 12 includes a first switch K1 and a second switch K2, and the drive signal includes a third drive signal. The test method may include: controlling the second switch K2 to be closed, controlling the accompanying test device 14 to be in a conductive state through the third drive signal, the main test device 16 to be reverse biased, and the auxiliary test device 17 to be forward biased, so that the current signal provided by the first end of the first power supply module C3 is transmitted back to the second end of the first power supply module C3 via the accompanying test device 14, the auxiliary test device 17, the wafer stage 18, the cable and the energy storage module 13 in sequence to charge the energy storage module 13; and the current signal provided by the first end of the second power supply module C2 is transmitted back to the second end of the second power supply module C2 via the auxiliary test device 17, the wafer stage 18, the cable and the energy storage module 13.

[0109] For the above-mentioned test method, in some examples, the selector 12 includes a first switch K1 and a second switch K2, and the drive signal includes a first drive signal and a second drive signal. The test method may include: controlling the first switch K1 to be closed, controlling the main test device 16 to be in an on state through the first drive signal, and controlling the auxiliary test device 17 to be in an on state through the second drive signal, and reverse biasing the companion test device 14, so that the current signal provided by the first end of the power supply module 11 is transmitted back to the second end of the power supply module 11 via the energy storage module 13, the cable, the wafer carrier 18 and the main test device 16 in sequence, obtaining the changes in voltage and current of the main test device 16, and obtaining the switching parameters of the main test device 16 according to the changes in voltage and current of the main test device 16.

[0110] For the above-mentioned test method, in some examples, the selector 12 includes a first switch K1 and a second switch K2, and the drive signal includes a first drive signal and a second drive signal. The test method may include: controlling the first switch K1 to be closed, controlling the main test device 16 to be in an off state through the first drive signal, and controlling the auxiliary test device 17 to be in an on state through the second drive signal, and forward biasing the accompanying test device 14, so that the current signal provided by the first end of the power supply module 11 is transmitted back to the first end of the power supply module 11 via the energy storage module 13, the cable, the wafer carrier 18, the auxiliary test device 17, and the accompanying test device 14 in sequence, and the changes in the voltage and current of the main test device 16 are obtained, and the switching parameters of the main test device 16 are obtained according to the changes in the voltage and current of the main test device 16.

[0111] The specific details of the above-mentioned dynamic parameter testing method for wafers that have not been described in detail can be found in the description of the dynamic parameter testing circuit for wafers mentioned above, and will not be repeated here.

[0112] It should be noted that the technical solutions described in the present disclosure can be combined arbitrarily without conflict.

[0113] The above are only specific implementation methods of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with the technical field within the technical scope disclosed in the present disclosure should be covered by the protection scope of the present disclosure.

Claims

1. A dynamic parameter test circuit for a wafer, characterized in that: The test circuit includes: a power supply module, a routing device, an energy storage module, a companion test device, a wafer carrier, a test module, a main test device and at least one auxiliary test device, wherein: The power supply module is used to provide a current signal for the test circuit; The energy storage module is used to store the current signal; The router is used to transmit the current signal to the main test device and / or the auxiliary test device via the energy storage module and the wafer stage, or to transmit the current signal to the main test device via the auxiliary test device and the energy storage module; The accompanying test device is connected between the auxiliary test device and the power module; The wafer stage is used to fix the main test device and transmit the current signal provided by the power module; The test module is used to obtain the voltage and current of the main test device to determine the test result according to the voltage and current.

2. The test circuit according to claim 1, characterized in that: The main test device and the auxiliary test device are adjacent to each other and are arranged in series, a plurality of the auxiliary test devices are arranged in parallel, and the main test device and the auxiliary test device are integrated on the same semiconductor substrate.

3. The test circuit according to claim 2, characterized in that: The path selector includes a first switch and a second switch, and the states thereof include a closed state and an open state. The first switch and the second switch are arranged in parallel, and one and only one of the first switch and the second switch is in a closed state, wherein the first switch is used to transmit the current signal provided by the power module back to the power module via the energy storage module, the wafer stage and the main test device in sequence, or to transmit the current signal provided by the power module back to the power module via the energy storage module, the wafer stage, the auxiliary test device and the accompanying test device in sequence; The second switch is used to transmit the current signal provided by the power module back to the power module via the auxiliary test device, the wafer stage and the energy storage module in sequence, or to transmit the current signal provided by the power module back to the power module via the main test device, the wafer stage and the energy storage module in sequence.

4. The test circuit according to claim 3, characterized in that: The accompanying test device comprises: A switch transistor has a first end connected to the first end of the auxiliary test device, a second end connected to the first end of the power module, and a third control end used to control the switch transistor to enter an on state or an off state.

5. The test circuit according to claim 4, characterized in that: The main test device comprises: A first transistor, a first end of which is connected to the second end of the power module, a second end of which is connected to the wafer stage, and a first control end of which is used to control the first transistor to enter an on state or an off state; The auxiliary test device comprises: A second transistor has a first end connected to the first end of the switch transistor, a second end connected to the wafer stage, and a second control end used to control the second transistor to enter a continuously conducting state.

6. The test circuit according to claim 3, characterized in that: When testing the switching parameters of the main test device, the first switch is closed, the main test device is in the on state, the auxiliary test device is in the on state, and the companion test device is in the off state, so that the current signal provided by the first end of the power supply module is transmitted back to the second end of the power supply module via the energy storage module, the cable, the wafer carrier and the main test device in sequence.

7. The test circuit according to claim 3, characterized in that: When testing the switching parameters of the main test device, the first switch is closed, the main test device is in the off state, the auxiliary test device is in the on state, and the accompanying test device is in the off state, so that the current signal provided by the first end of the power supply module is transmitted back to the first end of the power supply module via the energy storage module, the cable, the wafer carrier, the auxiliary test device and the accompanying test device in sequence.

8. The test circuit according to claim 3, characterized in that: In the first stage of testing the parameters of the reverse recovery process of the main test device, the second switch is closed, the main test device is in the off state, the auxiliary test device is in the on state, and the companion test device is in the on state, so that the current signal provided by the first end of the power module is transmitted back to the second end of the power module via the companion test device, the auxiliary test device, the wafer stage, the cable and the energy storage module in sequence to charge the energy storage module.

9. The test circuit according to claim 8, characterized in that: In the second stage of testing the parameters of the reverse recovery process of the main test device, the energy storage module is discharged, the second switch is closed, the main test device is in the off state, the auxiliary test device is in the on state, and the companion test device is in the off state, so that the current signal provided by the first end of the energy storage module is transmitted back to the second end of the energy storage module via the main test device, the wafer carrier and the cable in sequence.

10. The test circuit according to claim 4, characterized in that: The main test device comprises: A first diode, a first end of which is connected to the second end of the power module, and a second end of which is connected to the wafer stage; The auxiliary test device comprises: A second diode has a first end connected to the first end of the switch transistor in the companion device, and a second end connected to the wafer stage.

11. The test circuit according to claim 3, characterized in that: In the first stage of testing the parameters of the reverse recovery process of the main test device, the second switch is closed, the companion test device is in the on state, the main test device is reverse biased, and the auxiliary test device is forward biased, so that the current signal provided by the first end of the power supply module is transmitted back to the second end of the power supply module via the companion test device, the auxiliary test device, the wafer stage, the cable and the energy storage module in sequence to charge the energy storage module.

12. The test circuit according to claim 3, characterized in that: In the second stage of testing the parameters of the reverse recovery process of the main test device, the energy storage module is discharged, the second switch is closed, the companion test device is in the cut-off state, the main test device is forward biased, and the auxiliary test device is forward biased, so that the current signal provided by the first end of the energy storage module is transmitted back to the second end of the energy storage module via the main test device, the wafer carrier and the cable in sequence.

13. The test circuit according to claim 3, characterized in that: The test circuit also includes: a constant current device, used to provide a constant direct current bias for the auxiliary test device.

14. The test circuit according to claim 13, characterized in that: The constant current device comprises: A constant current transistor, having a first end connected to the first end of the power module and a second end connected to the first end of the auxiliary test device, is used to replicate the current signal provided by the power module and transmit it to the first end of the auxiliary test device.

15. The test circuit according to claim 13, characterized in that: In the first stage of testing the parameters of the reverse recovery process of the main test device, the second switch is closed, the companion test device is in the on state, the main test device is reverse biased, and the auxiliary test device is forward biased, so that the current signal provided by the first end of the power module is transmitted back to the second end of the power module via the companion test device, the auxiliary test device, the wafer stage, the cable and the energy storage module in sequence to charge the energy storage module, and the current signal provided by the first end of the power module is transmitted back to the second end of the power module via the constant current device, the auxiliary test device, the wafer stage, the cable and the energy storage module in sequence.

16. The test circuit according to claim 3, characterized in that: The power supply module includes a first power supply module and a second power supply module, wherein the first power supply module and the second power supply module are arranged in parallel, the first end of the first power supply module is connected to the second end of the companion test device through a first resistor, and the second end of the first power supply module is connected to the first end of the main test device; the first end of the second power supply module is connected to the first end of the auxiliary test device through a second resistor, and the second end of the second power supply module is connected to the first end of the main test device, for providing a bias current to the auxiliary test device.

17. The test circuit according to claim 16, characterized in that: In the first stage of testing the parameters of the reverse recovery process of the main test device, the second switch is closed, the companion test device is in the on state, the main test device is reverse biased, and the auxiliary test device is forward biased, so that the current signal provided by the first end of the first power supply module is transmitted back to the second end of the first power supply module via the companion test device, the auxiliary test device, the wafer stage, the cable and the energy storage module in sequence to charge the energy storage module; and the current signal provided by the first end of the second power supply module is transmitted back to the second end of the second power supply module via the auxiliary test device, the wafer stage, the cable and the energy storage module.

18. The test circuit according to claim 1, characterized in that: The accompanying test device comprises: A third diode has a first end connected to the first end of the power module and a second end connected to the first end of the auxiliary test device.

19. The test circuit according to claim 18, characterized in that: The main test device comprises: A first insulated gate bipolar transistor, a first end of which is connected to the second end of the power module, a second end of which is connected to the wafer stage, and a first control end is used to control the first insulated gate bipolar transistor to enter an on state or an off state; The auxiliary test device comprises: A second insulated gate bipolar transistor has a first end connected to the second end of the third diode, a second end connected to the wafer carrier, and a second control end used to control the second insulated gate bipolar transistor to enter an on state or an off state.

20. The test circuit according to claim 3, characterized in that: When testing the switching parameters of the main test device, the first switch is closed, the main test device is in the on state, the auxiliary test device is in the on state, and the companion test device is reverse biased, so that the current signal provided by the first end of the power supply module is transmitted back to the second end of the power supply module in sequence via the energy storage module, the cable, the wafer carrier and the main test device.

21. The test circuit according to claim 3, characterized in that: When testing the switching parameters of the main test device, the first switch is closed, the main test device is in the off state, the auxiliary test device is in the on state, and the companion test device is forward biased, so that the current signal provided by the first end of the power supply module is transmitted back to the first end of the power supply module via the energy storage module, the cable, the wafer carrier, the auxiliary test device, and the companion test device in sequence.

22. A method for testing dynamic parameters of a wafer, characterized in that: The test method includes: Determine the driving signal according to the parameters to be tested; Controlling the states of the main test device, the companion test device, and the auxiliary test device in the test circuit according to any one of claims 1 to 21 according to the drive signal, and obtaining the voltage and current of the main test device corresponding to the parameter to be tested; The parameters to be tested are determined according to the voltage and current of the main test device, wherein the parameters to be tested include switching parameters of the wafer and parameters of the reverse recovery process.

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