Semiconductor device, preparation method and memory system

Abstract

The invention discloses a semiconductor device, a preparation method and a memory system, and the semiconductor device comprises a semiconductor column which extends along a first direction Y; the gate dielectric layer surrounds the side surface of the semiconductor column; the grid electrode is connected with the grid dielectric layer; a first insulating layer surrounding the gate and the semiconductor pillar; the second insulating layer is positioned above the first insulating layer; the connecting part is located above the semiconductor column and connected with the semiconductor column, and at least part of the connecting part is located above the first insulating layer; the conductive part is located on the side, away from the semiconductor column, of the connecting part, and the conductive part is connected with the connecting part. According to the semiconductor device provided by the invention, the structure of the semiconductor column is prolonged through the connecting part, so that the conductive part can be completely reserved, the connection stability of the conductive part and other components is further improved, and the yield of manufacturing the semiconductor device is greatly improved.

Description

Technical Field

[0001] Embodiments of the present application relate to the technical field of electronic devices, and in particular to a semiconductor device, a manufacturing method, and a memory system. Background Art

[0002] Capacitors are important components in semiconductor devices. During the preparation of capacitors, the connection points in the transistors are often over-etched and damaged, making the capacitors fail to meet production standards and causing quality problems in the subsequent use of semiconductor devices. Summary of the invention

[0003] Embodiments of the present application provide a semiconductor device, a manufacturing method and a memory system to solve the technical problem in the prior art that connection points in transistors are easily over-etched.

[0004] In order to solve the above technical problems, the embodiments of the present application disclose the following technical solutions:

[0005] In a first aspect, a semiconductor device is provided, comprising:

[0006] A semiconductor column extending along a first direction Y;

[0007] A gate dielectric layer, the gate dielectric layer surrounding the side of the semiconductor column;

[0008] A gate connected to the gate dielectric layer;

[0009] a first insulating layer, the first insulating layer surrounding the gate and the semiconductor column;

[0010] a second insulating layer, the second insulating layer being located above the first insulating layer;

[0011] a connecting portion, the connecting portion being located above the semiconductor column and connected to the semiconductor column, wherein at least a portion of the connecting portion is located above the first insulating layer;

[0012] The conductive portion is located at a side of the connecting portion away from the semiconductor column, and the conductive portion is connected to the connecting portion.

[0013] In combination with the first aspect, it further includes a capacitor structure, which is located on a side of the conductive portion away from the connecting portion and coupled to the conductive portion, and the second insulating layer surrounds the peripheral side of the capacitor structure.

[0014] In combination with the first aspect, further comprising a stop layer, wherein the stop layer is located between the first insulating layer and the second insulating layer, and the stop layer surrounds the connecting portion; or

[0015] The stop layer surrounds the connection portion and the conductive portion.

[0016] In combination with the first aspect, the second insulating layer surrounds the conductive portion; or

[0017] The second insulating layer surrounds the connecting portion and the conductive portion.

[0018] In combination with the first aspect, the conductive portion is electrically connected to the connecting portion, and a material of the conductive portion includes metal silicide.

[0019] In combination with the first aspect, the connecting portion includes an epitaxially grown semiconductor, and the connecting portion and the semiconductor column are made of the same material.

[0020] In a second aspect, a method for preparing a semiconductor device is provided, the method comprising:

[0021] forming a semiconductor column, wherein the semiconductor column extends along a first direction;

[0022] forming a gate dielectric layer around the side of the semiconductor column;

[0023] forming a gate surrounding the gate dielectric layer;

[0024] forming a first insulating layer surrounding the semiconductor pillar and the gate;

[0025] forming a second insulating layer on the first insulating layer, and etching the second insulating layer to form a connecting groove to expose the semiconductor column;

[0026] forming a connecting portion in the connecting groove, the connecting portion being located above the semiconductor column and connected to the semiconductor column, wherein at least a portion of the connecting portion is located above the first insulating layer;

[0027] A conductive portion connected to the connecting portion is formed in the connecting groove, and the conductive portion is located on a side of the connecting portion away from the semiconductor column.

[0028] In combination with the second aspect, after the conductive portion is formed, a capacitor structure is formed in the connecting groove, and the capacitor structure is coupled to the conductive portion.

[0029] In combination with the second aspect, before forming the connecting groove, the preparation method further includes:

[0030] forming a stop layer on the first insulating layer and the semiconductor pillar;

[0031] forming a second insulating layer on the stop layer, wherein the second insulating layer covers the stop layer;

[0032] forming a mask layer on the second insulating layer, wherein the mask layer covers the second insulating layer;

[0033] The stop layer, the first insulating layer and the mask layer are etched away respectively along a first direction Y to form a connection groove to expose the semiconductor pillar.

[0034] In combination with the second aspect, there are a plurality of semiconductor pillars, there are a plurality of connection grooves, and the connection grooves correspond to the semiconductor pillars one by one.

[0035] In combination with the second aspect, a method for forming a connecting portion on the semiconductor column includes:

[0036] Using an epitaxial growth process to form the connection portion of the semiconductor column in the connection groove;

[0037] The connecting portion and the semiconductor column are both made of silicon.

[0038] In combination with the second aspect, the method for forming a conductive portion on the connecting portion includes:

[0039] Depositing the conductive portion in the connecting groove; and

[0040] removing the mask layer to expose the second insulating layer;

[0041] The conductive portion covers the connecting portion, and the conductive portion is electrically connected to the connecting portion.

[0042] In combination with the second aspect, the material of the conductive part includes titanium silicon.

[0043] In a third aspect, a memory system is provided, comprising:

[0044] The semiconductor device according to any embodiment of the first aspect;

[0045] A controller is electrically connected to the semiconductor device and is used to control the semiconductor device.

[0046] One of the above technical solutions has the following advantages or beneficial effects:

[0047] Compared with the prior art, the present application provides a semiconductor device, including: a semiconductor column, the semiconductor column extends along a first direction Y; a gate dielectric layer, the gate dielectric layer surrounds the side of the semiconductor column; a gate, the gate is connected to the gate dielectric layer; a first insulating layer, the first insulating layer surrounds the gate and the semiconductor column; a second insulating layer, the second insulating layer is located above the first insulating layer; a connecting portion, the connecting portion is located above the semiconductor column and connected to the semiconductor column, wherein at least part of the connecting portion is located above the first insulating layer; a conductive portion, the conductive portion is located on a side of the connecting portion away from the semiconductor column, and the conductive portion is connected to the connecting portion. The semiconductor device provided by the present application extends the structure of the semiconductor column through the connecting portion so that the conductive portion can be completely retained, thereby improving the connection stability of the conductive portion with other components, and greatly improving the yield of manufacturing semiconductor devices.

[0048] The present application provides a method for preparing a semiconductor device, the method comprising: forming a semiconductor column, the semiconductor column extending along a first direction to form a gate dielectric layer around the side of the conductor column; forming a gate around the gate dielectric layer; forming a first insulating layer around the semiconductor column and the gate; forming a second insulating layer on the first insulating layer, etching the second insulating layer to form a connection groove to expose the semiconductor column; forming a connection portion in the connection groove, the connection portion is located above the semiconductor column and connected to the semiconductor column, wherein at least part of the connection portion is located above the first insulating layer; forming a conductive portion connected to the connection portion in the connection groove, the conductive portion is located on a side of the connection portion away from the semiconductor column. The present application forms a second insulating layer after forming the semiconductor column, and forms a connection portion and a conductive portion respectively after etching and exposing the semiconductor column, thereby ensuring that the semiconductor column and the conductive portion can be completely retained, thereby improving the connection stability of the conductive portion with other components, thereby improving the yield rate of manufacturing semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0050] Figure 1 A schematic diagram of the first preparation method provided in the embodiment of the present application;

[0051] Figure 2 A schematic diagram of the structure of transition etching provided in an embodiment of the present application;

[0052] Figure 3 A schematic cross-sectional view of a semiconductor structure provided in an embodiment of the present application;

[0053] Figure 4 A schematic diagram of the cross-sectional structure of a semiconductor layer and a semiconductor column provided in an embodiment of the present application;

[0054] Figure 5A schematic diagram of a top view structure of a semiconductor layer and a semiconductor column provided in an embodiment of the present application;

[0055] Figure 6 A schematic diagram of a cross-sectional structure after a gate is formed according to an embodiment of the present application;

[0056] Figure 7 A schematic diagram of a cross-sectional structure after forming a first insulating layer provided in an embodiment of the present application;

[0057] Figure 8 A schematic diagram of the cross-sectional structure after depositing a mask layer provided in an embodiment of the present application;

[0058] Fig. 9 A schematic diagram of the cross-sectional structure of the connection groove formed by etching provided in an embodiment of the present application;

[0059] Fig.10 A schematic diagram of a cross-sectional structure of a connection portion provided in an embodiment of the present application;

[0060] Fig.11 A schematic diagram of a cross-sectional structure of a conductive portion formed according to an embodiment of the present application;

[0061] Fig.12 Schematic diagram of the cross-sectional structure after removing the mask layer provided in the embodiment of the present application

[0062] Fig.13 A schematic cross-sectional structure diagram of a capacitor structure provided in an embodiment of the present application.

[0063] The reference numerals are as follows:

[0064] 100-semiconductor layer, 101-substrate, 110-semiconductor column, 111-first groove, 112-second groove, 113-third groove, 120-gate, 130-gate dielectric layer, 140-first insulating layer, 150-air gap, 210-stop layer, 220-second insulating layer, 230-mask layer, 240-connecting part, 250-conductive part, 300-connecting groove, 400-capacitor structure. DETAILED DESCRIPTION

[0065] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. In the description of the present application, it is necessary to understand that the orientation or position relationship indicated by the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", etc. is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present application. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0066] It should be understood that although the terms first, second, etc. may be used herein to describe various components, these components should not be limited to these terms. These terms are used to distinguish one component from another component. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component without departing from the scope of the present invention.

[0067] It should be understood that when a component is said to be "on" or "connected" another component, it can be directly on or connected to another component, or there may be an intervening component. Other words used to describe the relationship between components should be interpreted in a similar manner.

[0068] As used herein, the term "layer" refers to a material portion including an area with thickness. The layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far away from the substrate. The layer can extend over the entire lower or upper structure, or can have a range less than the range of the lower or upper structure. In addition, the layer can be a region of a uniform or non-uniform continuous structure whose thickness is less than the thickness of the continuous structure. For example, the layer can be located between the top and bottom surfaces of the continuous structure or between any set of horizontal planes at the top and bottom surfaces. The layer can extend horizontally, vertically and / or along a tapered surface. The substrate can be a layer, which can include one or more layers, and / or can have one or more layers on, above and / or below it. The layer can include multiple layers. For example, an interconnect layer can include one or more conductive layers and a contact layer (wherein contacts, interconnects and one or more dielectric layers are formed.

[0069] This article uses a Cartesian coordinate system (expressed as X, Y and Z) to represent the cross-section of the memory in various directions, wherein the direction of the XY plane is parallel to the substrate and the Z direction is perpendicular to the substrate.

[0070] It should be noted that the diagrams provided in the embodiments of the present invention are only used to illustrate the basic concept of the present invention in a schematic manner. Although the diagrams only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout type may also be more complicated.

[0071] The memory in the embodiment of the present invention may be a wafer or a three-dimensional memory. The three-dimensional memory may be applied to communication products, consumer electronics products, automotive products, aerospace products, artificial intelligence products or big data, etc. Among them, consumer electronics products include but are not limited to mobile phones, computers, tablets, cameras, smart glasses or game products, etc.

[0072] See also Figure 1 and Figure 2 , Figure 1 and Figure 2 is a step for preparing a semiconductor device in some other embodiments of the present disclosure, and before this step, it also includes the steps of: depositing a conductive portion 250 on the formed semiconductor column 110, then forming a gate dielectric layer 130 and a gate 120, and then depositing a first insulating layer 140, wherein the upper surface of the first insulating layer 140 is flush with the top of the conductive portion 250, and then depositing a stop layer 210, a second insulating layer 220 and a mask layer 230 in sequence; and then obtaining a conductive portion 250 by a first etching method. Figure 1 The structure of the left figure is then removed by a second etching method to expose the conductive portion 250, and the Figure 1 However, during the second etching, the progress of etching cannot be guaranteed, resulting in the conductive part 250 being completely or partially etched, and the following is obtained: Figure 2 The structure shown in FIG. As a result, the semiconductor device cannot be used any more, resulting in a low yield of the semiconductor device. The embodiment of the present application proposes a new semiconductor structure and a preparation method, which can prevent the semiconductor device from being over-etched during the second etching.

[0073] See also Fig.13 , Fig.13Schematic diagram of the structure of the semiconductor device provided by the embodiment of the present application. The embodiment of the present application provides a semiconductor device, including a semiconductor column 110, a gate dielectric layer 130, a gate 120, a first insulating layer 140, a second insulating layer 220, a connecting portion 240 and a conductive portion 250. The semiconductor column 110 extends along the first direction Y; the gate dielectric layer 130 surrounds the side of the semiconductor column 110; the gate 120 is connected to the gate dielectric layer 130; the first insulating layer 140 surrounds the gate 120 and the semiconductor column 110; the second insulating layer 220 is located above the first insulating layer 140; the connecting portion 240 is located above the semiconductor column 110 and connected to the semiconductor column 110, wherein at least part of the connecting portion 240 is located above the first insulating layer 140; the conductive portion 250 is located on the side of the connecting portion 240 away from the semiconductor column 110, and the conductive portion 250 is connected to the connecting portion 240. It is understandable that the semiconductor column 110 and the gate 120 and gate dielectric layer 130 on its side can constitute a transistor, and the conduction of the transistor can be controlled by applying voltage to the gate 120. In the present application, the connection portion 240 extends the semiconductor column 110, thereby reducing the impedance between the conductive portion 250 and the semiconductor column 110. It should be noted that the connection portion 240 can be grown by an epitaxial process. Generally, the connection portion 240 obtained by epitaxial growth is the same material as the semiconductor column 110, usually Si material; in some other cases, the connection portion 240 obtained by epitaxial growth can also be different from the material of the semiconductor column 110, such as the semiconductor column 110 is SiGe or SiC, and the connection portion 240 is Si material. The connection portion 240 obtained by epitaxial growth extends the structure of the semiconductor column 110, improves the manufacturing process, and enables the conductive portion 250 to be completely retained, thereby improving the connection stability between the conductive portion 250 and other components, and greatly improving the yield of manufacturing semiconductor devices.

[0074] In some optional embodiments of the present disclosure, please refer to Fig.13 , further comprising a capacitor structure 400, the capacitor structure 400 is located on a side of the conductive portion 250 away from the connecting portion 240 and coupled to the conductive portion 250, and the second insulating layer 220 surrounds the peripheral side of the capacitor structure 400. It can be understood that after the semiconductor pillar 110 is coupled to the capacitor structure 400 through the conductive portion 250, a dynamic random access memory unit is formed, and the corresponding data is stored through the memory unit and applied in different scenarios. Among them, the capacitor structure 400 can be one or more of a pillar capacitor, a cylindrical capacitor or a cup capacitor.

[0075] In some optional embodiments of the present disclosure, please refer to Fig.13, further comprising a stop layer 210, the stop layer 210 being located between the first insulating layer 140 and the second insulating layer 220, the stop layer 210 surrounding the connection portion 240; or the stop layer 210 surrounding the connection portion 240 and the conductive portion 250. It is understood that the constituent material of the stop layer 210 is different from the constituent material of the second insulating layer 220, so that in the etching process, the etching rate of the second insulating layer 220 is greater than the etching rate of the stop layer 210, thereby reducing the over-etching of the semiconductor pillar 110 caused by the stop layer 210 after being penetrated, thereby avoiding damage to the semiconductor pillar 110, thereby improving the manufacturing yield of the semiconductor structure. At the same time, the stop layer 210 surrounds the connection portion 240 or surrounds the connection portion 240 and the conductive portion 250, not only supporting the connection portion 240 and the conductive portion 250, but also insulating the adjacent connection portion 240 and the conductive portion 250.

[0076] In some optional embodiments of the present disclosure, the second insulating layer 220 surrounds the conductive portion 250; or the second insulating layer 220 surrounds the connecting portion 240 and the conductive portion 250. It can be understood that the second insulating layer 220 is not only used to isolate the connecting portion 240 and the conductive portion 250, but also supports the capacitor structure 400, thereby ensuring that the capacitor structure 400 has a certain structure and stability.

[0077] In some optional embodiments of the present disclosure, the conductive portion 250 is electrically connected to the connecting portion 240, and the material of the conductive portion 250 includes metal silicide. It is understandable that the metal silicide includes tungsten silicide, titanium silicide, zirconium silicide, tantalum silicide, palladium silicide, cobalt silicide or platinum silicide. In some optional embodiments of the present disclosure, the conductive portion 250 includes a metal material, and the metal material includes gold, silver, copper, aluminum, titanium, nickel or tungsten, etc. The metal material can facilitate coupling with the capacitor structure 400, and the metal material can provide better support for the capacitor structure 400.

[0078] Figures 3 to 13 is a schematic diagram of a method for preparing a semiconductor device according to an exemplary embodiment. Figures 3 to 13 , the preparation method comprises the following steps:

[0079] S1: forming a semiconductor column 110, wherein the semiconductor column 110 extends along a first direction. Figures 3 to 5 , the specific steps are:

[0080] The semiconductor layer 100 is formed by using single crystal silicon or polycrystalline silicon, and after etching the semiconductor layer 100, a semiconductor column 110 protruding along the Y direction and a substrate 101 located at the bottom of the semiconductor column 110 are obtained. The semiconductor columns 110 and 101 together enclose a first groove 111, a second groove 112 and a third groove 113. Figure 4 and Figure 5The corresponding semiconductor column 110 and the position structure of the first groove 111, the second groove 112 and the third groove 113 are shown. It should be noted that: Figure 4 and Figure 5 The numbers of the semiconductor pillars 110 and the first grooves 111 , the second grooves 112 and the third grooves 113 shown in the figure are only examples. In actual applications, the numbers of the semiconductor pillars 110 and the first grooves 111 , the second grooves 112 and the third grooves 113 may be more or less.

[0081] S2: Form a gate dielectric layer 130 around the side of the semiconductor pillar 110. Figure 6 The specific steps are: forming a gate dielectric layer 130 on one or more sides of the semiconductor pillar 110. In some other embodiments, the gate dielectric layer 130 may also be arranged around the semiconductor pillar 110.

[0082] S3: forming a gate 120 surrounding the gate dielectric layer 130. Figure 6 The specific steps are as follows: after forming a gate dielectric layer 130 on the semiconductor pillar 110, a gate 120 is formed on the surface of the gate dielectric layer 130. The gate 120 may completely cover the gate dielectric layer 130 or partially cover the gate dielectric layer 130. Then, a semiconductor structure connected to the capacitor structure 400 is formed.

[0083] S4: forming a first insulating layer 140 surrounding the semiconductor pillar 110 and the gate 120. Figure 7 , the specific steps are:

[0084] After the gate 120 structure is formed, there are still many gaps between the semiconductor pillars 110. In order to reduce the crosstalk between the semiconductor pillars 110, a first insulating layer 140 is formed between the plurality of semiconductor pillars 110, so that the semiconductor pillars 110, the gate dielectric layer 130 and the gate 120 are all surrounded by the first insulating layer 140, and the gaps between the semiconductor pillars 110 are also filled. The first insulating layer 140 can provide support for the semiconductor pillars 110, the gate dielectric layer 130 and the gate 120 and provide insulation between adjacent gates 120. The material of the first insulating layer 140 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, polysiloxane, polysilazane and any combination thereof. When the first insulating layer 140 is deposited and formed, an air gap 150 is formed inside the first insulating layer 140, and a portion of the first insulating layer 140 can be removed by etching or other methods to open the air gap 150, and the air gap 150 is filled.

[0085] S5: forming a second insulating layer 220 on the first insulating layer 140, and etching the second insulating layer 220 to form a connecting groove 300 to expose the semiconductor pillar 110. Figure 8 and Fig. 9, the specific steps are:

[0086] A stop layer 210 is formed on the first insulating layer 140 and the semiconductor pillar 110; a second insulating layer 220 is formed on the stop layer 210, and the second insulating layer 220 covers the stop layer 210; a mask layer 230 is formed on the second insulating layer 220, and the mask layer 230 covers the second insulating layer 220; the first insulating layer 140, the mask layer 230 and the stop layer 210 are etched and removed in sequence along the first direction Y to form a connection groove 300 to expose the semiconductor pillar 110. It can be understood that in order to improve the integration of the capacitor structure 400 and the storage capacity of the memory, the aspect ratio of the connection groove 300 can be improved. Since the height of the connection groove 300 is basically fixed, the aspect ratio can only be improved by reducing the diameter of the connection groove 300. In order to avoid the diameter of the connection groove 300 being too large during the etching process, the etching rate is controlled by the mask layer 230, the second insulating layer 220 and the stop layer 210, and the aperture of the connection groove 300 is controlled by etching multiple times.

[0087] S6: forming a connection portion 240 in the connection groove 300, wherein the connection portion 240 is located above the semiconductor column 110 and connected to the semiconductor column 110, wherein at least a portion of the connection portion 240 is located above the first insulating layer 140. Fig.10 , the specific steps are:

[0088] An epitaxial growth process is used to form a connecting portion 240 in the connecting groove 300 of the semiconductor column 110; the connecting portion 240 and the semiconductor column 110 are both made of silicon. In general, the connecting portion 240 obtained by epitaxial growth and the semiconductor column 110 are made of the same material, usually Si material. In some other cases, the connecting portion 240 obtained by epitaxial growth may also be made of a different material from the semiconductor column 110, such as when the semiconductor column 110 is SiGe or SiC, and the connecting portion 240 is made of Si material. The connecting portion 240 obtained by epitaxial growth extends the structure of the semiconductor column 110, improves the manufacturing process, and allows the conductive portion 250 to be completely retained, thereby improving the connection stability between the conductive portion 250 and other components, greatly improving the yield of manufacturing semiconductor devices.

[0089] S7: forming a conductive portion 250 connected to the connecting portion 240 in the connecting groove 300, wherein the conductive portion 250 is located on a side of the connecting portion 240 away from the semiconductor pillar 110. Fig.11 and Fig.12 , the specific steps are:

[0090] The conductive part 250 is deposited in the connection groove 300; and the mask layer 230 is removed to expose the second insulating layer 220; the conductive part 250 covers the connection part 240, and the conductive part 250 is electrically connected to the connection part 240. The connection part 240 extends the semiconductor column 110, thereby reducing the impedance between the conductive part 250 and the semiconductor column 110. At the same time, the semiconductor column 110 and the connection part 240 are formed into a whole through epitaxial growth, so that the conductive part 250 obtains more silicon sources. Please refer to Fig.13 After forming the conductive part 250, a capacitor structure 400 is formed in the connecting groove 300, and the capacitor structure 400 is coupled to the conductive part 250. After the semiconductor column 110 is coupled to the capacitor structure 400 through the conductive part 250, a dynamic random access memory unit is formed, and corresponding data is stored through the memory unit. The capacitor structure 400 includes a first electrode, a dielectric layer and a second electrode, and the dielectric layer is located between the first electrode and the second electrode. Generally, the second electrode is a columnar structure, and the dielectric layer and the first electrode are respectively surrounded by the outside of the second electrode, and the first electrode is coupled to the conductive part 250. The constituent materials of the first electrode and the second electrode may include conductive materials such as gold, silver, copper, aluminum, titanium, nickel, tungsten, monocrystalline silicon or polycrystalline silicon. The constituent materials of the dielectric layer may include insulating materials such as silicon oxide, silicon nitride, silicon oxynitride or aluminum nitride. The conductive portion 250 may be made of titanium silicon, aluminum silicide or other related conductive silicide materials, or may be made of conductive materials such as gold, silver, copper, aluminum, titanium, nickel, tungsten, single crystal silicon or polycrystalline silicon.

[0091] In some optional embodiments of the present disclosure, there are multiple semiconductor pillars 110, and there are multiple connection grooves 300, and the connection grooves 300 correspond one to one with the semiconductor pillars 110. It can be understood that after forming the connection portion 240 and the conductive portion 250 on the semiconductor pillars 110, the capacitor structure 400 can be further formed to form a storage unit.

[0092] An embodiment of the present application further provides a memory system, comprising: a semiconductor device as provided in any of the above embodiments; and a controller, the controller being electrically connected to the semiconductor device and being used to control the semiconductor device.

[0093] The semiconductor device and its preparation method, and the memory system provided in the embodiments of the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. 一 A semiconductor device, characterized in that include: A semiconductor column extending along a first direction (Y); A gate dielectric layer, the gate dielectric layer surrounding the side of the semiconductor column; A gate connected to the gate dielectric layer; a first insulating layer, the first insulating layer surrounding the gate and the semiconductor column; a second insulating layer, the second insulating layer being located above the first insulating layer; a connecting portion, the connecting portion being located above the semiconductor column and connected to the semiconductor column, wherein at least a portion of the connecting portion is located above the first insulating layer; The conductive portion is located at a side of the connecting portion away from the semiconductor column, and the conductive portion is connected to the connecting portion.

2. The semiconductor device according to claim 1, wherein: It also includes a capacitor structure, which is located on a side of the conductive portion away from the connecting portion and coupled to the conductive portion, and the second insulating layer surrounds the peripheral side of the capacitor structure.

3. The semiconductor device according to claim 1, wherein: further comprising a stop layer, wherein the stop layer is located between the first insulating layer and the second insulating layer, and the stop layer surrounds the connecting portion; or The stop layer surrounds the connection portion and the conductive portion.

4. The semiconductor device according to claim 1, wherein: The second insulating layer surrounds the conductive portion; or The second insulating layer surrounds the connecting portion and the conductive portion.

5. The semiconductor device according to claim 1, wherein: The conductive part is electrically connected to the connecting part, and the material of the conductive part includes metal silicide.

6. The semiconductor device according to claim 1, wherein: The connecting portion includes an epitaxially grown semiconductor, and the connecting portion and the semiconductor column are made of the same material.

7. A method for preparing a semiconductor device, characterized in that: The method comprises: forming a semiconductor column, wherein the semiconductor column extends along a first direction; forming a gate dielectric layer around the side of the semiconductor column; forming a gate surrounding the gate dielectric layer; forming a first insulating layer surrounding the semiconductor pillar and the gate; forming a second insulating layer on the first insulating layer, and etching the second insulating layer to form a connecting groove to expose the semiconductor column; forming a connecting portion in the connecting groove, the connecting portion being located above the semiconductor column and connected to the semiconductor column, wherein at least a portion of the connecting portion is located above the first insulating layer; A conductive portion connected to the connecting portion is formed in the connecting groove, and the conductive portion is located on a side of the connecting portion away from the semiconductor column.

8. The method for preparing a semiconductor device according to claim 7, characterized in that: After the conductive part is formed, a capacitor structure is formed in the connection groove, and the capacitor structure is coupled to the conductive part.

9. The method for preparing a semiconductor device according to claim 7, wherein: Before forming the connection groove, the preparation method further comprises: forming a stop layer on the first insulating layer and the semiconductor pillar; forming a second insulating layer on the stop layer, wherein the second insulating layer covers the stop layer; forming a mask layer on the second insulating layer, wherein the mask layer covers the second insulating layer; The stop layer, the first insulating layer and the mask layer are etched and removed respectively along a first direction (Y) to form a connection groove to expose the semiconductor pillar.

10. The method for preparing a semiconductor device according to claim 7, wherein: There are a plurality of semiconductor pillars, a plurality of connecting grooves, and the connecting grooves correspond to the semiconductor pillars one by one.

11. The method for preparing a semiconductor device according to claim 7, characterized in that: The method of forming a connection portion on the semiconductor column includes: Using an epitaxial growth process to form the connection portion of the semiconductor column in the connection groove; The connecting portion and the semiconductor column are both made of silicon.

12. The method for preparing a semiconductor device according to claim 9, characterized in that: The method of forming a conductive portion on the connecting portion includes: Depositing the conductive portion in the connecting groove; and removing the mask layer to expose the second insulating layer; The conductive portion covers the connecting portion, and the conductive portion is electrically connected to the connecting portion.

13. The method for preparing a semiconductor device according to claim 7, characterized in that: The conductive part is made of titanium silicon.

14. A memory system, characterized in that: include: The semiconductor device according to any one of claims 1 to 6; A controller is electrically connected to the semiconductor device and is used to control the semiconductor device.

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