Sample sheet for resistivity measurement and preparation method thereof

Abstract

The invention provides a sample wafer for resistivity measurement and a preparation method thereof, and belongs to the technical field of semiconductors. The preparation method of the sample wafer for resistivity measurement comprises the steps that a crystal bar is provided, the crystal bar is cut into a plurality of silicon wafers, the silicon wafers serve as a substrate, and the substrate is provided with a first face and a second face. And forming a doped epitaxial layer on the first surface of the substrate, and when the epitaxial layer is formed, respectively forming epitaxial layers with different resistivity on at least one substrate by controlling the type and flow of doped gas. And removing the substrate to obtain a sample wafer. According to the invention, a crystal bar is cut into a plurality of silicon wafers as substrates, and epitaxial layers with different resistivity are formed on the substrates. And finally, removing the substrate to obtain a sample wafer. Not only is the sample preparation time shortened, but also the loss of the crystal bar is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a sample for resistivity measurement and a preparation method thereof. Background Art

[0002] Single crystal silicon grown by the Czochralski method is widely used in the manufacture of semiconductor electronic devices. Silicon crystals with different resistivities can be grown by doping. For certain device requirements such as advanced wireless communication applications, insulated gate bipolar transistors (IGBTs) and low-power, low-leakage devices, silicon wafers are required to have very high resistivity (over 500ohm.cm). High-resistance silicon wafers are conducive to reducing the impact of parasitic capacitance between devices. Devices can be more densely stacked on the surface of the silicon wafer, while reducing signal transmission losses between devices.

[0003] Resistivity is the main parameter for evaluating the properties of 12-inch single crystal silicon materials. The semiconductor equipment required for resistivity measurement includes four-probe detectors, QCS, mercury CV, SRP, etc. In order to determine the accuracy, stability, and test linearity of the measuring equipment, these devices require a series of samples with different resistivities for calibration, debugging, and mass production process monitoring. Silicon wafers are classified by conductivity type, including phosphorus or arsenic doped N-type resistor silicon wafers, boron doped P-type resistor silicon wafers, P-type and N-type spaced multi-layer resistor silicon wafers, heavily doped low-resistance silicon wafers, intrinsic high-resistance silicon wafers, etc. At present, 12-inch single crystal samples are mainly prepared by the pulling method, which is to seed and pull out silicon crystal rods from silicon solution. If a series of samples with multiple resistivities are required, multiple crystal rods must be pulled, and each crystal rod must be ground and polished before it can be used for resistivity measurement. The entire sample preparation process has defects such as high loss and long time.

[0004] It should be noted that the information disclosed in the background technology section of the invention is only intended to deepen the understanding of the general background technology of the invention, and should not be regarded as an admission or suggestion in any form that the information constitutes prior art already known to those skilled in the art. Summary of the invention

[0005] The object of the present invention is to provide a sample for resistivity measurement and a preparation method thereof, so as to solve the problem that when measuring the resistivity of existing resistor silicon wafers, multiple crystal rods need to be pulled, resulting in long measurement time and high loss.

[0006] In order to solve the above technical problems, the present invention provides a method for preparing a resistivity measurement sample, comprising:

[0007] Providing a crystal rod, cutting the crystal rod into a plurality of silicon wafers, and using the silicon wafers as substrates, wherein the substrate has a first surface and a second surface;

[0008] forming a doped epitaxial layer on the first surface of the substrate, and when forming the epitaxial layer, forming epitaxial layers with different resistivities on at least one substrate by controlling the type and flow rate of the doping gas;

[0009] The substrate is removed to obtain a sample.

[0010] Preferably, before forming the epitaxial layer, the preparation method further comprises:

[0011] forming an oxide layer on the second side of the substrate;

[0012] Removing the substrate, and obtaining the sample further comprises:

[0013] The oxide layer is removed.

[0014] Preferably, the material of the oxide layer is silicon dioxide, and the thickness of the silicon dioxide deposition is greater than or equal to

[0015] Preferably, forming an epitaxial layer on the first surface of the substrate comprises:

[0016] A single epitaxial layer is formed on the first surface of the substrate, and the single epitaxial layer is doped with the same impurity.

[0017] Preferably, forming an epitaxial layer on the first surface of the substrate comprises:

[0018] A plurality of epitaxial layers are formed on the first surface of the substrate, and the resistivity of each epitaxial layer is different by controlling the type of doping gas and the flow rate of the doping gas.

[0019] Preferably, the thickness of the epitaxial layer is greater than or equal to 700 μm.

[0020] Preferably, the impurity types doped in the epitaxial layer include any one of borane, phosphine and arsine, or a combination of two or three of them.

[0021] Preferably, when forming the epitaxial layer, the flow rate of the doping gas is 0 to 500 sccm.

[0022] Preferably, when the substrate is removed, the preparation method further comprises:

[0023] 10 to 20 μm of the epitaxial layer close to the substrate is removed.

[0024] Based on the same inventive concept, the present invention also provides a sample for resistivity measurement, including preparing a plurality of samples with different resistivities using the above-mentioned preparation method.

[0025] Compared with the prior art, the method for preparing a resistivity measurement sample of the present invention has the following advantages:

[0026] The present invention provides a crystal rod, cuts the crystal rod into several silicon wafers, and uses the silicon wafers as substrates, wherein the substrate has a first surface and a second surface. A doped epitaxial layer is formed on the first surface of the substrate. When forming the epitaxial layer, epitaxial layers with different resistivities are formed on at least one substrate by controlling the type and flow rate of the doping gas, and the doping type of the epitaxial layer is different from the doping type of the substrate. The substrate is removed to obtain a sample. Therefore, the method for preparing a resistivity measurement sample provided by the present invention is to cut a crystal rod into several silicon wafers as substrates, and form epitaxial layers with different resistivities on different substrates. Finally, the substrate is removed to obtain a sample. Not only is the sample preparation time shortened, but also the loss of the crystal rod is reduced.

[0027] The sample for resistivity measurement provided by the present invention and the method for preparing the sample for resistivity measurement provided by the present invention belong to the same inventive concept. Therefore, the sample for resistivity measurement provided by the present invention has at least all the advantages of the method for preparing the sample for resistivity measurement provided by the present invention. Multiple samples with different resistivities prepared by the above-mentioned preparation method can reduce the loss of crystal rods. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a flow chart of a method for preparing a sample for resistivity measurement in one embodiment of the present invention;

[0029] Figure 2 is a schematic structural diagram of a substrate in one embodiment of the present invention;

[0030] Figure 3 It is a schematic diagram of a structure in which an epitaxial layer is formed on a substrate in one embodiment of the present invention;

[0031] Figure 4 is a schematic structural diagram of a sample in one embodiment of the present invention;

[0032] Figure 5 is a schematic structural diagram of forming an epitaxial layer on a substrate in another embodiment of the present invention;

[0033] Figure 6 is a schematic structural diagram of a sample in another embodiment of the present invention;

[0034] In the figure,

[0035] 100-substrate; 200-epitaxial layer;

[0036] 210 - first epitaxial layer; 220 - second epitaxial layer;

[0037] 300-Oxide layer. DETAILED DESCRIPTION

[0038] In order to make the purpose, advantages and features of the present invention clearer, the sample for resistivity measurement and its preparation method proposed by the present invention are further described in detail in combination with the drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. It should be understood that the drawings in the specification do not necessarily show the specific structure of the present invention in proportion, and the illustrative features used to illustrate certain principles of the present invention in the drawings in the specification will also adopt a slightly simplified drawing method. The specific design features of the present invention disclosed herein include, for example, specific dimensions, directions, positions and shapes, which will be determined in part by the specific application and use environment. And, in the embodiments described below, sometimes the same figure mark is used in common between different drawings to represent the same part or a part with the same function, and its repeated description is omitted. In this specification, similar numbers and letters are used to represent similar items, so once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0039] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0040] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0041] In the prior art, when measuring the resistivity of a silicon wafer, a series of crystal rods with different resistivities need to be pulled. After the crystal rods are pulled, they need to be ground and polished, which not only increases the time for resistivity measurement, but also causes the problem of high crystal rod loss.

[0042] The core idea of ​​the present invention is to provide a method for preparing a resistivity measurement sample, which can shorten the resistivity measurement time of a silicon wafer and reduce the loss of a crystal rod.

[0043] In order to realize the above idea, the present invention provides a method for preparing a resistivity measurement sample. Figures 1 to 3 A specific implementation of a method for preparing a resistivity measurement sample is disclosed. The method for preparing a resistivity measurement sample includes the following steps S1 to S3.

[0044] Step S1 : providing a crystal rod, cutting the crystal rod into a plurality of silicon wafers, and using the silicon wafers as substrates 100 , wherein the substrate 100 has a first surface 110 and a second surface 120 .

[0045] Specifically, refer to Figure 1 and Figure 2 As shown, a crystal rod is provided, which has been subjected to grinding, polishing and other treatments. The crystal rod is cut into a number of silicon wafers. When measuring the resistivity of the silicon wafer, a plurality of silicon wafers with different resistivities are required. Therefore, according to actual needs, when the number of silicon wafers to be measured for resistivity is determined, the crystal rod can be cut into the actual required number according to actual needs. The silicon wafer can have different sizes, for example, 8 inches, 12 inches, etc. In this embodiment, no specific requirements are made for the size and thickness of the silicon wafer, as long as the requirements of the machine for measuring resistivity can be met. Taking a 12-inch silicon wafer as an example, in order to meet the requirements of the resistivity measuring machine, the thickness of a 12-inch silicon wafer is generally between 700μm and 800μm. That is, the thickness of the silicon wafer can be 700μm, 750μm, 800μm, or any thickness value within the range of 700μm to 800μm. The cut silicon wafer is used as a substrate 100. The substrate 100 has the following Figure 2 The arrows in the middle indicate the first surface 110 and the second surface 120. According to the resistance classification, the substrate 100 can be an N-type doped resistance silicon wafer, a P-type doped resistance silicon wafer, a multi-layer resistance silicon wafer with P-type and N-type alternate distribution, a heavily doped low resistance silicon wafer, or an intrinsic high resistance silicon wafer.

[0046] Step S2: forming a doped epitaxial layer 200 on the first surface of the substrate. When forming the epitaxial layer 200 , epitaxial layers 200 with different resistivities are formed on at least one substrate 100 by controlling the type and flow rate of the doping gas.

[0047] Specifically, refer to Figures 1 to 3 , Figure 5As shown, an epitaxial layer 200 is formed on the first surface 110 of the substrate 100 by an epitaxial process. When forming the epitaxial layer 200, a series of epitaxial layers 200 with different resistivities are formed by controlling the type and flow of doping. And the doping type of the substrate 100 can be the same as that of the epitaxial layer 200, or it can be different. That is, when the substrate 100 is an N-type semiconductor doped with phosphorus, arsenic, etc., the epitaxial layer 200 can be a P-type semiconductor doped with boron, aluminum, etc., or it can be an N-type semiconductor doped with phosphorus, arsenic, etc. The epitaxial layer 200 is made of the same material as the substrate 100, which is silicon.

[0048] As one embodiment, forming the epitaxial layer 200 on the first surface 110 of the substrate 100 includes:

[0049] A single epitaxial layer is formed on the first surface 110 of the substrate 100, and the single epitaxial layer is doped with the same impurity. The thickness of the single epitaxial layer is greater than or equal to 700 μm. The types of doping in the epitaxial layer include any one or a combination of two or three of borane (B2H6), phosphine (PH3) and arsine (AsH3). When forming the epitaxial layer, the flow rate of the doping gas is 0 to 500 sccm, and the resistivity of the sample is 0 to 2000 ohm.cm. Under the condition of doping with the same gas, the greater the flow rate of the doped gas, the smaller the resistivity of the epitaxial layer.

[0050] As another embodiment, forming the epitaxial layer 200 on the first surface 110 of the substrate 100 includes:

[0051] A plurality of epitaxial layers are formed on the first surface 110 of the substrate 100 to measure the resistivity of the plurality of epitaxial layers along the depth direction. By controlling the type of doping gas and the flow rate of the doping gas, the resistivity of each epitaxial layer formed is different. The total thickness of the plurality of epitaxial layers is greater than or equal to 700 μm. The gas types doped in the epitaxial layers include any one or a combination of two or three of borane (B2H6), phosphine (PH3) and arsine (AsH3). When forming each epitaxial layer, the flow rate of the doping gas is 0 to 500 sccm, and the resistivity of the sample is 0 to 2000 ohm.cm. The plurality of epitaxial layers may include, for example, Figure 5 The two epitaxial layers shown include a first epitaxial layer 210 and a second epitaxial layer 220, and may also include three epitaxial layers or more. Figure 5 Taking the two epitaxial layers formed in the embodiment as an example, the doping types in the first epitaxial layer 210 and the second epitaxial layer 220 may be the same or different. When the first epitaxial layer 210 and the second epitaxial layer 220 are doped with the same impurity, the resistivity of the first epitaxial layer 210 and the second epitaxial layer 220 is different by controlling the doping gas flow rate when forming the first epitaxial layer 210 and the second epitaxial layer 220.

[0052] Due to the diffusion of impurity atoms in the high temperature process, different resistance layers will have mutual influence, and the resistivity difference between the substrate 100 and the epitaxial layer 200 is large, especially when the resistivity of the epitaxial layer 200 is above 100ohm.cm. When it presents a high resistivity, slight impurity doping can cause resistance abnormality. The epitaxial process needs to pass the LTO (Low Temperature Oxide) back-sealing process on the back of the substrate to form an oxide layer 300 on the second surface 120 of the substrate to reduce the doping effect of the substrate 100. That is, before forming the epitaxial layer 200, the preparation method also includes:

[0053] An oxide layer 300 is formed on the second surface 120 of the substrate 100. The oxide layer 300 is made of silicon dioxide, and the thickness of the silicon dioxide deposition is greater than or equal to

[0054] Step S3: removing the substrate 100 to obtain a sample.

[0055] Specifically, refer to Figures 1 to 6 By using one of the processes of grinding, polishing, etching, etc., or by combining the above processes, the substrate 100 is completely removed to obtain a silicon wafer including only the epitaxial layer 200, forming a sample. When a single epitaxial layer is formed on the first surface 110 of the substrate 100, after removing the substrate 100, a silicon wafer as shown in FIG. Figure 4 The sample shown in FIG. 1 includes only a single epitaxial layer. When multiple epitaxial layers are formed on the first surface 110 of the substrate 100, after removing the substrate 100, the following is formed: Figure 6 The sample shown. The substrate 100 is removed, and obtaining the sample further includes: removing the oxide layer 300.

[0056] When the resistance difference between the substrate 100 and the epitaxial layer 200 is large, or the conductive P-type and N-type are different, there will be a resistance gradient transition zone and a PN junction carrier depletion high resistance zone, which will affect the calibration resistance. Therefore, when the back substrate is removed by grinding, polishing or etching, part of the epitaxial layer needs to be further removed to ensure the resistance stability. When the substrate is removed, the preparation method also includes:

[0057] The epitaxial layer 200 on the side close to the substrate 100 is removed by 10 to 20 μm. That is, the epitaxial layer 200 is thinned by 10 to 20 μm.

[0058] Embodiment 1

[0059] The process of obtaining a P-type epitaxial doped sample with a resistivity of 175 ohm.cm:

[0060] Select a 12-inch P-type single crystal silicon wafer with a thickness of 775μm. The resistivity of the silicon wafer is 0.01ohm.cm. First, grow Thickness or thickness greater than The oxide layer 300 is used to prevent the diffusion of substrate impurities;

[0061] A doping gas cylinder with borane concentration of 100ppm was selected and the doping gas flow rate was 25sccm to pass into the epitaxial furnace, and a resistive type P-type epitaxial layer with a resistivity of 175ohm.cm was obtained.

[0062] The single crystal silicon wafer and the oxide layer 300 are removed by grinding, polishing and other processes to obtain a P-type epitaxially doped sample with a resistivity of 175 ohm.cm.

[0063] Embodiment 2

[0064] The process of obtaining a double-layer epitaxial doping sample with a resistivity of 10 ohm.cm and a P-type and N-type interval distribution:

[0065] A 12-inch P-type single crystal silicon wafer is selected, the thickness of the silicon wafer is 775 μm, and the resistivity of the silicon wafer is 10 ohm.cm.

[0066] A doping gas cylinder with phosphine concentration of 20ppm is selected, and a doping gas flow rate of 150sccm is introduced into the epitaxial furnace, so that a resistance type N-type epitaxial layer with a resistivity of 10ohm.cm can be obtained as the first epitaxial layer.

[0067] A doping gas cylinder with borane concentration of 100ppm is selected and a doping gas flow rate of 100sccm is passed into the epitaxial furnace to obtain a resistance type P-type epitaxial layer with a resistivity of 10ohm.cm as the second epitaxial layer.

[0068] The single crystal silicon wafer is removed by grinding, polishing and other processes to obtain a double-layer epitaxial doped sample with a resistivity of 10 ohm.cm and a P-type and N-type alternate distribution.

[0069] In this embodiment, a crystal rod is cut into several silicon wafers as the substrate 100, and an epitaxial layer 200 with different resistivities is formed on the substrate 100. Finally, the substrate 100 is removed to obtain a sample. The sample provided in this embodiment is a sample including only the epitaxial layer 200. By adjusting the type of epitaxial doping gas and the doping gas flow rate, any resistivity can be obtained. Compared with the pulling method, the resistance control is simple and convenient, and has obvious advantages in terms of consumption cost and cycle time.

[0070] To realize the above idea, this embodiment also discloses a sample for resistivity measurement, including: preparing a plurality of samples with different resistivities by using the preparation method as described above.

[0071] The sample for resistivity measurement provided in this embodiment and the method for preparing the sample for resistivity measurement provided in this embodiment belong to the same inventive concept. Therefore, the sample for resistivity measurement provided in this embodiment has at least all the advantages of the method for preparing the sample for resistivity measurement provided in this embodiment. A plurality of samples with different resistivities prepared by the above-mentioned preparation method can reduce the loss of the crystal rod.

[0072] In summary, the above embodiments provide detailed descriptions of different configurations of samples for resistivity measurement and preparation methods thereof. Of course, the above description is only a description of preferred embodiments of the present invention, and is not any limitation to the scope of the present invention. The present invention includes but is not limited to the configurations listed in the above embodiments. Those skilled in the art can draw inferences based on the contents of the above embodiments. Any changes and modifications made by those of ordinary skill in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for preparing a resistivity measurement sample, characterized in that: include: Providing a crystal rod, cutting the crystal rod into a plurality of silicon wafers, and using the silicon wafers as substrates, wherein the substrate has a first surface and a second surface; forming a doped epitaxial layer on the first surface of the substrate, and when forming the epitaxial layer, forming epitaxial layers with different resistivities on at least one substrate by controlling the type and flow rate of the doping gas; The substrate is removed to obtain a sample.

2. The method for preparing a resistivity measurement sample according to claim 1, characterized in that: Before forming the epitaxial layer, the preparation method further comprises: forming an oxide layer on the second side of the substrate; The substrate is removed and the sample is obtained further comprising: The oxide layer is removed.

3. The method for preparing a resistivity measurement sample according to claim 2, characterized in that: The material of the oxide layer is silicon dioxide, and the thickness of the silicon dioxide deposition is greater than or equal to 4. The method for preparing a resistivity measurement sample according to claim 1, characterized in that: The forming of an epitaxial layer on the first surface of the substrate comprises: A single epitaxial layer is formed on the first surface of the substrate, and the single epitaxial layer is doped with the same impurity.

5. The method for preparing a resistivity measurement sample according to claim 1, characterized in that: The forming of an epitaxial layer on the first surface of the substrate comprises: A plurality of epitaxial layers are formed on the first surface of the substrate, and the resistivity of each epitaxial layer is different by controlling the type of doping gas and the flow rate of the doping gas.

6. The method for preparing a resistivity measurement sample according to claim 1, characterized in that: The thickness of the epitaxial layer is greater than or equal to 700 μm.

7. The method for preparing a resistivity measurement sample according to claim 1, characterized in that: The gas species for doping the epitaxial layer include any one of borane, phosphine and arsine or a combination of two or three thereof.

8. The method for preparing a resistivity measurement sample according to claim 1, characterized in that: When forming the epitaxial layer, the flow rate of the doping gas is 0 to 500 sccm.

9. The method for preparing a resistivity measurement sample according to claim 1, characterized in that: When the substrate is removed, the preparation method further comprises: 10 to 20 μm of the epitaxial layer close to the substrate is removed.

10. A sample for resistivity measurement, characterized in that: include: A plurality of samples with different resistivities are prepared by the preparation method according to any one of claims 1 to 9.

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