Write-in method of ferroelectric field effect transistor array

Abstract

The invention discloses a writing method of a ferroelectric field effect transistor array, and belongs to the technical field of micro-nano electronics. According to the method, a self-compensation write-in method is provided for a multi-stage storage ferroelectric field effect transistor array of a 1T structure, a pulse sequence of a self-compensation waveform is adopted for write-in and corresponds to different storage states in multi-stage storage, positive pulse write-in is adopted when the pulse sequence is higher than an intermediate storage state, and negative pulse write-in is adopted when the pulse sequence is lower than the intermediate storage state. The method comprises the following steps of: writing a FeFET memory cell, performing read verification on a written state of the FeFET memory cell, starting an error correction program for correction when a write error is found so as to reach a target state, and starting a durability recovery program to recover the performance of the FeFET memory device if the error correction program fails; the method simultaneously solves the reliability problems of large fluctuation between devices and between cycles, limited durability and serious write-in crosstalk, has the advantages of simple process, low hardware overhead and the like, is compatible with the current advanced node CMOS technology, and is easy to implement.

Description

Technical Field

[0001] The invention belongs to the technical field of micro-nano electronics, and in particular relates to a writing method for a ferroelectric field effect transistor (FeFET) array. Background Art

[0002] With the advent of the post-Moore era, new technologies such as artificial intelligence, the Internet of Things, autonomous driving, and cloud computing are developing rapidly, and the total amount of global data is surging year by year, which has put forward higher requirements for data storage and efficient processing. When processing data, a large amount of data needs to be frequently moved between computing units and storage units at all levels, which restricts the further improvement of computing power and brings serious power consumption bottlenecks. The root cause of this is that traditional storage units cannot simultaneously achieve the requirements of non-volatility, high storage density, and high-speed data access, which in turn severely limits the storage and efficient processing capabilities of massive data. Therefore, there is an urgent need to develop new non-volatile storage devices with high speed, high integration density, and low power consumption.

[0003] Among the many new non-volatile memory device candidates, hafnium oxide-based ferroelectric field-effect transistors (FeFETs) have great development prospects due to their ultra-low power consumption, high speed, miniaturization potential, and multi-level storage potential. However, FeFETs still face serious reliability issues, including fluctuations between devices (D2D) and between cycles (C2C), limited durability, and severe write crosstalk problems in 1T structure arrays. These reliability issues become more serious when FeFETs are extended to multi-level storage, that is, storing multiple bits of information in one unit. Any of the above reliability issues may become a bottleneck limiting the future application of FeFETs, and therefore need to be solved at the same time.

[0004] Most of the past research work focused on optimizing reliability issues from the perspective of device structure or materials. In recent years, the academic community has begun to pay attention to reliability improvement routes based on operation methods, such as target programming, durability recovery, and V w / 2 or V w / 3 writing method, etc. However, at this stage, there is still a lack of in-depth research on array operation methods, and the reliability of FeFET arrays needs to be further improved, especially in terms of write crosstalk. In addition, existing work is limited to solving reliability problems from a single angle and lacks comprehensive optimization of reliability. Integrating the proposed optimization methods into a compact and mutually compatible operation method is indispensable for the realization of FeFET arrays. Summary of the invention

[0005] In view of the problems existing in the above-mentioned prior art, the present invention proposes a writing method for a ferroelectric field effect transistor (FeFET) array. For a multi-level storage ferroelectric field effect transistor array with a 1T structure, self-compensating writing, an error correction program, and a durability recovery program are adopted, and the reliability problems faced by the array, such as large fluctuations between devices (D2D) and between cycles (C2C), limited durability, and severe write crosstalk, are solved at the same time. The method has the advantages of simple process and low hardware overhead, and is compatible with the current advanced node CMOS technology and is easy to implement.

[0006] The technical solution of the present invention is as follows:

[0007] A method for writing a ferroelectric field effect transistor (FeFET) array, wherein the FeFET array is a multi-level storage array of a 1T structure composed of FeFET storage cells, word lines, bit lines and source lines, wherein FeFET storage cells in the same row share the same word line, and FeFET storage cells in the same column share the same bit line and source line, and wherein during the writing process of the FeFET array, a pulse sequence of alternating positive and negative voltage pulses of a self-compensating waveform is used for writing, and a read verification is performed on the state of the FeFET storage cell after writing, and when a write error is found, an error correction program is started to correct it to achieve a target state, and if the error correction program fails, a durability recovery program is started to restore the performance of the FeFET storage device; the method comprises the following steps:

[0008] 1) Initializing the FeFET array and setting each FeFET storage unit to an intermediate storage state;

[0009] 2) writing the FeFET array row by row using a pulse sequence of a self-compensating waveform, wherein the pulse sequence of the self-compensating waveform is a pulse sequence of alternating positive and negative voltage pulses, and the absolute values ​​of the amplitudes of adjacent positive and negative voltage pulses are substantially equal;

[0010] When writing each row, a pulse sequence of the self-compensating waveform is used, that is, positive and negative voltage pulses are written alternately, corresponding to different storage states in the multi-level storage, and a storage state higher than the middle storage state is written by a positive pulse, while a storage state lower than the middle storage state is written by a negative pulse; the writing sequence is: first write the highest storage state, i.e., the positive pulse, then write the lowest storage state, i.e., the negative pulse, then write the second highest storage state, i.e., the positive pulse, then write the second lowest storage state, i.e., the negative pulse, then write the third highest storage state, i.e., the positive pulse, then write the third lowest storage state, i.e., the negative pulse, and write different storage states in sequence.

[0011] Furthermore, the step 1) initializes the FeFET array by first erasing the entire array to place each FeFET memory cell in the lowest state, then selecting all word lines of the array, applying programming pulses corresponding to the intermediate storage state on the word lines, and grounding all bit lines and source lines at the same time, thereby placing all FeFET memory cells in the array in the intermediate storage state to complete initialization.

[0012] Further, when writing to a row of the FeFET array in step 2), writing is performed in sequence according to the order of the different storage states, and the writing step of each storage state includes:

[0013] 2-1) writing a positive / negative pulse corresponding to the current state to the FeFET storage unit to be written in the row;

[0014] 2-2) Perform post-write read verification on the FeFET storage unit being written: if the verification write passes, the current state is written successfully; if the verification write fails, proceed to step 2-3) start the error correction program to correct the written state to achieve the target state;

[0015] 2-3) Start the error correction program to correct the written state: if the error correction passes and reaches the target state, the current state is written successfully; if the error correction fails, go to step 2-4) to start the durability recovery program;

[0016] 2-4) Starting the durability recovery program, after restoring the performance of the FeFET memory device, re-writing the pulse corresponding to the current state into the restored FeFET memory device, repeating step 2-2) until the current state is successfully written.

[0017] Furthermore, when writing to the FeFET array row by row in the step 2), the word line corresponding to each row is selected respectively, and writing is performed on the row.

[0018] Furthermore, when writing to a row of the FeFET array in the step 2), the FeFET memory cells storing the same storage state in the row are written simultaneously: a corresponding write pulse is applied to the word line corresponding to the selected row, and the bit line and source line corresponding to the memory cell to be written are grounded. At the same time, a voltage pulse with an amplitude of 1 / 2 of the write pulse amplitude is applied to the bit line and source line of other unselected memory cells in the row and the word line corresponding to other unselected rows to suppress write crosstalk.

[0019] Further, the write-after-read verification in step 2-2) is used to check whether the storage state of the FeFET storage unit meets the requirements after writing to the FeFET storage unit, by measuring the I d -V gThe threshold voltage is extracted from the curve and tested to see whether it is within the threshold range.

[0020] Furthermore, the error correction program of step 2-3) is used to correct the erroneous storage state; when a write error is detected, according to whether the erroneous threshold state is higher than the upper limit or lower than the lower limit relative to the threshold interval, an increasing or decreasing pulse sequence with a certain step size is selected for rewriting; when the threshold voltage exceeds the upper limit of the threshold interval, an increasing positive pulse sequence is used for error correction, and each time the step size is increased based on the previous pulse amplitude and rewriting is performed, and a read verification is performed after each writing until the threshold voltage is within the correct interval, and the error correction program is stopped; similarly, when the threshold voltage is less than the lower limit of the threshold interval, a decreasing negative pulse sequence is used for rewriting until the threshold voltage reaches the correct interval; a limit is set for the number of pulses of the pulse sequence for error correction. If the erroneous storage state is not restored after exceeding this limit, it is determined that the error correction program has failed and the durability recovery program needs to be started.

[0021] Furthermore, the durability recovery procedure of step 2-4) is used to restore the performance of the FeFET device degraded after cycling; according to the actual device characteristics, a relatively large negative voltage pulse is applied to the gate of the FeFET, and the trapped electrons accumulated in the cycle are decaptured, thereby recovering the threshold voltage drift caused by the cycling process; the absolute value of the selected recovery voltage pulse amplitude is 6 to 10V, and the pulse width is 10μs to 1ms.

[0022] The technical effects of the present invention are as follows:

[0023] 1. In the proposed new FeFET array writing method, by adopting an error correction method, if a write error is detected after each write, error correction is performed to adjust its threshold voltage to achieve the correct storage state, thereby effectively avoiding write errors caused by D2D or C2C fluctuations of FeFET storage cells and reducing the error rate of FeFET memory. Compared with the conventional target programming method, the proposed error correction method has the advantages of low time cost and simple operation.

[0024] The error correction method proposed in the present invention uses an increasing or decreasing pulse sequence to correct the wrong storage state. If it is detected that the threshold voltage exceeds the upper limit of the threshold interval, a positive pulse sequence with a voltage increase (fixed step length) is used for error correction, and the amplitude of a step is increased on the basis of the previous pulse each time and re-written. Due to the increase in amplitude, the polarization intensity pointing to the channel direction in the FeFET ferroelectric layer increases, and the influence of the polarization charge on the channel potential is more significant, and the threshold voltage is reduced. After each write pulse, read verification, once the threshold voltage returns to the correct interval, the error correction is stopped. Correspondingly, if the threshold voltage is detected to be less than the lower limit of the threshold interval, a negative pulse sequence with a voltage decrease (fixed step length) is used for error correction. Due to the increase in the negative pulse amplitude, the polarization intensity pointing to the gate direction in the FeFET ferroelectric layer increases, so the threshold voltage increases.

[0025] 2. In the proposed new FeFET array writing method, a durability recovery method is adopted to perform durability recovery after the FeFET becomes fatigued due to an increase in the number of cycles (i.e., the number of writes), so that the degraded device performance is restored, thereby further extending the durability of the FeFET.

[0026] As the number of FeFET cycles increases, the electrons captured by the interface traps in the FeFET gradually accumulate, and the shielding effect on the polarization charge of the ferroelectric layer increases, which causes the threshold voltage of the highest storage state of the FeFET to gradually shift to the negative direction. At the same time, it is also observed that the D2D and C2C fluctuations of the FeFET gradually increase. The increase in the shift and fluctuation of the threshold voltage causes the error rate of the FeFET to gradually increase with the number of cycles, which may cause the error correction program to fail. When the error correction program failure is detected, the durability recovery program is started: by applying a negative voltage pulse with a large amplitude and pulse width to the gate of the FeFET, the electrons accumulated during the cycle are decaptured, so that the threshold voltage of the highest storage state shifts to the positive direction and the storage performance is restored.

[0027] 3. In the proposed new FeFET writing method, a novel self-compensation writing method is proposed. Compared with the traditional writing method, the adopted self-compensation waveform causes the write crosstalk to other unselected cells in the FeFET array to cancel each other during each writing, thereby suppressing the accumulation of write crosstalk.

[0028] In the traditional writing method, the FeFET memory array is first completely erased to the lowest storage state, and then programmed row by row. When programming each row, only increasing positive voltage pulses are used for programming, which results in a positive write crosstalk being applied to other FeFET memory cells in the array each time programming occurs. The write crosstalk gradually accumulates, causing the threshold voltage of the FeFET memory cell to shift. In the proposed self-compensation writing method, the FeFET array is first initialized to an intermediate state, and then written row by row. When writing each row, a pulse sequence of alternating positive and negative voltage pulses is used for writing, which results in the write crosstalk to the unselected cells also alternating between positive and negative each time writing, and the absolute values ​​of the amplitudes are basically equal, so the write crosstalks cancel each other out, thereby suppressing the shift of the threshold voltage and reducing the write crosstalk.

[0029] Fourth, in the novel FeFET array writing method proposed in the present invention, the error correction procedure, durability recovery procedure and self-compensation programming waveform are compatible with each other and can be implemented in a single workflow, while solving the reliability problems faced by FeFET, such as large D2D and C2C fluctuations, limited durability and severe write crosstalk. At the same time, the proposed novel FeFET array writing scheme is easy to operate, has a compact process, and can be implemented with a simple circuit design, with low hardware overhead for peripheral circuits. The present invention lays the foundation for the development of high-reliability FeFET memory arrays. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 In the figure, (a) is a schematic diagram of a multi-level storage FeFET array of a 1T structure, and (b) is a schematic diagram of a work flow of a writing method of a ferroelectric field effect transistor array according to an embodiment of the present invention;

[0031] Figure 2 1 is a waveform diagram comparing a conventional FeFET array writing method according to an embodiment of the present invention and a FeFET array automatic compensation writing method according to the present invention;

[0032] Figure 3 is the error correction procedure and result of an embodiment of the present invention, wherein:

[0033] (a) is a pulse sequence used for error correction procedures, including an increasing positive pulse sequence and a decreasing negative pulse sequence;

[0034] (b) D2D and C2C fluctuations of FeFET extracted before and after error correction in the initial state and the calculated error rate;

[0035] (c) After 10 3 After cycles, the extracted D2D and C2C fluctuations of the FeFET before and after error correction and the calculated error rate;

[0036] Figure 4 Schematic diagram of the durability recovery procedure and results of an embodiment of the present invention, wherein:

[0037] (a) is a schematic diagram of the operation of the endurance recovery procedure. After the error correction procedure fails, a negative voltage pulse of -9 V, 100 μs is used for endurance recovery;

[0038] (b) is two durability recovery processes before and after the durability recovery process according to the embodiment of the present invention;

[0039] (c) is a graph of the FeFET of the present invention after 10 6 After durability cycles and after durability recovery treatment, I d -V g curve;

[0040] (d) is the change of threshold voltage with cycle number of FeFET in the embodiment of the present invention after configuring the durability recovery program. After configuring the durability recovery program, the durability of FeFET is improved to more than 10 8 Secondary cycle;

[0041] (e) is the variation of error rate and D2D and C2C fluctuations with cycle number of the FeFET according to the embodiment of the present invention after configuring the durability recovery program and the error correction program;

[0042] Figure 5 The figure is a comparison of the write crosstalk between the self-compensation write method and the conventional write method in the 6×6 FeFET array prepared in the embodiment of the present invention, wherein:

[0043] (a) is a schematic diagram of specific waveforms of the self-compensation writing method according to an embodiment of the present invention;

[0044] (b) is a specific waveform diagram of a conventional writing method for comparison in an embodiment of the present invention;

[0045] (c) is a comparison of the threshold voltage offsets of each storage cell in the first row in a 6×6 FeFET array prepared in an embodiment of the present invention after the entire array is written using the self-compensating writing method of the present invention and the traditional writing method based on a randomly generated state table. DETAILED DESCRIPTION

[0046] The present invention will be further described below by way of examples in conjunction with the accompanying drawings.

[0047] 1T structure multi-level storage FeFET array Figure 1 As shown in (a), FeFET memory cells in the same row share the same word line, while FeFET memory cells in the same column share the same bit line and source line. Figure 1 As shown in (b), it includes self-compensation write waveform, post-write read verification, error correction program, durability recovery program, etc. In actual operation, the entire FeFET memory array is first initialized to an intermediate state, that is, between the 01 state and the 10 state, and then written row by row. When writing a row, write in the order of 11, 00, 10 and 01. After each writing of the current state, a post-write read verification is performed to extract the threshold voltage of the FeFET. If it is in the correct threshold voltage interval, it means that the write is correct and continue to write the next storage state; if it is not in the correct threshold voltage interval, it means that the write is wrong, and the error correction program is started for correction. If the error correction program passes, the writing of the next storage state continues, otherwise the durability recovery program continues to be started to recover the erroneous FeFET storage unit. Correspondingly, the error correction program can reduce the D2D and C2C fluctuations of the FeFET, the durability recovery program can extend the durability of the FeFET, and the self-compensation waveform can suppress the write crosstalk of the array.

[0048] The novel self-compensation writing method of the present invention is compared with the conventional writing method. Figure 2 As shown, in the traditional writing method, only positive voltage pulses are used for programming, which will cause the accumulation of write crosstalk. In the self-compensating writing method, since positive and negative voltage pulses are used alternately for writing, the polarity of the crosstalk during each writing is opposite and the magnitude is similar. Therefore, the write crosstalk compensates each other, which can effectively suppress the write crosstalk.

[0049] like Figure 3 As shown in (a), the error correction procedure in the embodiment of the present invention includes two types of pulse sequences. If the detected threshold voltage is greater than the upper threshold limit, an increasing positive pulse sequence with a step size of +0.1V is used for error correction; if the detected threshold voltage is less than the upper threshold limit, a decreasing negative pulse sequence with a compensation of -0.1V is used for error correction. Each error correction pulse contains at most 10 correction pulses. If the threshold voltage of the FeFET storage unit still does not return to the correct threshold interval after 10 correction pulses, it means that the error correction procedure has failed. The initial state and after 10 correction pulses 3 The D2D and C2C fluctuations of the FeFET extracted after the endurance cycle before and after error correction and the calculated error rate are shown in Figure 2. Figure 3 (b) and Figure 3 (c) In the initial state, the error rate of FeFET before error correction is about 0.725%, and after the error correction process, the error rate of FeFET is reduced to about 0.02%; 10 3After the endurance cycle, the error rate of FeFET before error correction was about 2.1%, and after the error correction procedure, the error rate of FeFET was reduced to about 0.5%. The significant reduction in the error rate of FeFET after error correction proves that the error correction procedure of the embodiment of the present invention can effectively suppress the storage state error caused by the D2D and C2C fluctuations of FeFET.

[0050] The durability recovery process of the embodiment of the present invention is as follows Figure 4 As shown in (a), after a certain number of durability cycles, due to the degradation of device performance, read verification errors may occur and the error correction program may fail. At this time, the durability recovery program is started, and a negative voltage pulse of -9V, 100μs is used for durability recovery, and then the durability cycle is continued. The two durability fatigue processes of the FeFET of the embodiment of the present invention before and after the durability recovery are shown in FIG. Figure 4 As shown in (b), after the durability recovery treatment, the error rate of the FeFET is reduced to the same as the initial state, and the two durability fatigue processes are almost completely consistent, which shows that the durability recovery procedure can completely restore the storage performance of the FeFET that has been degraded due to the accumulation of cycle times. 6 After durability cycles and after durability recovery treatment, I d -V g Curve like Figure 4 As shown in (c), after durability recovery, the I corresponding to state 11 d -V g The curve shifts toward the negative direction of the x-axis and returns to the position at the initial state. This is mainly because the large negative voltage pulse applied during the durability recovery causes the electrons accumulated in the interface traps during the cycle to be decaptured. The change in threshold voltage of the FeFET of the embodiment of the present invention with the durability recovery program as the number of cycles is shown in FIG. Figure 4 As shown in (d), by every 10 6 After a durability cycle, a durability recovery pulse is applied as a cycle. After 100 cycles, the threshold voltage of each state of FeFET has no obvious shift, which shows that after configuring the durability recovery program, the durability of FeFET can be improved to more than 10 8 The error rate and the fluctuations of D2D and C2C of the FeFET according to the embodiment of the present invention after configuring the durability recovery program vary with the number of cycles. Figure 4 As shown in (e), the error rate of FeFET is reduced from 6% to 0.8% after the durability recovery procedure, and further reduced to 0.4% after the configuration error correction procedure. 8 The value of D2D and C2C of FeFET remains low at about 0.4% within the first cycle. In addition, the fluctuations of D2D and C2C of FeFET remain almost unchanged during the cycle after durability recovery. This further shows that the durability of FeFET can be improved to more than 108 Second cycle.

[0051] A specific waveform diagram of the self-compensation writing method according to an embodiment of the present invention is shown in FIG. Figure 5 As shown in (a), the entire array is first erased to the 00 state, and then a suitable positive voltage pulse is applied to initialize all FeFET memory cells to the intermediate state. Then, write is performed row by row. When writing a row, the corresponding positive and negative voltage pulses are applied alternately to the selected word line WL in the order of 11, 00, 10 and 00 states, and the voltage of the selected bit line BL is 0. At the same time, a voltage pulse with an amplitude of half the amplitude of the write pulse is applied to the unselected word line WL and bit line BL to suppress the write crosstalk to the unselected cells, which is the conventionally used V w / 2 suppression scheme. Each time a state is written, the I d -V g Curve, extract V th After completing one row of writing, the next row of writing is performed until the entire array is written. Finally, the threshold voltage of the FeFET storage unit in the first row is read again to check the write crosstalk. The specific waveform of the traditional writing method is as follows Figure 5 As shown in (b), the entire array is first erased to the 00 state, and then written row by row. When writing a row, the corresponding positive voltage pulses are used to write in the order of 01, 10, and 11 states, and V is used on the unselected WL and BL. w / 2 suppression scheme is used to suppress write crosstalk. After completing the writing of one row, continue writing the next row until the entire array is written. Similarly, read the threshold voltage of the FeFET storage unit in the first row to check the write crosstalk. The results after writing using the self-compensation writing method of the embodiment of the present invention and the traditional method are shown in Figure 2. Figure 5 As shown in (c), when the traditional writing method is used, the FeFET has a serious threshold voltage offset, especially the 00 state, which is due to the accumulation of write crosstalk in the traditional writing method; when the self-compensation writing method is used, there is almost no threshold voltage offset in each storage state of the FeFET, which is because the self-compensation writing waveform makes the write crosstalk cancel each other. Therefore, the self-compensation writing method of the embodiment of the present invention can effectively suppress the write crosstalk in the FeFET array.

[0052] Finally, it should be noted that the purpose of publishing the embodiments is to help further understand the present invention, but those skilled in the art can understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the contents disclosed in the embodiments, and the scope of protection claimed by the present invention shall be subject to the scope defined in the claims.

Claims

1. A writing method for a FeFET array, wherein the FeFET array is a multi-level storage array of a 1T structure composed of FeFET storage cells, word lines, bit lines and source lines, wherein the FeFET storage cells in the same row share the same word line, and the FeFET storage cells in the same column share the same bit line and source line, characterized in that: In the writing process of the FeFET array, a pulse sequence of alternating positive and negative voltage pulses of a self-compensating waveform is used for writing, and the state of the FeFET storage unit after writing is read and verified. When a write error is found, an error correction program is started to correct it to achieve a target state. If the error correction program fails, a durability recovery program is started to restore the performance of the FeFET storage device. The method includes the following steps: 1) Initializing the FeFET array and setting each FeFET storage unit to an intermediate storage state; 2) writing the FeFET array row by row using a pulse sequence of a self-compensating waveform, wherein the pulse sequence of the self-compensating waveform is a pulse sequence of alternating positive and negative voltage pulses, and the absolute values ​​of the amplitudes of adjacent positive and negative voltage pulses are substantially equal; When writing each row, a pulse sequence of the self-compensating waveform is used, that is, positive and negative voltage pulses are written alternately, corresponding to different storage states in the multi-level storage, and a storage state higher than the middle storage state is written by a positive pulse, while a storage state lower than the middle storage state is written by a negative pulse; the writing sequence is: first write the highest storage state, i.e., the positive pulse, then write the lowest storage state, i.e., the negative pulse, then write the second highest storage state, i.e., the positive pulse, then write the second lowest storage state, i.e., the negative pulse, then write the third highest storage state, i.e., the positive pulse, then write the third lowest storage state, i.e., the negative pulse, and write different storage states in sequence.

2. The writing method of the FeFET array according to claim 1, characterized in that: The step 1) initializes the FeFET array by first erasing the entire array to place each FeFET memory cell in the lowest state, then selecting all word lines of the array, applying programming pulses corresponding to the intermediate storage state to the word lines, and simultaneously grounding all bit lines and source lines, thereby placing all FeFET memory cells in the array in the intermediate storage state to complete initialization.

3. The writing method of the FeFET array according to claim 1, characterized in that: When writing to a row of the FeFET array in step 2), the writing is performed in sequence according to the order of the different storage states, and the writing step of each storage state includes: 2-1) writing a positive / negative pulse corresponding to the current state to the FeFET storage unit to be written in the row; 2-2) Perform post-write read verification on the FeFET storage unit being written: if the verification write passes, the current state is written successfully; if the verification write fails, proceed to step 2-3) start the error correction program to correct the written state to achieve the target state; 2-3) Start the error correction program to correct the written state: if the error correction passes and reaches the target state, the current state is written successfully; if the error correction fails, go to step 2-4) to start the durability recovery program; 2-4) Starting the durability recovery program, after restoring the performance of the FeFET memory device, re-writing the pulse corresponding to the current state into the restored FeFET memory device, and repeating step 2-2) until the current state is successfully written.

4. The method for writing a FeFET array according to claim 1, wherein: When writing to the FeFET array row by row in the step 2), the word line corresponding to each row is selected and writing is performed on the row.

5. The method for writing a FeFET array according to claim 1, wherein: When writing to a row of the FeFET array in the step 2), the FeFET storage cells storing the same storage state in the row are written simultaneously: a corresponding write pulse is applied to the word line corresponding to the selected row, and the bit line and source line corresponding to the storage cell to be written are grounded. At the same time, a voltage pulse with an amplitude of 1 / 2 of the write pulse amplitude is applied to the bit line and source line of other unselected storage cells in the row and the word line corresponding to other unselected rows to suppress write crosstalk.

6. The writing method of the FeFET array as claimed in claim 3, characterized in that: The post-write read verification in step 2-2) is used to verify whether the storage state of the FeFET storage unit meets the requirements after writing to the FeFET storage unit, by measuring the I d -V g The threshold voltage is extracted from the curve and tested to see whether it is within the threshold range.

7. The writing method of the FeFET array according to claim 3, characterized in that: The error correction program in step 2-3) is used to correct the erroneous storage state; when a write error is detected, according to whether the threshold state of the error is higher than the upper limit or lower than the lower limit relative to the threshold interval, a pulse sequence with a certain step length of increment or decrement is selected for rewriting; When the threshold voltage exceeds the upper limit of the threshold interval, an increasing positive pulse sequence is used for error correction, and each time the step size is increased based on the previous pulse amplitude and re-written, and a read verification is performed after each write until the threshold voltage is within the correct interval, then the error correction program is stopped; Similarly, when the threshold voltage is less than the lower limit of the threshold interval, a decreasing negative pulse sequence is used for rewriting until the threshold voltage reaches the correct interval; A limit is set for the number of pulses in the pulse sequence for error correction. If the erroneous storage state is not restored after exceeding this limit, it is determined that the error correction program has failed and the durability recovery program needs to be started.

8. The method for writing into a FeFET array as claimed in claim 3, characterized in that: The durability recovery procedure of step 2-4) is used to recover the performance of the FeFET device degraded after cycling; according to the actual device characteristics, a relatively large negative voltage pulse is applied to the gate of the FeFET, and the trapped electrons accumulated in the cycle are decaptured, thereby recovering the threshold voltage drift caused by the cycling process; the absolute value of the selected recovery voltage pulse amplitude is 6 to 10V, and the pulse width is 10μs to 1ms.

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