Full-group transmission test method for autonomous controllable protection device based on common-port transmission

Abstract

The invention discloses an autonomous controllable protection device whole group transmission test method based on common port transmission, and the test system is connected in series between an acquisition execution unit and a protection device, and is responsible for decoupling GOOSE and SV messages sent by the acquisition execution unit, blocking an SV signal sent by the acquisition execution unit, and transmitting the SV signal to the protection device. The GOOSE between the protection device and the acquisition execution unit is kept in bidirectional conduction; reconstructing an SV message based on the SCD file, sending the SV message and an original GOOSE message in a common port manner, and sending the SV message and the original GOOSE message to a protection device together so as to perform a protection function test; the method has the advantages of simplicity in operation, rapidness and convenience.

Description

Technical Field

[0001] The present invention belongs to the technical field of relay protection of electric power systems, and in particular relates to a method for testing a whole group of transmission of an autonomous controllable protection device based on common port transmission. Background Art

[0002] In the SV / GOOSE common port transmission mode, when conventional test tools are used to perform a protection group transmission test, the protection device cannot obtain the actual position of the switch in real time, and cannot fully verify the protection group transmission test. The debugging personnel need to add current at the control cabinet, and a dedicated person is required to verify the protection action information at the protection screen. The present invention proposes a new test method, which automatically filters out the SV data after receiving the SV+GOOSE data sent by the acquisition execution unit, and only retains the GOOSE information. The debugging personnel only need to add current at the protection installation to carry out the protection group test, which ensures the strict real-time and time uniformity of the SV control block, while the GOOSE block has a small delay. Summary of the invention

[0003] The purpose of the present invention is to avoid the deficiencies in the prior art and to provide a whole group transmission test method of an autonomous controllable protection device based on common port transmission.

[0004] The above-mentioned object of the present invention is achieved by the following technical means: a whole group transmission test method of an autonomous controllable protection device based on common port transmission, comprising the following steps: Step 1: The acquisition execution unit is connected to the optical Ethernet port Eth0 of the autonomous controllable protection test system through optical fiber; Step 2: The protection device is connected to the optical Ethernet port Eth1 of the autonomous and controllable protection test system through an optical fiber; Step 3: Send the 100M Ethernet line speed 100Mbs at equal intervals according to the sampling rate of the SV message 4Khz, that is, send 3125 bytes every 250us, and further divide each 250us into 2 time slots, each time slot can send a maximum of 1562 bytes; the time slot controller generates an INT_4K interrupt signal to the CPU; Step 4: After receiving the SV / GOOSE message from the acquisition execution unit, the 100M optical Ethernet port Eth0 (005) of the autonomous controllable protection test system sends it to the FPGA. After receiving the SV / GOOSE message, the FPGA sends its data stream to two branches. The message of one branch is cached inside the FPGA and then sent to the CPU via Gigabit Ethernet; the message of the other branch is filtered and cached in the FPGA. Step 5: Self-generated SV message sending. After receiving the Gigabit Ethernet message, the CPU parses the message address, message type, APPID and payload information. The tester sends the configuration command through the CPU. The CPU parses the configuration command and sends the filter parameters to the FPGA through the EMA_BUS. Under the control of the INT_4K interrupt signal, the CPU generates SV data to be sent and sends it to the FPGA through the PCIE data bus in DMA mode. Step 6: The message is sent to the protection device. Step 3 divides each 250us into two equal-length time slots. The first time slot completes the reading and sending of the CPU-generated SV message, and operates in ping-pong mode during the actual sending process of the SV message, thereby ensuring the timing and integrity of the SV message. The second time slot completes the reading and sending of the BRAM cache filter message. The CPU-generated SV message and the BRAM cache filter message are both sent to the protection device through the optical Ethernet port Eth1 of the autonomous and controllable protection test system. Step 7: The message is sent to the collection and execution unit; the GOOSE message from the protection device is sent to the FPGA through the 100M optical Ethernet port Eth1 of the autonomous and controllable protection test system. After receiving the SV / GOOSE message, the FPGA sends its data stream to two branches. One branch message is cached inside the FPGA and then sent to the CPU through Gigabit Ethernet; the other branch message is forwarded to the 100M optical Ethernet port Eth0 of the autonomous and controllable protection test system through transparent transmission and reaches the collection and execution unit.

[0005] Furthermore, the optical network port is configured by the CPU to have the functions of SV message filtering, self-generated SV sending and transparent forwarding of GOOSE messages from the protection device. At the same time, it can also be configured as a common optical network port function.

[0006] Furthermore, the filtering and caching of the message in step 4 are controlled by a state machine. After the message reaches the filtering module inside the FPGA, the filtering module parses the message content, determines whether to filter, and stores the message in real time to the BRAM in the FPGA. After a frame of message parsing is completed, if the message is determined to be filtered, the BRAM write address is restored to the first address of this frame of message, the FIFO is not written, and the frame write is invalid; if the message is determined not to be filtered, the FIFO writes the first address and message length of the message, and the frame write is valid.

[0007] Furthermore, determining whether the message is filtered in step 4 includes the following steps: filtering based on the message type, after the filtering module receives the message type filtering enable signal and it is pulled high, it matches the message type flag in the message content according to the filtering type flag, and if the match is successful, it outputs a filtering effective signal; filtering based on APPID, after the filtering module receives the APPID filtering enable signal and it is pulled high, it matches the APPID in the message content according to the APPID filter word issued by the CPU, and if the match is successful, it outputs a filtering effective signal.

[0008] Compared with the prior art, the present invention has the following beneficial effects: Simple, quick and convenient operation; The message processing speed is fast and the delay is low. The maximum delay from the message filtering and forwarding processing from the acquisition execution unit to the protection device does not exceed 375us. After receiving the SV+GOOSE data sent by the acquisition execution unit, the SV data is automatically filtered out and only the GOOSE information is retained. The debugging personnel only need to increase the amount of protection to carry out the whole group test work at the protection installation site. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is the system principle diagram of the present invention; Figure 2 It is the main signal flow chart of the present invention; Figure 3 Send a flow chart for filtering messages; Figure 4 To send a timing schedule diagram; Figure 5 Sending timing diagram for filtering messages; In the figure: 001, autonomous and controllable protection test system; 002, CPU; 003, FPGA; 004, optical Ethernet port Eth1; 005, optical Ethernet port Eth0; 006, acquisition execution unit; 007, protection device; 008, EMA_BUS; 009, PCIE data bus; 012, Gigabit Ethernet. DETAILED DESCRIPTION

[0010] In order to facilitate those skilled in the art to understand and implement the present invention, the present invention is further described in detail below in conjunction with embodiments. It should be understood that the implementation examples described herein are only used to illustrate and explain the present invention and are not used to limit the present invention.

[0011] The present invention provides a whole group transmission test method of an autonomous controllable protection device based on common port transmission, such as Figure 1 , Figure 3 As shown, it includes: an acquisition execution unit (006), an autonomous controllable protection test system (001), and a protection device (007). The acquisition execution unit (006) is connected to the optical Ethernet port Eth0 (005) of the autonomous controllable protection test system (001), the protection device (007) is connected to the optical Ethernet port Eth1 (004) of the autonomous controllable protection test system (001), and the autonomous controllable protection test system (001) is mainly composed of a CPU (002) and an FPGA (003), which exchange data through a PCIE data bus (009), a Gigabit Ethernet (012) and an EMA_BUS (008); Step 1, the acquisition execution unit (006) is connected to the optical Ethernet port Eth0 (005) of the autonomous controllable protection test system through an optical fiber; Step 2, the protection device (007) is connected to the optical Ethernet port Eth1 (004) of the autonomous controllable protection test system through an optical fiber; Step 3: Send the 100M Ethernet line speed 100Mbs at equal intervals according to the sampling rate of the SV message 4Khz, that is, send 3125 bytes every 250us, and further divide each 250us into two time slots, each time slot can send a maximum of 1562 bytes; the time slot controller generates an INT_4K interrupt signal to the CPU (002); specifically, the time slot control timer starts timing at the rising edge of each PWM with a frequency of 4k, and pulls up the send enable signal of the second time slot after timing to 125us, and pulls down the send enable signal of the second time slot at the rising edge of the next PWM; Step 4: After receiving the SV / GOOSE message from the acquisition execution unit (006), the 100M optical Ethernet port Eth0 (005) of the autonomous controllable protection test system sends it to the FPGA (003). After receiving the SV / GOOSE message, the FPGA (003) sends its data stream to two branches. The message of one branch (branch 1) is cached inside the FPGA (003) and then sent to the CPU (002) via the Gigabit Ethernet (012); the message of the other branch (branch 2) is filtered and cached in the FPGA (003). Specifically, after the message of branch 1 arrives at the FPGA, it is first stored in Buffer0 together with other service messages. When Buffer0 When there is a complete data packet, it is immediately framed and sent out according to the Gigabit Ethernet standard protocol. The filtering and caching of the message in branch 2 are controlled by the state machine. After the message reaches the filtering module (RX_FILTER) inside the FPGA (003), the filtering module parses the message content and determines whether to filter it. At the same time, the message is stored in real time in the BRAM inside the FPGA (003). After the parsing of a frame of messages is completed, if the message is filtered, the BRAM write address is reset to the first address of the message in this frame, the FIFO is not written, and the frame write is invalid; if the message is not filtered, the FIFO writes the first address and message length of the message, and the frame write is valid. The signal flow of message filtering and storage is as follows: Figure 2 As shown; Determining whether a message is filtered includes the following steps: filtering based on message type, after the filtering module receives the message type filter enable signal and it is pulled high, it matches the message type flag in the message content according to the filter type flag, and if the match is successful, it outputs a filter effective signal; filtering based on APPID, after the filtering module receives the APPID filter enable signal and it is pulled high, it matches the APPID in the message content according to the APPID filter word issued by the CPU (002), and if the match is successful, it outputs a filter effective signal.

[0012] Step 5: Send the self-generated SV message. After receiving the message sent by Gigabit Ethernet (012), the CPU (002) parses the message address, message type, APPID and payload information. The tester sends a configuration command through the CPU (002). The CPU (002) parses the configuration command and sends the filter parameters to the FPGA (003) through the EMA_BUS (008). Under the control of the INT_4K interrupt signal, the CPU (002) generates SV data to be sent and sends it to the FPGA (003) in DMA mode through the PCIE data bus (009). Step 6, the message is sent to the protection device. Step 3 divides each 250us into two equal-length time slots. The first time slot completes the reading and sending of the SV message generated by the CPU (002). During the actual sending process of the SV message, it operates in ping-pong mode to ensure the timing and integrity of the SV message. The second time slot completes the reading and sending of the BRAM cache filter message. The CPU (002) self-generated SV message and the BRAM cache filter message are both sent to the protection device through the optical Ethernet port Eth1 (004) of the autonomous and controllable protection test system.

[0013] Specifically, in the first 250us cycle, the first SV data packet is cached in FIFO-0; at the beginning of the next 250us, the SV data packet of FIFO-0 will be scheduled to the optical Ethernet port Eth1 (004) in real time, and at the same time, in the second 250us cycle, the second SV data packet is moved into FIFO-1. At the beginning of the third 250us cycle, the SV data packet of FIFO-1 will be scheduled to the optical Ethernet port Eth1 (004) in real time. Subsequent self-generated SV data packets are sent in sequence according to the above process, and their timing control is as follows: Figure 4 As shown in the figure; if the size of an SV message is 300 bytes, the time taken to send 4 SV messages is 300x4*4*20ns / 0.9 =106.7us, which is less than 125us. The first time slot can complete the sending of 4 self-generated SV messages.

[0014] Specifically, the second time slot is 125us, and a time slot can send a maximum of 1562 bytes of data, that is, at least one GOOSE message can be sent in each 250us cycle; after the send enable signal of the second time slot is pulled high, the FPGA queries the empty and full flags of the filter message buffer FIFO, obtains the starting address and frame length of the frame to be sent in the time slot, and schedules the message in the corresponding BRAM space to the optical Ethernet port Eth1 (004) in real time; since the GOOSE message rate is much lower than 4K, it can be guaranteed that each GOOSE message can be sent out within the earliest first 250us cycle or the latest second 250us cycle when the FPGA receives the message, considering the following two situations: If the filtered GOOSE message has been completely stored in BRAM before the forwarding pulse TX_EN arrives, the filtered message can be sent within this PWM cycle. The theoretical message delay time is the sum of the filtered message storage time (T1) and the message storage end and forwarding time (T2). Assuming that the storage is completed and forwarded immediately, that is, T2 is 0, the delay is minimum, which is the frame storage time. Assuming that the frame length is 64Byte, the minimum delay is ((64+8)*8 / 4 / 25+0)us = 5.76us, and its timing is as follows Figure 5 shown.

[0015] If the filtered GOOSE message has not been completely stored in BRAM before the forwarding pulse arrives, the filtered message will be forwarded at the TX_EN moment of the next PWM cycle. The theoretical message delay time is 250us+T3, where T3 represents the time difference from the start of message storage to the TX_EN moment of this PWM cycle. If the storage is completed and the forwarding moment has just passed, the delay is the largest. If the frame length is 1518Byte, the maximum delay is ((1518+8)*8 / 4 / 25+250)us = 372.08us, and the timing is as follows: Figure 5 shown.

[0016] Step 7, the message is sent to the collection execution unit; the GOOSE message from the protection device is sent to the FPGA (003) through the 100M optical Ethernet port Eth1 (007) of the autonomous controllable protection test system. After receiving the SV / GOOSE message, the FPGA (003) sends its data stream to two branches. The message of one branch (branch 3) is sent to the CPU (002) through Gigabit Ethernet (012) after being cached inside the FPGA (003). The message of the other branch (branch 4) is forwarded to the 100M optical Ethernet port Eth0 (005) of the autonomous controllable protection test system through transparent transmission and reaches the collection execution unit.

[0017] The advantage of the present invention over the existing technology is that after receiving the SV+GOOSE data sent by the acquisition execution unit, the SV data is automatically filtered out and only the GOOSE information is retained. The debugging personnel only need to increase the amount at the protection installation site to carry out the protection group test work; the strict real-time and time uniformity of the SV control block are guaranteed, and the GOOSE block has a small delay.

[0018] The specific embodiments described herein are merely examples of the spirit of the present invention. Those skilled in the art may make various modifications or additions to the specific embodiments described or replace them in similar ways, but they will not deviate from the spirit of the present invention or exceed the scope defined by the appended claims.

Claims

1. A whole group transmission test method of an autonomous controllable protection device based on common port transmission, characterized in that: The following steps are involved: Step 1: The acquisition execution unit (006) is connected to the optical Ethernet port Eth0 (005) of the autonomous controllable protection test system (001) through an optical fiber; Step 2: The protection device (007) is connected to the optical Ethernet port Eth1 (004) of the autonomous controllable protection test system (001) through an optical fiber; Step 3: Send the 100M Ethernet line speed 100Mbs at equal intervals according to the sampling rate of the SV message 4Khz, that is, send 3125 bytes every 250us, and then further divide each 250us into 2 time slots, each time slot can send a maximum of 1562 bytes; the time slot controller generates an INT_4K interrupt signal to the CPU (002); Step 4: After receiving the SV / GOOSE message from the acquisition execution unit (006), the 100M optical Ethernet port Eth0 (005) of the autonomous controllable protection test system (001) sends it to the FPGA (003). After receiving the SV / GOOSE message, the FPGA (003) sends its data stream to two branches. The message of one branch is sent to the CPU (002) through the Gigabit Ethernet (012) after being cached inside the FPGA (003); the message of the other branch is filtered and cached inside the FPGA (003); Step 5: Self-generated SV message sending. After receiving the message sent by Gigabit Ethernet (012), CPU (002) parses the message address, message type, APPID and payload information. The tester sends a configuration command through CPU (002). CPU (002) parses the configuration command and sends the filter parameters to FPGA (003) through EMA_BUS (008). Under the control of the INT_4K interrupt signal, CPU (002) generates SV data to be sent and sends it to FPGA (003) in DMA mode through PCIE data bus (009). Step 6: The message is sent to the protection device. Step 3 divides each 250us into two equal-length time slots. The first time slot completes the reading and sending of the SV message generated by the CPU (002). During the actual sending process of the SV message, the ping-pong mode is used to ensure the timing and integrity of the SV message. The second time slot completes the reading and sending of the BRAM cache filter message. The CPU (002) self-generated SV message and the BRAM cache filter message are both sent to the protection device through the optical Ethernet port Eth1 (004) of the autonomous and controllable new generation protection test system. Step 7: The message is sent to the collection execution unit. The GOOSE message from the protection device is sent to the FPGA (003) through the 100M optical Ethernet port Eth1 (007) of the autonomous and controllable new generation protection test system. After receiving the SV / GOOSE message, the FPGA (003) sends its data stream to two branches. The message of one branch is sent to the CPU (002) through Gigabit Ethernet (012) after being cached inside the FPGA (003). The message of the other branch is forwarded to the 100M optical Ethernet port Eth0 (005) of the autonomous and controllable protection test system (001) through transparent transmission and reaches the collection execution unit.

2. The whole group transmission test method of the autonomous controllable protection device based on common port transmission according to claim 1 is characterized in that: The optical network port is configured by the CPU to have the functions of SV message filtering, self-generated SV sending and transparent forwarding of GOOSE messages from the protection device. At the same time, it can also be configured as a common optical network port function.

3. The whole group transmission test method of the autonomous controllable protection device based on common port transmission according to claim 1 is characterized in that: The filtering and caching of the message in step 4 is controlled by a state machine. After the message reaches the filtering module inside the FPGA (003), the filtering module parses the message content and determines whether to filter it. At the same time, the message is stored in real time in the BRAM inside the FPGA (003). After the parsing of a frame of messages is completed, if the message is determined to be filtered, the BRAM write address is reset to the first address of the frame of messages, the FIFO is not written, and the writing of the frame is invalid. If it is determined that the message is not filtered, the FIFO writes the first address and message length of the message, and the frame write is valid.

4. The whole group transmission test method of the autonomous controllable protection device based on common port transmission according to claim 1 is characterized in that: Determining whether the message is filtered in step 4 includes the following steps: filtering according to the message type, after the filtering module receives the message type filtering enable signal and pulls up, it matches the message type flag in the message content according to the filtering type flag, and if the match is successful, outputs a filtering effective signal; filtering according to APPID, after the filtering module receives the APPID filtering enable signal and pulls up, it matches the APPID in the message content according to the APPID filtering word issued by the CPU (002), and if the match is successful, outputs a filtering effective signal.

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