CPO optical module packaging structure

Abstract

The utility model relates to the technical field of optical packaging, and specifically discloses a CPO optical module packaging structure comprising a housing assembly comprising a housing top part and a housing bottom part which are oppositely arranged; a substrate assembly over the bottom portion of the housing; the reconfiguration electric chip assembly is located on the side, away from the bottom part of the shell, of the substrate assembly and is in bonding connection with the substrate assembly; the optical chip assembly is inversely arranged on one side, deviating from the substrate assembly, of the reconstruction electric chip assembly and is at least electrically connected with a driver of the reconstruction electric chip assembly; the optical fiber array assembly is located on the side, away from the substrate assembly, of the reconstruction electric chip assembly; the heat conduction assembly at least comprises a first heat conduction gasket located between the reconstruction electric chip assembly and the top part of the shell and a second heat conduction gasket located between the reconstruction electric chip assembly and the bottom part of the shell. The CPO optical module packaging structure provided by the utility model has the advantage of high integration level.

Description

Technical Field

[0001] The utility model relates to the technical field of optical packaging, in particular to a CPO optical module packaging structure. Background Art

[0002] With the increase in the capacity of ASIC chips used in data centers and AI applications, the transmission rate of high-speed optical modules has developed from 100G Gbps to 800Gbps. For a single optical module, the number of optoelectronic chips on the internal PCB (Printed Circuit Board) and the number of internal channels have also increased dramatically. Under the premise of meeting the packaging standards of existing optical modules and switches, achieving multi-chip, high-integration, low-loss interconnection and manufacturing reliable, low-insertion-loss optical coupling packaging solutions that match the packaging design will be important technical challenges facing future optical modules and CPO (Co-packaged Optics) modules.

[0003] At present, the commonly used optical module products with a rate of more than 400Gbps mainly meet the module packaging standards related to QSFP and OSFP, and the width of the internal patch area is generally 16mm~18.5mm. At present, the maximum rate of the domestic mass-produced transmitting module chips (laser chips, modulator chips, driver chips) and receiving module chips (detectors, transimpedance amplifiers) is generally around 400Gbps. Therefore, with the increase in the capacity of switches, the increase in the number of optoelectronic chips and the size of single chips in incoherent optical modules with a rate of more than 800Gbps is an inevitable problem. At the same time, the interconnection of optoelectronic chips inside the optical module is still mainly based on the COB (Chip On Board, chip packaging on board) process. The wire bonding interconnection method often occupies a large space on the board, and the surge in the number of wires will also cause the accumulation of delays and power consumption.

[0004] Currently, advanced packaging is one of the solutions to increase the integration and number of I / O interfaces per unit area. However, since PIC (Photonics Integrated Circuit) is a heat-sensitive device with a small coupling tolerance, and the end coupler on the PIC is usually located at the edge of the chip, the current advanced packaging process is difficult to effectively protect the PIC optical port structure and difficult to adapt to a stable and reliable optical connection solution at the same time.

[0005] When studying the packaging form of optical modules, the inventors found that the loss and delay of existing high-speed optical modules are partly caused by the cumulative number of leads due to the increased integration; due to the COB mounting method, the pad type is mostly positive, so the area on the chip surface that can be used to attach the heat sink is relatively small.

[0006] Therefore, how to provide an optical module packaging structure with high integration and low loss becomes a technical problem that needs to be solved urgently by those skilled in the art. Summary of the invention

[0007] The utility model provides a CPO optical module packaging structure, which solves the problems of low integration and high loss existing in the related technology.

[0008] As one aspect of the utility model, a CPO optical module packaging structure is provided, which includes:

[0009] A housing assembly, comprising a housing top portion and a housing bottom portion disposed opposite to each other;

[0010] a substrate assembly, located on the bottom portion of the housing and connected to the bottom portion of the housing;

[0011] A reconstructed electric chip assembly is located on a side of the substrate assembly away from the bottom portion of the housing and is bonded to the substrate assembly, wherein the reconstructed electric chip assembly is formed by at least a photodetector, a transimpedance amplifier, and a driver being packaged together;

[0012] An optical chip component is flipped on a side of the reconstructed electric chip component away from the substrate component and is at least electrically connected to a driver of the reconstructed electric chip component;

[0013] An optical fiber array assembly is located on a side of the reconstructed electrical chip assembly away from the substrate assembly and is coupled and connected to the photodetector and the optical chip assembly respectively;

[0014] a thermally conductive assembly including at least a first thermally conductive pad between the reconstructed electrical chip assembly and the top portion of the housing and a second thermally conductive pad between the reconstructed electrical chip assembly and the bottom portion of the housing;

[0015] The top portion of the housing is located on a side of the reconstructed electrical chip assembly facing away from the substrate assembly and at least covers the optical chip assembly, the optical fiber array assembly and the first thermal conductive pad.

[0016] Furthermore, the reconstructed electric chip assembly includes:

[0017] The chip layer includes an injection molding material body, an electrical introduction unit embedded in the injection molding material body, and a photodetector, a transimpedance amplifier, and a driver arranged at intervals;

[0018] A first redistribution layer is connected to the upper surface of the chip layer, and can realize electrical connection between the photodetector and the electrical introduction unit, between the driver and the electrical introduction unit, and between the photodetector and the transimpedance amplifier; wherein the upper surface of the chip layer is a side of the reconstructed electrical chip component away from the substrate component;

[0019] A first electrical connection member, located on a surface of the first redistribution layer away from the chip layer and at least realizing an electrical connection between the driver and the optical chip assembly;

[0020] A second redistribution layer is connected to the lower surface of the chip layer and is electrically connected to the electrical introduction unit of the chip layer; wherein the lower surface of the chip layer is a side of the reconstructed electrical chip component facing the substrate component;

[0021] The second electrical connection component is located on a surface of the second redistribution layer away from the chip layer and at least realizes electrical connection between the reconstructed electrical chip component and the substrate component.

[0022] Furthermore, the optical chip assembly includes a chip body, an end face coupler formed on the chip body, and a third electrical connector, and the third electrical connector is in contact with the first electrical connector to achieve electrical connection between the driver and the optical chip assembly.

[0023] Furthermore, the optical fiber array assembly comprises a first optical fiber array assembly part and a second optical fiber array assembly part.

[0024] The first optical fiber array component is located on the surface of the reconstructed electrical chip component away from the substrate component, the first optical fiber array component is end-face coupled with the photodetector, a transparent dielectric material is filled in the coupling region between the first optical fiber array component and the photodetector, and no metal connection wire of the first redistribution layer exists in the coupling region;

[0025] The second optical fiber array component is partially located on the side of the optical chip component away from the first thermal conductive pad;

[0026] The first optical fiber array component is partially coupled to the photodetector, and the second optical fiber array component is partially coupled to the optical chip component.

[0027] Further, the substrate assembly includes a PCB board and a fourth electrical connection member formed on the surface of the PCB board;

[0028] The PCB board is formed with a stepped PCB through hole, and the stepped PCB through hole is filled with a metal heat sink material;

[0029] The fourth electrical connector contacts the second electrical connector of the reconstructed electric chip assembly to achieve electrical connection between the reconstructed electric chip assembly and the substrate assembly. The metal heat sink material contacts the reconstructed electric chip assembly and is located in the projection area of ​​the transimpedance amplifier and the driver.

[0030] The CPO optical module packaging structure provided by the utility model is composed of a shell component, a substrate component, a reconstructed electric chip component, an optical chip component, an optical fiber array component and a thermal conductive component packaging, and has the advantages of high integration, low loss and good heat dissipation performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present invention, but do not constitute a limitation to the present invention.

[0032] Figure 1 This is a cross-sectional view of the CPO optical module packaging structure provided by the utility model.

[0033] Figure 2 The present invention provides a flow chart of a method for preparing a CPO optical module packaging structure.

[0034] Figure 3 This is a schematic diagram of the structure of forming the first photosensitive release layer provided by the utility model.

[0035] Figure 4 This is a schematic diagram of the structure after the photoelectric detector, transimpedance amplifier and driver provided by the utility model are pasted.

[0036] Figure 5 The utility model provides Figure 4 Schematic diagram of the structure after filling with injection molding material based on.

[0037] Figure 6 The utility model provides Figure 5 Schematic diagram of the structure of the wafer after thinning.

[0038] Figure 7 The utility model provides Figure 6 Schematic diagram of the wafer structure after photodebonding and flipping.

[0039] Figure 8 The utility model provides Figure 7 Schematic diagram of the structure after spin coating the first PI glue on the structure basis.

[0040] Fig. 9 This is a schematic diagram of the structure of forming the second photosensitive release layer provided by the utility model.

[0041] Fig.10 This is a schematic diagram of the structure after spin coating of negative photoresist provided by the utility model.

[0042] Fig.11 This is a schematic structural diagram of an inverted trapezoidal window formed after development provided by the utility model.

[0043] Fig.12 This is a schematic diagram of the structure after the seed layer is evaporated provided by the utility model.

[0044] Fig.13 This is a schematic structural diagram of a copper column structure formed by electroplating provided by the utility model.

[0045] Fig.14 This is a schematic diagram of the structure after the negative photoresist provided by the utility model is removed.

[0046] Fig.15 This is a schematic diagram of the structure after the temporary co-sealed chip and the reconstructed electric chip support structure are pasted together provided by the utility model.

[0047] Fig.16 This is a schematic diagram of the structure after secondary injection molding of the material provided by the utility model.

[0048] Fig.17 This is a schematic diagram of the structure after thinning provided by the utility model.

[0049] Fig.18 This is a schematic diagram of the structure after spin coating the second PI glue and preparing the first redistribution layer provided by the utility model.

[0050] Fig.19 The utility model provides Fig.18 Schematic diagram of the structure after photodebonding of the structure.

[0051] Fig. 20 This is a schematic diagram of the structure after preparing the second redistribution layer provided by the utility model.

[0052] Fig.21 The utility model provides Fig. 20 Schematic diagram of the wafer structure after flipping.

[0053] Fig. 22 This is a schematic diagram of the structure after the optical chip component and the reconstructed electrical chip component are bonded together provided by the utility model.

[0054] Fig.23 This is a schematic diagram of the structure of forming stepped PCB through holes and PCB bumps on the PCB board provided by the utility model.

[0055] Fig.24A schematic diagram of the structure of filling a metal heat sink material in a stepped PCB through hole provided by the utility model.

[0056] Fig.25 The utility model provides Fig. 22 Schematic diagram of the structure after being bonded to the substrate assembly.

[0057] Fig.26 This is a schematic diagram of the structure after the base glue is filled provided by the utility model.

[0058] Fig. 27 This is a schematic diagram of the structure after the optical fiber array assembly provided by the utility model is assembled.

[0059] Fig.28 This is a structural schematic diagram of the housing assembly provided by the utility model.

[0060] Fig.29 The shell component, heat conduction component and Fig. 27 Schematic diagram of the structure for assembly.

[0061] Fig.30 The utility model provides a flow chart for preparing and reconstructing an electric chip assembly.

[0062] Fig.31 The utility model provides a flow chart for bonding an optical chip component to the reconstructed electrical chip component based on a flip-chip process.

[0063] Fig.32 A flow chart of bonding a first bonding component to a substrate component provided by the utility model.

[0064] Fig.33 A flow chart of assembling an optical fiber array assembly provided by the utility model. DETAILED DESCRIPTION

[0065] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present invention can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0066] In order to enable those skilled in the art to better understand the solution of the utility model, the technical solution in the embodiment of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiment of the utility model. Obviously, the described embodiment is only a part of the embodiment of the utility model, not all of the embodiments. Based on the embodiment of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the utility model.

[0067] It should be noted that the terms "first", "second", etc. in the specification and claims of the utility model and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so as to describe the embodiments of the utility model described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0068] In this embodiment, a CPO optical module packaging structure is provided. Figure 1 is a cross-sectional view of a CPO optical module packaging structure provided according to an embodiment of the utility model, such as Figure 1 As shown, including:

[0069] The housing assembly 100 includes a housing top portion 110 and a housing bottom portion 120 that are disposed opposite to each other;

[0070] The substrate assembly 200 is located on the housing bottom portion 120 and connected to the housing bottom portion 120;

[0071] The reconstructed electric chip component 300 is located on a side of the substrate component 200 away from the bottom portion 120 of the housing and is bonded to the substrate component 200, wherein the reconstructed electric chip component 300 is formed by at least a photodetector, a transimpedance amplifier and a driver being packaged together;

[0072] The optical chip assembly 400 is flip-mounted on a side of the reconstructed electrical chip assembly 300 away from the substrate assembly 200 and is at least electrically connected to a driver of the reconstructed electrical chip assembly 300;

[0073] The optical fiber array assembly 500 is located at a side of the reconstructed electrical chip assembly 300 away from the substrate assembly 200 and is coupled to the photodetector and the optical chip assembly 400 respectively;

[0074] The heat conducting assembly 600 includes at least a first heat conducting pad 610 located between the reconstructed electrical chip assembly 300 and the housing top portion 110 and a second heat conducting pad 620 located between the reconstructed electrical chip assembly 300 and the housing bottom portion 120;

[0075] The housing top portion 110 is located on a side of the reconstructed electrical chip assembly 300 away from the substrate assembly 200 , and covers at least the optical chip assembly 400 , the optical fiber array assembly 500 and the first thermal conductive pad 610 .

[0076] For the CPO optical module packaging structure, when working, the coupling connection between the optical fiber array component and the photodetector transmits the input light to the photodetector via the optical fiber array component to realize the light detection function, that is, converting the optical signal into an electrical signal; in addition, the electrical connection between the driver and the optical chip component enables the driver to drive the optical chip component to work, thereby transmitting the optical signal through the optical fiber array component. In the embodiment of the utility model, it is precisely because the optical fiber array component and the reconstructed electrical chip component are stacked structures arranged up and down, and the optical chip component is flip-chip mounted on the reconstructed electrical chip component, which can not only meet the normal operation of the CPO optical module packaging structure, but also improve the integration per unit area and reduce the packaging size.

[0077] Therefore, in the embodiment of the utility model, by packaging the photodetector, the transimpedance amplifier and the driver together to form a reconstructed electric chip assembly, the integration per unit area is effectively improved; in addition, by flipping the optical chip assembly on the reconstructed electric chip assembly, the package size can be further reduced and the integration of the package structure can be improved. In addition, by providing a heat-conducting assembly in the embodiment of the utility model, the package structure has two heat dissipation paths at its top and bottom, thereby improving the overall heat dissipation capacity of the package structure.

[0078] Therefore, the CPO optical module packaging structure provided by the utility model is composed of a shell component, a substrate component, a reconstructed electric chip component, an optical chip component, an optical fiber array component and a thermal conductive component. Since the reconstructed electric chip component forms a co-sealed chip of a photodetector, a transimpedance amplifier and a driver, the integration per unit area is improved, and the package size can be effectively reduced by the flip-chip setting of the optical chip component; in addition, the thermal conductive component can effectively improve the heat dissipation capacity. Therefore, the CPO optical module packaging structure provided by the utility model has the advantages of high integration, low loss and good heat dissipation performance.

[0079] In the embodiment of the present utility model, Figure 1 As shown, the reconstructed electrical chip assembly 300 includes:

[0080] The chip layer 310 includes an injection molding material body 311, an electrical introduction unit embedded in the injection molding material body 311, and a photodetector 313, a transimpedance amplifier 314, and a driver 315 arranged at intervals;

[0081] The first redistribution layer 320 is connected to the upper surface of the chip layer 310, and can respectively realize the electrical connection between the photodetector 313 and the electrical introduction unit, between the driver 315 and the electrical introduction unit, and between the photodetector 313 and the transimpedance amplifier 314; wherein the upper surface of the chip layer 310 is the side of the reconstructed electrical chip assembly 300 away from the substrate assembly 200;

[0082] A first electrical connection member 330 is located on a surface of the first redistribution layer 320 away from the chip layer 310 and at least realizes an electrical connection between the driver 315 and the optical chip assembly 400;

[0083] The second redistribution layer 340 is connected to the lower surface of the chip layer 310 and is electrically connected to the electrical introduction unit of the chip layer 310; wherein the lower surface of the chip layer 310 is the side of the reconstructed electrical chip assembly 300 facing the substrate assembly 200;

[0084] The second electrical connection component 350 is located on a surface of the second redistribution layer 340 away from the chip layer 310 , and at least realizes electrical connection between the reconstructed electrical chip assembly 300 and the substrate assembly 200 .

[0085] Specifically, the electrical introduction unit embedded in the injection molding material body 311 in the chip layer 310 is Figure 1 Take the first electrical introduction unit 312a and the second electrical introduction unit 312b shown in FIG as an example, Figure 1 The photodetector 313 , the transimpedance amplifier 314 and the driver 315 are located between the first electrical property introduction unit 312 a and the second electrical property introduction unit 312 b and are spaced apart from each other.

[0086] When the first redistribution layer 320 realizes electrical connection, Figure 1 Taking the structure shown as an example, the first redistribution layer 320 can realize the electrical connection between the first electrical introduction unit 312a and the photodetector 313, the electrical connection between the photodetector 313 and the transimpedance amplifier 314, the electrical introduction / extraction of the transimpedance amplifier 314, the introduction / extraction of the driver 315, and the electrical connection between the driver 315 and the second electrical introduction unit 312b.

[0087] by Figure 1 Taking the structure shown as an example, the first electrical connector 330 can realize electrical connection with the driver 315 and the first redistribution layer 320 corresponding to the second electrical introduction unit 312b. Specifically, in the embodiment of the utility model, the first electrical connector 330 can be a UBM Pad.

[0088] by Figure 1 Taking the structure shown as an example, the second redistribution layer 340 may specifically include a first portion 341 and a second portion 342, wherein the first portion 341 is electrically connected to the first electrical introduction unit 312a, and the second portion 342 is electrically connected to the second electrical introduction unit 312b.

[0089] by Figure 1 Taking the structure shown as an example, the second electrical connector 350 can be electrically connected to the first portion 341 and the second portion 342. Specifically, in the embodiment of the present invention, the second electrical connector 350 can be a UBM Pad.

[0090] It should be noted that, in the embodiment of the present utility model, the first electrical introduction unit 312a and the second electrical introduction unit 312b may specifically be copper column structures.

[0091] In the embodiment of the utility model, the reconstructed electric chip component 300 integrates a photodetector 313, a transimpedance amplifier 314 and a driver 315 on the chip layer 310, which effectively improves the integration of the reconstructed electric chip component. In addition, a first redistribution layer is set on the chip layer 310 to realize the electrical connection of the chip layer 310, and a first electrical connector 330 is set to realize the electrical connection between the first redistribution layer 320 and the chip layer 310, and a second redistribution layer 340 and a second electrical connector 350 are set to realize the electrical connection between the chip layer 310 and the substrate assembly 200, etc. Due to the setting of the first redistribution layer and the second redistribution layer, the connection lines of the electronic devices of the chip layer are wired in the metal layer at the top or bottom of the chip, thereby greatly saving size and space; in addition, a high-density interconnection structure can be realized, the delay and power consumption of signal transmission can be reduced, and the working performance of the circuit can be improved.

[0092] In the embodiment of the present utility model, Figure 1 As shown, the optical chip assembly 400 includes a chip body 410, an end face coupler 420 formed on the chip body 410, and a third electrical connector 430, wherein the third electrical connector 430 contacts the first electrical connector 330 to realize the electrical connection between the driver 315 and the optical chip assembly 400.

[0093] It should be understood that the optical chip assembly 400 can set the end coupler 420 on the chip body 410, and the end coupler 420 can be electrically connected to the reconstructed electrical chip assembly 300 through the third electrical connector 430 and the first electrical connector 330. Since the optical chip assembly 400 is electrically connected to the reconstructed electrical chip assembly 300 by a flip-chip process, the integration level can be further improved and the device size can be reduced.

[0094] In the embodiment of the present invention, the third electrical connection member 430 may specifically be a bump structure formed on the chip body 410 .

[0095] In the embodiment of the present utility model, the optical fiber array assembly 500 includes a first optical fiber array assembly part 510 and a second optical fiber array assembly part 520.

[0096] The first optical fiber array component part 510 is located on the surface of the reconstructed electrical chip component 300 away from the substrate component 200, the first optical fiber array component part 510 is end-face coupled with the photodetector 313, a transparent dielectric material is filled in the coupling region between the first optical fiber array component part 510 and the photodetector 313, and no metal connection wire of the first redistribution layer exists in the coupling region;

[0097] The second optical fiber array assembly portion 520 is located on the side of the optical chip assembly 400 away from the first thermal conductive pad 610;

[0098] The first optical fiber 530 is used as an incident optical fiber to transmit the received optical signal to the first optical fiber array component part 510, and the first optical fiber array component part 510 transmits the received optical signal to the first optical fiber array component part 510. Figure 1 The bend path in the optical chip assembly 400 changes the propagation direction of the optical signal, causing the optical signal to propagate downward. Since the first optical fiber array component part 510 is coupled to the photodetector 400, the received optical signal is then propagated to the photodetector 313 via the first optical fiber array component part 510; since the optical chip assembly 400 is coupled to the second optical fiber array component part 520, the optical signal in the optical chip assembly 400 can propagate to the second optical fiber array component part 520, and then propagate to the second optical fiber 540, and the optical signal is output via the second optical fiber 540.

[0099] Specifically, in the embodiment of the present utility model, combined with Figure 1As shown, after the first optical fiber 530 is horizontally connected to the first optical fiber array component part 510 as an incident optical fiber, it is converted into an optical signal transmitted vertically downward through the bend in the first optical fiber array component part 510. Based on the end face coupling between the first optical fiber array component part 510 and the photodetector 313, the optical signal is transmitted to the photodetector 313, and then the photodetector performs photoelectric conversion to obtain an electrical signal. In order to realize the coupling function between the photodetector 313 and the first optical fiber array component part 510, the first dielectric layer in the coupling area between the photodetector 313 and the first optical fiber array component part 510 is filled with a transparent dielectric material, and the metal connecting wire of the first redistribution layer is not set in the coupling area. In addition, the electrical connection between the driver and the optical chip component realizes the work of the driver driving the optical chip component, and the optical chip component and the second optical fiber array component part 520 are coupled and connected through the second optical fiber 540. The second optical fiber 540, as an output optical fiber, can emit the optical signal output by the optical chip component.

[0100] Therefore, the first optical fiber array component part and the reconstructed optical chip component in the embodiment of the utility model are stacked up and down, the first optical fiber array component part is coupled to the photodetector in the reconstructed optical chip component, and the optical signal from the first optical fiber received by the first optical fiber array component part is converted into an optical signal transmitted toward the photodetector after passing through the bend arranged inside the first optical fiber array component part, and the coupling area between the photodetector and the first optical fiber array component part (including the first medium layer and the part between the photodetector and the first optical fiber array component part) is filled with transparent medium material, which not only realizes the function of the photodetector in the CPO optical module packaging structure, but also can effectively improve the integration per unit area; in addition, by flipping the optical chip component on the reconstructed electrical chip component, the package size can be further reduced and the integration of the CPO optical module packaging structure can be improved.

[0101] like Figure 1 As shown, the first optical fiber array component part 510 is located on the surface of the reconstructed electrical chip component away from the substrate component, and is located above the photodetector 313 in the reconstructed electrical chip component 300. Specifically, whether the first optical fiber array component part 510 is located above or directly above the photodetector 313, or how much position deviation there is, needs to be determined according to the positions of the light outlet of the first optical fiber array component part 510 and the light inlet of the photodetector 313, so as to ensure that the light outlet of the first optical fiber array component part 510 is coupled and connected with the light inlet of the photodetector 313.

[0102] In the embodiment of the utility model, the second optical fiber array component part 520 is located on the outer side of the optical chip component, and the first thermal conductive gasket 610 is located on the inner side of the optical chip component, that is, the second optical fiber array component part 520 is located on the side of the optical chip component 400 away from the first thermal conductive gasket 610.

[0103] Specifically, the optical fiber array assembly 500 further includes a glass cover plate 550, which is located between the housing top portion 110 and the reconstructed electrical chip assembly 300, and the glass cover plate 550 at least covers the second optical fiber array assembly portion 520 and a portion of the optical chip assembly 400. Figure 1 As shown, the glass cover 550 is located directly above the second optical fiber array assembly part 520 , and can not only cover the second optical fiber array assembly part 520 , but also cover a portion of the optical chip assembly 400 .

[0104] In the embodiment of the present utility model, Figure 1 As shown, the substrate assembly 200 includes a PCB board 210 and a fourth electrical connection member 220 formed on the surface of the PCB board 210;

[0105] The PCB board 210 is formed with a stepped PCB through hole 211, and the stepped PCB through hole 211 is filled with a metal heat sink material;

[0106] The fourth electrical connector 220 contacts the second electrical connector 350 of the reconstructed electric chip assembly 300 to achieve electrical connection between the reconstructed electric chip assembly and the substrate assembly. The metal heat sink material contacts the reconstructed electric chip assembly 300 and is located in the projection area of ​​the transimpedance amplifier and the driver.

[0107] It should be understood that in the embodiment of the utility model, the substrate assembly 200 includes a PCB board 210 and a fourth electrical connector 220, and the fourth electrical connector 220 realizes the electrical connection between the substrate assembly 200 and the reconstructed electric chip assembly 300; a stepped PCB through hole 211 is formed on the PCB board 210, and the PCB through hole 211 is filled with a metal heat sink material, which can effectively improve the heat dissipation capacity of the substrate assembly. Specifically, as an optional embodiment, the projection of the stepped PCB through hole 211 near the stepped PCB through hole of the reconstructed electric chip assembly 300 at least partially overlaps with the projection of the transimpedance amplifier and the driver on the surface.

[0108] In the embodiment of the present utility model, the fourth electrical connection member 220 may specifically be a PCB bump.

[0109] Specifically, the PCB through hole 211 formed in the middle of the PCB board can be filled with tungsten-copper heat sink material, and the second thermal conductive gasket 620 corresponds to the bottom of the PCB through hole 211. The heat generated by the reconstructed electric chip assembly 300 is transferred to the second thermal conductive gasket 620 through the heat sink material filled in the PCB through hole 211, thereby effectively improving the heat dissipation capacity of the CPO optical module packaging structure.

[0110] In addition, in order to fix the housing assembly 100, a threaded hole can be set on the housing bottom part 120, and a threaded hole can be set on the PCB board 210 at a corresponding position of the housing bottom part 120, and the housing bottom part 120 is connected to the substrate assembly 200 by tightening screws.

[0111] In summary, the CPO optical module packaging structure provided by the present invention can not only effectively improve the integration, but also reduce the loss and improve the heat dissipation capacity of the CPO optical module packaging structure.

[0112] As another aspect of the present invention, a method for preparing a CPO optical module packaging structure is provided, which is used to prepare the CPO optical module packaging structure described above, wherein: Figure 2 As shown, the preparation method comprises:

[0113] S100, preparing a reconstructed electric chip component based on a fan-out process, wherein the reconstructed electric chip component is formed by at least a photodetector, a transimpedance amplifier, and a driver being packaged together;

[0114] In the embodiment of the utility model, the reconstructed electric chip assembly is prepared based on the fan-out process, and a packaging structure with low power loss can be formed by using a high-density wiring manufacturing process.

[0115] Specifically, based on the fan-out process, a reconstructed electric chip component is prepared, such as Fig.30 As shown, including:

[0116] S110, providing a first temporary substrate, and pasting a photodetector, a transimpedance amplifier, and a driver on the first temporary substrate to obtain a temporary co-sealed chip;

[0117] like Figure 3 As shown, a first temporary substrate 1 is provided, and a photo-release adhesive is spin-coated on the first temporary substrate 1 to form a first photo-release layer 2 .

[0118] like Figure 4 As shown, the photodetector 313, the transimpedance amplifier 314 and the driver 315 are pasted in a face-down manner.

[0119] like Figure 5 As shown, the injection molding process is used to Figure 4The surface of the wafer structure shown is filled with a primary injection molding material 6 to achieve plastic sealing, cover the back side of the chip and the surrounding space, and complete thermal curing.

[0120] like Figure 6 As shown, after injection molding Figure 5 The wafer structure shown is thinned until the substrate material on the back side of all chips is exposed, that is, until the substrate material on the back side of the photodetector 313 , the transimpedance amplifier 314 and the driver 315 is exposed.

[0121] like Figure 7 As shown, UV light is used to perform photodebonding on the co-sealed wafer, and the structure after photodebonding is flipped.

[0122] like Figure 8 As shown, the first PI glue 7 is spin-coated on the flipped wafer surface (ie, the PAD side of the photodetector 313 , the transimpedance amplifier 314 , and the driver 315 ) and cured to obtain a temporary co-sealed chip 8 .

[0123] S120, providing a second temporary substrate, and preparing an electrical introduction unit on the second temporary substrate to obtain a reconstructed electric chip support structure;

[0124] In the embodiment of the present utility model, the reconstructed electric chip support structure is obtained by preparing an electrical introduction unit on the second temporary substrate.

[0125] Specifically, Fig. 9 As shown, a second temporary substrate 3 is provided, and a photo-release adhesive is spin-coated on the second temporary substrate 3 to form a second photo-release layer 9 .

[0126] like Fig.10 As shown, two layers of negative photoresist 10 are spin-coated on the second photo-release layer 9 .

[0127] like Fig.11 As shown, a developer is used to open an inverted trapezoidal notch 11 in the negative photoresist.

[0128] like Fig.12 As shown, a Ti / Cu thin layer is evaporated in the inverted trapezoidal notch 11 as a seed layer 12 .

[0129] like Fig.13 As shown, in Fig.12 Electroplating is performed on the seed layer 12 in the embodiment to form a copper column structure, so as to form electrical introduction units (a first electrical introduction unit 312 a and a second electrical introduction unit 312 b ).

[0130] like Fig.14 As shown, Fig.13The reconstructed electric chip support structure 14 is obtained by partially or completely removing the two layers of negative photoresist in the wafer. Whether to remove all or part of the two layers of negative photoresist can be operated according to actual needs, and this solution does not make specific restrictions on it.

[0131] S130, pasting the temporary co-sealed chip on the reconstructed electric chip support structure, so that the photodetector, the transimpedance amplifier, the driver and the electrical introduction unit are located together on the reconstructed electric chip support structure;

[0132] In the embodiment of the present utility model, Figure 8 The temporary co-sealed chip 8 is shown to be adhered to the reconstructed electric chip supporting structure 14 .

[0133] Specifically, in the embodiment of the utility model, the electrical introduction unit is Figure 1 Take the first electrical introduction unit 312a and the second electrical introduction unit 312b shown in FIG as an example, Figure 1 The photodetector 313, transimpedance amplifier 314 and driver 315 are located between the first electrical introduction unit 312a and the second electrical introduction unit 312b and are arranged at intervals. Specifically, the first electrical introduction unit 312a and the second electrical introduction unit 312b can be copper column structures. Fig.15 As shown, the temporary co-sealed chip 8 is pasted in a face-up manner to the area between the copper pillar structures of the reconstructed electric chip support structure 14 .

[0134] like Fig.16 As shown, the pasted wafer structure is filled with secondary injection molding material 15.

[0135] S140, performing injection molding and thinning on the wafer structure formed by pasting the temporary co-sealed chip and the reconstructed electric chip support structure to form a chip layer;

[0136] like Fig.17 As shown, the wafer structure filled with the secondary injection molding material 15 is thinned until the PI glue on the surface of the electrical introduction unit and the temporary co-sealed chip 8 are exposed at the same time, thereby obtaining a chip layer.

[0137] S150, sequentially forming a first redistribution layer and a first electrical connector on the upper surface of the chip layer, wherein the first redistribution layer can respectively realize electrical connection between the photodetector and the electrical introduction unit, between the driver and the electrical introduction unit, and between the photodetector and the transimpedance amplifier; wherein the upper surface of the chip layer is a side of the temporary co-sealed chip away from the reconstructed electrical chip support structure; the first electrical connector is located on the surface of the first redistribution layer away from the chip layer, and at least realizes electrical connection between the driver and the optical chip assembly;

[0138] like Fig.18 As shown, in Fig.17 After the second PI glue 18 is spin-coated on the surface of the thinned wafer structure, a first redistribution layer 320 is prepared, and contact holes 16 are formed on the first electrical introduction unit 312a and the second electrical introduction unit 312b, respectively, to be electrically connected to the first redistribution layer 320. In addition, a first electrical connector 330 is formed on the first redistribution layer 320, and the first electrical connector 330 is located at a position of the first redistribution layer away from the driver, and at a position of the first redistribution layer away from the second electrical introduction unit 312b.

[0139] Fig.18 The second PI glue 18 shown can cover the first redistribution layer and the chip layer. In the actual process, the coverage range of the second PI glue 18 can be set according to actual needs, and this solution does not make any specific limitations on it.

[0140] like Fig.19 As shown, Fig.18 The structure shown is subjected to photodebonding, that is, the second photorelease layer 9 and the second temporary substrate base plate 3 on the back side of the chip layer are removed.

[0141] S160. A second redistribution layer and a second electrical connection member are sequentially formed on the lower surface of the chip layer, and the second redistribution layer is electrically connected to the electrical introduction unit; wherein the second electrical connection member is located on the surface of the second redistribution layer away from the chip layer, and at least realizes the electrical connection between the reconstructed electrical chip component and the substrate component.

[0142] like Fig. 20 As shown, the second photorelease layer 9 is removed from the chip layer, and the third PI glue 20 is spin-coated on the surface of the second temporary substrate 3 (i.e., the lower surface of the chip layer), and a second redistribution layer 340 and a second electrical connector 350 are prepared, wherein the second redistribution layer 340 includes a first portion 341 formed at the position of the first electrical introduction unit 312a, and a second portion 342 formed at the position of the second electrical introduction unit 312b, and second electrical connectors 350 are formed on the first portion 341 and the second portion 342, respectively.

[0143] The third PI glue 20 spin-coated on the lower surface of the chip layer can cover the second redistribution layer 340 and the second electrical connection member 350 .

[0144] S200, bonding the optical chip assembly to the reconstructed electrical chip assembly based on a flip-chip process to obtain a first bonding assembly;

[0145] In the embodiment of the present utility model, Fig.21 As shown, Fig. 20 Schematic diagram of the wafer structure after flipping.

[0146] Specifically, the optical chip component is bonded to the reconstructed electrical chip component based on a flip-chip process, such as Fig.31 As shown, including:

[0147] S210, providing an optical chip assembly, wherein the optical chip assembly includes a chip body, an end face coupler formed on the chip body, and a third electrical connection member;

[0148] like Fig. 22 As shown, the optical chip assembly 400 includes a chip body 410 , an end face coupler 420 formed on the chip body 410 , and a third electrical connection member 430 .

[0149] S220, bonding the optical chip assembly to the reconstructed electrical chip assembly based on a flip-chip process, wherein the third electrical connector contacts the first electrical connector of the reconstructed electrical chip assembly to achieve electrical connection between the driver and the optical chip assembly.

[0150] like Fig. 22 As shown, the optical chip assembly 400 is bonded to the reconstructed electrical chip assembly 300 based on a flip-chip process, wherein the third electrical connection member 430 contacts the first electrical connection member 330 to achieve electrical connection.

[0151] S300, bonding the first bonding component to a substrate component to obtain a second bonding component;

[0152] In an embodiment of the utility model, a substrate assembly is provided, and the first bonding assembly is bonded to the substrate assembly.

[0153] Specifically, the first bonding component is bonded to the substrate component, such as Fig.32 As shown, including:

[0154] S310, provide PCB board;

[0155] S320, forming a stepped PCB through hole on the PCB board, and forming a fourth electrical connection member on the surface of the PCB board;

[0156] like Fig.23 As shown, a stepped PCB through hole 211 is formed on the PCB board 210, and a ball planting process is performed at the PCB PAD 230 position on the surface of the PCB board 210 to obtain a fourth electrical connector 220. At the same time, in order to achieve connection and fixation with the housing assembly 100, a plurality of first threaded holes 212 are also formed on the PCB board 210.

[0157] S330, filling the stepped PCB through hole with a metal heat sink material 240 to form a substrate assembly;

[0158] like Fig.24 As shown, the stepped PCB through hole 211 is filled with a metal heat sink material. Specifically, in the embodiment of the utility model, a tungsten-copper heat sink material is filled, and the tungsten-copper heat sink material is bonded to the PCB board 210 .

[0159] S340, bonding the first bonding component to the substrate component 230, wherein the fourth electrical connector contacts the second electrical connector of the reconstructed electric chip component to achieve electrical connection between the reconstructed electric chip component and the substrate component, and the metal heat sink material contacts the reconstructed electric chip component and is located in the projection area of ​​the transimpedance amplifier and the driver.

[0160] like Fig.25 As shown, Fig. 20 The first bonded assembly obtained is bonded on Fig.24 The fourth electrical connector 220 is in contact with the second electrical connector 350 to achieve electrical connection between the first bonding component and the substrate component. The metal heat sink material of the substrate component is in contact with the reconstructed electrical chip component to achieve heat dissipation function for the CPO optical module packaging component.

[0161] like Fig.26 As shown, the gap between the substrate component and the first bonding component is filled with the first primer 33, and the gap between the optical chip component and the reconstructed electric chip component is filled with the second primer 32, and thermal curing is completed.

[0162] S400, assembling an optical fiber array assembly on a side of the first bonding assembly facing away from the substrate assembly, so that the optical fiber array assembly is coupled and connected to the photodetector and the optical chip assembly respectively;

[0163] In the embodiment of the present utility model, Fig.26 The optical fiber array assembly is assembled based on the structure shown.

[0164] Specifically, the optical fiber array assembly is assembled on the side of the first bonding assembly away from the substrate assembly, such as Fig.33As shown, including:

[0165] S410, assembling a first optical fiber array component part on a surface of the first bonding component away from the substrate component, the first optical fiber array component part and the photodetector are end-face coupled, a transparent dielectric material is filled in a coupling region between the first optical fiber array component part and the photodetector, and no metal connecting wires of the first redistribution layer exist in the coupling region;

[0166] S420, assembling a second optical fiber array assembly part on a side of the optical chip assembly away from the first optical fiber array assembly part;

[0167] The first optical fiber array component is partially coupled to the photodetector, and the second optical fiber array component is partially coupled to the optical chip component.

[0168] like Fig. 27 As shown, the first optical fiber array component part 510 on the top surface of the photodetector is coupled and pasted at the corresponding position by active coupling, and pre-curing is completed by UV glue; then the horizontally emitted first optical fiber 530 is coupled with the end face of the optical chip component, and the glass carrier 550 is glued on the top surface of the optical chip component 400 and the top surface of the second optical fiber array component part 520, and pre-curing is completed by UV glue; the pre-cured optical module is sent into a high-temperature oven to complete the final glue curing.

[0169] S500, assembling the second bonding component after assembling the optical fiber array component, the housing component and the heat conduction component together to obtain a CPO optical module packaging structure.

[0170] like Fig.28 , which is a schematic structural diagram of a housing assembly 100 , specifically includes a housing top portion 110 and a housing bottom portion 120 that are relatively arranged. As an optional embodiment, a plurality of second threaded holes 40 are formed on the housing bottom portion 120 .

[0171] like Fig.29 As shown, the second thermally conductive pad 620 is pasted on the bottom portion 120 of the housing, and thermally conductive silicone grease is applied to the surface of the second thermally conductive pad 620 away from the bottom portion 120 of the housing. Fig. 27 The structure shown is assembled with the bottom part 120 of the housing and can be fastened by passing the fastening screws 39 through the first threaded hole on the PCB board and the second threaded hole on the bottom part 120 of the housing to achieve the fit and fixation of the PCB board and the bottom part of the housing.

[0172] A first thermal conductive pad 610 is pasted on the top of the region of the transimpedance amplifier and the driver on the upper surface of the chip layer, and the top portion 110 of the housing is assembled to complete the packaging of the CPO optical module and obtain a CPO optical module packaging structure.

[0173] In summary, the preparation method of the CPO optical module packaging structure provided by the utility model obtains a reconstructed electric chip component through a fan-out process and a rewiring process, and obtains an optical chip component through a flip-chip process, thereby improving the integration of the reconstructed electric chip component and the optical chip component and reducing the device size; in addition, thermal pads are provided on the upper and lower surfaces of the chip layer, and a metal heat sink material is filled on the substrate assembly to connect the chip and the second thermal pad to improve the heat dissipation capacity of the substrate, thereby effectively improving the heat dissipation capacity of the entire module. Therefore, the CPO optical module packaging structure obtained by the preparation method provided by the utility model effectively improves the integration and heat dissipation performance of the CPO optical module packaging structure.

[0174] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present invention, but the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A CPO optical module packaging structure, It is characterized in that include: A housing assembly, comprising a housing top portion and a housing bottom portion disposed opposite to each other; a substrate assembly, located on the bottom portion of the housing and connected to the bottom portion of the housing; A reconstructed electric chip assembly is located on a side of the substrate assembly away from the bottom portion of the housing and is bonded to the substrate assembly, wherein the reconstructed electric chip assembly is formed by at least a photodetector, a transimpedance amplifier, and a driver being packaged together; An optical chip component is flipped on a side of the reconstructed electric chip component away from the substrate component and is at least electrically connected to a driver of the reconstructed electric chip component; An optical fiber array assembly is located on a side of the reconstructed electrical chip assembly away from the substrate assembly and is coupled and connected to the photodetector and the optical chip assembly respectively; a thermally conductive assembly including at least a first thermally conductive pad between the reconstructed electrical chip assembly and the top portion of the housing and a second thermally conductive pad between the reconstructed electrical chip assembly and the bottom portion of the housing; The top portion of the housing is located on a side of the reconstructed electrical chip assembly facing away from the substrate assembly and at least covers the optical chip assembly, the optical fiber array assembly and the first thermal conductive pad.

2. The CPO optical module packaging structure according to claim 1, It is characterized in that The reconstructed electric chip assembly comprises: The chip layer includes an injection molding material body, an electrical introduction unit embedded in the injection molding material body, and a photodetector, a transimpedance amplifier, and a driver arranged at intervals; A first redistribution layer is connected to the upper surface of the chip layer, and can realize electrical connection between the photodetector and the electrical introduction unit, between the driver and the electrical introduction unit, and between the photodetector and the transimpedance amplifier; wherein the upper surface of the chip layer is a side of the reconstructed electrical chip component away from the substrate component; A first electrical connection member, located on a surface of the first redistribution layer away from the chip layer and at least realizing an electrical connection between the driver and the optical chip assembly; A second redistribution layer is connected to the lower surface of the chip layer and is electrically connected to the electrical introduction unit of the chip layer; wherein the lower surface of the chip layer is a side of the reconstructed electrical chip component facing the substrate component; The second electrical connection component is located on a surface of the second redistribution layer away from the chip layer and at least realizes electrical connection between the reconstructed electrical chip component and the substrate component.

3. The CPO optical module packaging structure according to claim 2, It is characterized in that The optical chip assembly includes a chip body, an end face coupler formed on the chip body, and a third electrical connection member, wherein the third electrical connection member contacts the first electrical connection member to achieve electrical connection between the driver and the optical chip assembly.

4. The CPO optical module packaging structure according to claim 1, It is characterized in that The optical fiber array assembly comprises a first optical fiber array assembly part and a second optical fiber array assembly part, The first optical fiber array component is located on the surface of the reconstructed electrical chip component away from the substrate component, the first optical fiber array component is end-face coupled with the photodetector, a transparent dielectric material is filled in the coupling region between the first optical fiber array component and the photodetector, and no metal connection wire of the first redistribution layer exists in the coupling region; The second optical fiber array component is partially located on the side of the optical chip component away from the first thermal conductive pad; The first optical fiber array component is partially coupled to the photodetector, and the second optical fiber array component is partially coupled to the optical chip component.

5. The CPO optical module packaging structure according to claim 1, It is characterized in that The substrate assembly includes a PCB board and a fourth electrical connection member formed on the surface of the PCB board; The PCB board is formed with a stepped PCB through hole, and the stepped PCB through hole is filled with a metal heat sink material; The fourth electrical connector contacts the second electrical connector of the reconstructed electric chip assembly to achieve electrical connection between the reconstructed electric chip assembly and the substrate assembly. The metal heat sink material contacts the reconstructed electric chip assembly and is located in the projection area of ​​the transimpedance amplifier and the driver.

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